max8998-irq.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Interrupt controller support for MAX8998
  4. //
  5. // Copyright (C) 2010 Samsung Electronics Co.Ltd
  6. // Author: Joonyoung Shim <[email protected]>
  7. #include <linux/device.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/mfd/max8998-private.h>
  12. struct max8998_irq_data {
  13. int reg;
  14. int mask;
  15. };
  16. static struct max8998_irq_data max8998_irqs[] = {
  17. [MAX8998_IRQ_DCINF] = {
  18. .reg = 1,
  19. .mask = MAX8998_IRQ_DCINF_MASK,
  20. },
  21. [MAX8998_IRQ_DCINR] = {
  22. .reg = 1,
  23. .mask = MAX8998_IRQ_DCINR_MASK,
  24. },
  25. [MAX8998_IRQ_JIGF] = {
  26. .reg = 1,
  27. .mask = MAX8998_IRQ_JIGF_MASK,
  28. },
  29. [MAX8998_IRQ_JIGR] = {
  30. .reg = 1,
  31. .mask = MAX8998_IRQ_JIGR_MASK,
  32. },
  33. [MAX8998_IRQ_PWRONF] = {
  34. .reg = 1,
  35. .mask = MAX8998_IRQ_PWRONF_MASK,
  36. },
  37. [MAX8998_IRQ_PWRONR] = {
  38. .reg = 1,
  39. .mask = MAX8998_IRQ_PWRONR_MASK,
  40. },
  41. [MAX8998_IRQ_WTSREVNT] = {
  42. .reg = 2,
  43. .mask = MAX8998_IRQ_WTSREVNT_MASK,
  44. },
  45. [MAX8998_IRQ_SMPLEVNT] = {
  46. .reg = 2,
  47. .mask = MAX8998_IRQ_SMPLEVNT_MASK,
  48. },
  49. [MAX8998_IRQ_ALARM1] = {
  50. .reg = 2,
  51. .mask = MAX8998_IRQ_ALARM1_MASK,
  52. },
  53. [MAX8998_IRQ_ALARM0] = {
  54. .reg = 2,
  55. .mask = MAX8998_IRQ_ALARM0_MASK,
  56. },
  57. [MAX8998_IRQ_ONKEY1S] = {
  58. .reg = 3,
  59. .mask = MAX8998_IRQ_ONKEY1S_MASK,
  60. },
  61. [MAX8998_IRQ_TOPOFFR] = {
  62. .reg = 3,
  63. .mask = MAX8998_IRQ_TOPOFFR_MASK,
  64. },
  65. [MAX8998_IRQ_DCINOVPR] = {
  66. .reg = 3,
  67. .mask = MAX8998_IRQ_DCINOVPR_MASK,
  68. },
  69. [MAX8998_IRQ_CHGRSTF] = {
  70. .reg = 3,
  71. .mask = MAX8998_IRQ_CHGRSTF_MASK,
  72. },
  73. [MAX8998_IRQ_DONER] = {
  74. .reg = 3,
  75. .mask = MAX8998_IRQ_DONER_MASK,
  76. },
  77. [MAX8998_IRQ_CHGFAULT] = {
  78. .reg = 3,
  79. .mask = MAX8998_IRQ_CHGFAULT_MASK,
  80. },
  81. [MAX8998_IRQ_LOBAT1] = {
  82. .reg = 4,
  83. .mask = MAX8998_IRQ_LOBAT1_MASK,
  84. },
  85. [MAX8998_IRQ_LOBAT2] = {
  86. .reg = 4,
  87. .mask = MAX8998_IRQ_LOBAT2_MASK,
  88. },
  89. };
  90. static inline struct max8998_irq_data *
  91. irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
  92. {
  93. return &max8998_irqs[data->hwirq];
  94. }
  95. static void max8998_irq_lock(struct irq_data *data)
  96. {
  97. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  98. mutex_lock(&max8998->irqlock);
  99. }
  100. static void max8998_irq_sync_unlock(struct irq_data *data)
  101. {
  102. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  103. int i;
  104. for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
  105. /*
  106. * If there's been a change in the mask write it back
  107. * to the hardware.
  108. */
  109. if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
  110. max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
  111. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
  112. max8998->irq_masks_cur[i]);
  113. }
  114. }
  115. mutex_unlock(&max8998->irqlock);
  116. }
  117. static void max8998_irq_unmask(struct irq_data *data)
  118. {
  119. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  120. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
  121. max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
  122. }
  123. static void max8998_irq_mask(struct irq_data *data)
  124. {
  125. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  126. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
  127. max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
  128. }
  129. static struct irq_chip max8998_irq_chip = {
  130. .name = "max8998",
  131. .irq_bus_lock = max8998_irq_lock,
  132. .irq_bus_sync_unlock = max8998_irq_sync_unlock,
  133. .irq_mask = max8998_irq_mask,
  134. .irq_unmask = max8998_irq_unmask,
  135. };
  136. static irqreturn_t max8998_irq_thread(int irq, void *data)
  137. {
  138. struct max8998_dev *max8998 = data;
  139. u8 irq_reg[MAX8998_NUM_IRQ_REGS];
  140. int ret;
  141. int i;
  142. ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
  143. MAX8998_NUM_IRQ_REGS, irq_reg);
  144. if (ret < 0) {
  145. dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
  146. ret);
  147. return IRQ_NONE;
  148. }
  149. /* Apply masking */
  150. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
  151. irq_reg[i] &= ~max8998->irq_masks_cur[i];
  152. /* Report */
  153. for (i = 0; i < MAX8998_IRQ_NR; i++) {
  154. if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
  155. irq = irq_find_mapping(max8998->irq_domain, i);
  156. if (WARN_ON(!irq)) {
  157. disable_irq_nosync(max8998->irq);
  158. return IRQ_NONE;
  159. }
  160. handle_nested_irq(irq);
  161. }
  162. }
  163. return IRQ_HANDLED;
  164. }
  165. int max8998_irq_resume(struct max8998_dev *max8998)
  166. {
  167. if (max8998->irq && max8998->irq_domain)
  168. max8998_irq_thread(max8998->irq, max8998);
  169. return 0;
  170. }
  171. static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
  172. irq_hw_number_t hw)
  173. {
  174. struct max8997_dev *max8998 = d->host_data;
  175. irq_set_chip_data(irq, max8998);
  176. irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
  177. irq_set_nested_thread(irq, 1);
  178. irq_set_noprobe(irq);
  179. return 0;
  180. }
  181. static const struct irq_domain_ops max8998_irq_domain_ops = {
  182. .map = max8998_irq_domain_map,
  183. };
  184. int max8998_irq_init(struct max8998_dev *max8998)
  185. {
  186. int i;
  187. int ret;
  188. struct irq_domain *domain;
  189. if (!max8998->irq) {
  190. dev_warn(max8998->dev,
  191. "No interrupt specified, no interrupts\n");
  192. return 0;
  193. }
  194. mutex_init(&max8998->irqlock);
  195. /* Mask the individual interrupt sources */
  196. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
  197. max8998->irq_masks_cur[i] = 0xff;
  198. max8998->irq_masks_cache[i] = 0xff;
  199. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
  200. }
  201. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
  202. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
  203. domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
  204. max8998->irq_base, &max8998_irq_domain_ops, max8998);
  205. if (!domain) {
  206. dev_err(max8998->dev, "could not create irq domain\n");
  207. return -ENODEV;
  208. }
  209. max8998->irq_domain = domain;
  210. ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
  211. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  212. "max8998-irq", max8998);
  213. if (ret) {
  214. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  215. max8998->irq, ret);
  216. return ret;
  217. }
  218. if (!max8998->ono)
  219. return 0;
  220. ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
  221. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
  222. IRQF_ONESHOT, "max8998-ono", max8998);
  223. if (ret)
  224. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  225. max8998->ono, ret);
  226. return 0;
  227. }
  228. void max8998_irq_exit(struct max8998_dev *max8998)
  229. {
  230. if (max8998->ono)
  231. free_irq(max8998->ono, max8998);
  232. if (max8998->irq)
  233. free_irq(max8998->irq, max8998);
  234. }