lpc_sch.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * lpc_sch.c - LPC interface for Intel Poulsbo SCH
  4. *
  5. * LPC bridge function of the Intel SCH contains many other
  6. * functional units, such as Interrupt controllers, Timers,
  7. * Power Management, System Management, GPIO, RTC, and LPC
  8. * Configuration Registers.
  9. *
  10. * Copyright (c) 2010 CompuLab Ltd
  11. * Copyright (c) 2014 Intel Corp.
  12. * Author: Denis Turischev <[email protected]>
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/errno.h>
  17. #include <linux/acpi.h>
  18. #include <linux/pci.h>
  19. #include <linux/mfd/core.h>
  20. #define SMBASE 0x40
  21. #define SMBUS_IO_SIZE 64
  22. #define GPIO_BASE 0x44
  23. #define GPIO_IO_SIZE 64
  24. #define GPIO_IO_SIZE_CENTERTON 128
  25. #define WDTBASE 0x84
  26. #define WDT_IO_SIZE 64
  27. enum sch_chipsets {
  28. LPC_SCH = 0, /* Intel Poulsbo SCH */
  29. LPC_ITC, /* Intel Tunnel Creek */
  30. LPC_CENTERTON, /* Intel Centerton */
  31. LPC_QUARK_X1000, /* Intel Quark X1000 */
  32. };
  33. struct lpc_sch_info {
  34. unsigned int io_size_smbus;
  35. unsigned int io_size_gpio;
  36. unsigned int io_size_wdt;
  37. };
  38. static struct lpc_sch_info sch_chipset_info[] = {
  39. [LPC_SCH] = {
  40. .io_size_smbus = SMBUS_IO_SIZE,
  41. .io_size_gpio = GPIO_IO_SIZE,
  42. },
  43. [LPC_ITC] = {
  44. .io_size_smbus = SMBUS_IO_SIZE,
  45. .io_size_gpio = GPIO_IO_SIZE,
  46. .io_size_wdt = WDT_IO_SIZE,
  47. },
  48. [LPC_CENTERTON] = {
  49. .io_size_smbus = SMBUS_IO_SIZE,
  50. .io_size_gpio = GPIO_IO_SIZE_CENTERTON,
  51. .io_size_wdt = WDT_IO_SIZE,
  52. },
  53. [LPC_QUARK_X1000] = {
  54. .io_size_gpio = GPIO_IO_SIZE,
  55. .io_size_wdt = WDT_IO_SIZE,
  56. },
  57. };
  58. static const struct pci_device_id lpc_sch_ids[] = {
  59. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH },
  60. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC },
  61. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON },
  62. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 },
  63. { 0, }
  64. };
  65. MODULE_DEVICE_TABLE(pci, lpc_sch_ids);
  66. #define LPC_NO_RESOURCE 1
  67. #define LPC_SKIP_RESOURCE 2
  68. static int lpc_sch_get_io(struct pci_dev *pdev, int where, const char *name,
  69. struct resource *res, int size)
  70. {
  71. unsigned int base_addr_cfg;
  72. unsigned short base_addr;
  73. if (size == 0)
  74. return LPC_NO_RESOURCE;
  75. pci_read_config_dword(pdev, where, &base_addr_cfg);
  76. base_addr = 0;
  77. if (!(base_addr_cfg & (1 << 31)))
  78. dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n",
  79. name);
  80. else
  81. base_addr = (unsigned short)base_addr_cfg;
  82. if (base_addr == 0) {
  83. dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name);
  84. return LPC_SKIP_RESOURCE;
  85. }
  86. res->start = base_addr;
  87. res->end = base_addr + size - 1;
  88. res->flags = IORESOURCE_IO;
  89. return 0;
  90. }
  91. static int lpc_sch_populate_cell(struct pci_dev *pdev, int where,
  92. const char *name, int size, int id,
  93. struct mfd_cell *cell)
  94. {
  95. struct resource *res;
  96. int ret;
  97. res = devm_kzalloc(&pdev->dev, sizeof(*res), GFP_KERNEL);
  98. if (!res)
  99. return -ENOMEM;
  100. ret = lpc_sch_get_io(pdev, where, name, res, size);
  101. if (ret)
  102. return ret;
  103. memset(cell, 0, sizeof(*cell));
  104. cell->name = name;
  105. cell->resources = res;
  106. cell->num_resources = 1;
  107. cell->ignore_resource_conflicts = true;
  108. cell->id = id;
  109. return 0;
  110. }
  111. static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id)
  112. {
  113. struct mfd_cell lpc_sch_cells[3];
  114. struct lpc_sch_info *info = &sch_chipset_info[id->driver_data];
  115. unsigned int cells = 0;
  116. int ret;
  117. ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus",
  118. info->io_size_smbus,
  119. id->device, &lpc_sch_cells[cells]);
  120. if (ret < 0)
  121. return ret;
  122. if (ret == 0)
  123. cells++;
  124. ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio",
  125. info->io_size_gpio,
  126. id->device, &lpc_sch_cells[cells]);
  127. if (ret < 0)
  128. return ret;
  129. if (ret == 0)
  130. cells++;
  131. ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt",
  132. info->io_size_wdt,
  133. id->device, &lpc_sch_cells[cells]);
  134. if (ret < 0)
  135. return ret;
  136. if (ret == 0)
  137. cells++;
  138. if (cells == 0) {
  139. dev_err(&dev->dev, "All decode registers disabled.\n");
  140. return -ENODEV;
  141. }
  142. return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL);
  143. }
  144. static void lpc_sch_remove(struct pci_dev *dev)
  145. {
  146. mfd_remove_devices(&dev->dev);
  147. }
  148. static struct pci_driver lpc_sch_driver = {
  149. .name = "lpc_sch",
  150. .id_table = lpc_sch_ids,
  151. .probe = lpc_sch_probe,
  152. .remove = lpc_sch_remove,
  153. };
  154. module_pci_driver(lpc_sch_driver);
  155. MODULE_AUTHOR("Denis Turischev <[email protected]>");
  156. MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
  157. MODULE_LICENSE("GPL");