iqs62x.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Azoteq IQS620A/621/622/624/625 Multi-Function Sensors
  4. *
  5. * Copyright (C) 2019 Jeff LaBundy <[email protected]>
  6. *
  7. * These devices rely on application-specific register settings and calibration
  8. * data developed in and exported from a suite of GUIs offered by the vendor. A
  9. * separate tool converts the GUIs' ASCII-based output into a standard firmware
  10. * file parsed by the driver.
  11. *
  12. * Link to datasheets and GUIs: https://www.azoteq.com/
  13. *
  14. * Link to conversion tool: https://github.com/jlabundy/iqs62x-h2bin.git
  15. */
  16. #include <linux/completion.h>
  17. #include <linux/delay.h>
  18. #include <linux/device.h>
  19. #include <linux/err.h>
  20. #include <linux/firmware.h>
  21. #include <linux/i2c.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/kernel.h>
  24. #include <linux/list.h>
  25. #include <linux/mfd/core.h>
  26. #include <linux/mfd/iqs62x.h>
  27. #include <linux/module.h>
  28. #include <linux/notifier.h>
  29. #include <linux/of_device.h>
  30. #include <linux/property.h>
  31. #include <linux/regmap.h>
  32. #include <linux/slab.h>
  33. #include <asm/unaligned.h>
  34. #define IQS62X_PROD_NUM 0x00
  35. #define IQS62X_SYS_FLAGS 0x10
  36. #define IQS620_HALL_FLAGS 0x16
  37. #define IQS621_HALL_FLAGS 0x19
  38. #define IQS622_HALL_FLAGS IQS621_HALL_FLAGS
  39. #define IQS624_INTERVAL_NUM 0x18
  40. #define IQS625_INTERVAL_NUM 0x12
  41. #define IQS622_PROX_SETTINGS_4 0x48
  42. #define IQS620_PROX_SETTINGS_4 0x50
  43. #define IQS620_PROX_SETTINGS_4_SAR_EN BIT(7)
  44. #define IQS621_ALS_CAL_DIV_LUX 0x82
  45. #define IQS621_ALS_CAL_DIV_IR 0x83
  46. #define IQS620_TEMP_CAL_MULT 0xC2
  47. #define IQS620_TEMP_CAL_DIV 0xC3
  48. #define IQS620_TEMP_CAL_OFFS 0xC4
  49. #define IQS62X_SYS_SETTINGS 0xD0
  50. #define IQS62X_SYS_SETTINGS_ACK_RESET BIT(6)
  51. #define IQS62X_SYS_SETTINGS_EVENT_MODE BIT(5)
  52. #define IQS62X_SYS_SETTINGS_CLK_DIV BIT(4)
  53. #define IQS62X_SYS_SETTINGS_COMM_ATI BIT(3)
  54. #define IQS62X_SYS_SETTINGS_REDO_ATI BIT(1)
  55. #define IQS62X_PWR_SETTINGS 0xD2
  56. #define IQS62X_PWR_SETTINGS_DIS_AUTO BIT(5)
  57. #define IQS62X_PWR_SETTINGS_PWR_MODE_MASK (BIT(4) | BIT(3))
  58. #define IQS62X_PWR_SETTINGS_PWR_MODE_HALT (BIT(4) | BIT(3))
  59. #define IQS62X_PWR_SETTINGS_PWR_MODE_NORM 0
  60. #define IQS62X_OTP_CMD 0xF0
  61. #define IQS62X_OTP_CMD_FG3 0x13
  62. #define IQS62X_OTP_DATA 0xF1
  63. #define IQS62X_MAX_REG 0xFF
  64. #define IQS62X_HALL_CAL_MASK GENMASK(3, 0)
  65. #define IQS62X_FW_REC_TYPE_INFO 0
  66. #define IQS62X_FW_REC_TYPE_PROD 1
  67. #define IQS62X_FW_REC_TYPE_HALL 2
  68. #define IQS62X_FW_REC_TYPE_MASK 3
  69. #define IQS62X_FW_REC_TYPE_DATA 4
  70. #define IQS62X_ATI_STARTUP_MS 350
  71. #define IQS62X_FILT_SETTLE_MS 250
  72. struct iqs62x_fw_rec {
  73. u8 type;
  74. u8 addr;
  75. u8 len;
  76. u8 data;
  77. } __packed;
  78. struct iqs62x_fw_blk {
  79. struct list_head list;
  80. u8 addr;
  81. u8 mask;
  82. u8 len;
  83. u8 data[];
  84. };
  85. struct iqs62x_info {
  86. u8 prod_num;
  87. u8 sw_num;
  88. u8 hw_num;
  89. } __packed;
  90. static int iqs62x_dev_init(struct iqs62x_core *iqs62x)
  91. {
  92. struct iqs62x_fw_blk *fw_blk;
  93. unsigned int val;
  94. int ret;
  95. list_for_each_entry(fw_blk, &iqs62x->fw_blk_head, list) {
  96. /*
  97. * In case ATI is in progress, wait for it to complete before
  98. * lowering the core clock frequency.
  99. */
  100. if (fw_blk->addr == IQS62X_SYS_SETTINGS &&
  101. *fw_blk->data & IQS62X_SYS_SETTINGS_CLK_DIV)
  102. msleep(IQS62X_ATI_STARTUP_MS);
  103. if (fw_blk->mask)
  104. ret = regmap_update_bits(iqs62x->regmap, fw_blk->addr,
  105. fw_blk->mask, *fw_blk->data);
  106. else
  107. ret = regmap_raw_write(iqs62x->regmap, fw_blk->addr,
  108. fw_blk->data, fw_blk->len);
  109. if (ret)
  110. return ret;
  111. }
  112. switch (iqs62x->dev_desc->prod_num) {
  113. case IQS620_PROD_NUM:
  114. case IQS622_PROD_NUM:
  115. ret = regmap_read(iqs62x->regmap,
  116. iqs62x->dev_desc->prox_settings, &val);
  117. if (ret)
  118. return ret;
  119. if (val & IQS620_PROX_SETTINGS_4_SAR_EN)
  120. iqs62x->ui_sel = IQS62X_UI_SAR1;
  121. fallthrough;
  122. case IQS621_PROD_NUM:
  123. ret = regmap_write(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
  124. IQS620_GLBL_EVENT_MASK_PMU |
  125. iqs62x->dev_desc->prox_mask |
  126. iqs62x->dev_desc->sar_mask |
  127. iqs62x->dev_desc->hall_mask |
  128. iqs62x->dev_desc->hyst_mask |
  129. iqs62x->dev_desc->temp_mask |
  130. iqs62x->dev_desc->als_mask |
  131. iqs62x->dev_desc->ir_mask);
  132. if (ret)
  133. return ret;
  134. break;
  135. default:
  136. ret = regmap_write(iqs62x->regmap, IQS624_HALL_UI,
  137. IQS624_HALL_UI_WHL_EVENT |
  138. IQS624_HALL_UI_INT_EVENT |
  139. IQS624_HALL_UI_AUTO_CAL);
  140. if (ret)
  141. return ret;
  142. /*
  143. * The IQS625 default interval divider is below the minimum
  144. * permissible value, and the datasheet mandates that it is
  145. * corrected during initialization (unless an updated value
  146. * has already been provided by firmware).
  147. *
  148. * To protect against an unacceptably low user-entered value
  149. * stored in the firmware, the same check is extended to the
  150. * IQS624 as well.
  151. */
  152. ret = regmap_read(iqs62x->regmap, IQS624_INTERVAL_DIV, &val);
  153. if (ret)
  154. return ret;
  155. if (val >= iqs62x->dev_desc->interval_div)
  156. break;
  157. ret = regmap_write(iqs62x->regmap, IQS624_INTERVAL_DIV,
  158. iqs62x->dev_desc->interval_div);
  159. if (ret)
  160. return ret;
  161. }
  162. /*
  163. * Place the device in streaming mode at first so as not to miss the
  164. * limited number of interrupts that would otherwise occur after ATI
  165. * completes. The device is subsequently placed in event mode by the
  166. * interrupt handler.
  167. *
  168. * In the meantime, mask interrupts during ATI to prevent the device
  169. * from soliciting I2C traffic until the noise-sensitive ATI process
  170. * is complete.
  171. */
  172. ret = regmap_update_bits(iqs62x->regmap, IQS62X_SYS_SETTINGS,
  173. IQS62X_SYS_SETTINGS_ACK_RESET |
  174. IQS62X_SYS_SETTINGS_EVENT_MODE |
  175. IQS62X_SYS_SETTINGS_COMM_ATI |
  176. IQS62X_SYS_SETTINGS_REDO_ATI,
  177. IQS62X_SYS_SETTINGS_ACK_RESET |
  178. IQS62X_SYS_SETTINGS_REDO_ATI);
  179. if (ret)
  180. return ret;
  181. /*
  182. * The following delay gives the device time to deassert its RDY output
  183. * in case a communication window was open while the REDO_ATI field was
  184. * written. This prevents an interrupt from being serviced prematurely.
  185. */
  186. usleep_range(5000, 5100);
  187. return 0;
  188. }
  189. static int iqs62x_firmware_parse(struct iqs62x_core *iqs62x,
  190. const struct firmware *fw)
  191. {
  192. struct i2c_client *client = iqs62x->client;
  193. struct iqs62x_fw_rec *fw_rec;
  194. struct iqs62x_fw_blk *fw_blk;
  195. unsigned int val;
  196. size_t pos = 0;
  197. int ret = 0;
  198. u8 mask, len, *data;
  199. u8 hall_cal_index = 0;
  200. while (pos < fw->size) {
  201. if (pos + sizeof(*fw_rec) > fw->size) {
  202. ret = -EINVAL;
  203. break;
  204. }
  205. fw_rec = (struct iqs62x_fw_rec *)(fw->data + pos);
  206. pos += sizeof(*fw_rec);
  207. if (pos + fw_rec->len - 1 > fw->size) {
  208. ret = -EINVAL;
  209. break;
  210. }
  211. pos += fw_rec->len - 1;
  212. switch (fw_rec->type) {
  213. case IQS62X_FW_REC_TYPE_INFO:
  214. continue;
  215. case IQS62X_FW_REC_TYPE_PROD:
  216. if (fw_rec->data == iqs62x->dev_desc->prod_num)
  217. continue;
  218. dev_err(&client->dev,
  219. "Incompatible product number: 0x%02X\n",
  220. fw_rec->data);
  221. ret = -EINVAL;
  222. break;
  223. case IQS62X_FW_REC_TYPE_HALL:
  224. if (!hall_cal_index) {
  225. ret = regmap_write(iqs62x->regmap,
  226. IQS62X_OTP_CMD,
  227. IQS62X_OTP_CMD_FG3);
  228. if (ret)
  229. break;
  230. ret = regmap_read(iqs62x->regmap,
  231. IQS62X_OTP_DATA, &val);
  232. if (ret)
  233. break;
  234. hall_cal_index = val & IQS62X_HALL_CAL_MASK;
  235. if (!hall_cal_index) {
  236. dev_err(&client->dev,
  237. "Uncalibrated device\n");
  238. ret = -ENODATA;
  239. break;
  240. }
  241. }
  242. if (hall_cal_index > fw_rec->len) {
  243. ret = -EINVAL;
  244. break;
  245. }
  246. mask = 0;
  247. data = &fw_rec->data + hall_cal_index - 1;
  248. len = sizeof(*data);
  249. break;
  250. case IQS62X_FW_REC_TYPE_MASK:
  251. if (fw_rec->len < (sizeof(mask) + sizeof(*data))) {
  252. ret = -EINVAL;
  253. break;
  254. }
  255. mask = fw_rec->data;
  256. data = &fw_rec->data + sizeof(mask);
  257. len = sizeof(*data);
  258. break;
  259. case IQS62X_FW_REC_TYPE_DATA:
  260. mask = 0;
  261. data = &fw_rec->data;
  262. len = fw_rec->len;
  263. break;
  264. default:
  265. dev_err(&client->dev,
  266. "Unrecognized record type: 0x%02X\n",
  267. fw_rec->type);
  268. ret = -EINVAL;
  269. }
  270. if (ret)
  271. break;
  272. fw_blk = devm_kzalloc(&client->dev,
  273. struct_size(fw_blk, data, len),
  274. GFP_KERNEL);
  275. if (!fw_blk) {
  276. ret = -ENOMEM;
  277. break;
  278. }
  279. fw_blk->addr = fw_rec->addr;
  280. fw_blk->mask = mask;
  281. fw_blk->len = len;
  282. memcpy(fw_blk->data, data, len);
  283. list_add(&fw_blk->list, &iqs62x->fw_blk_head);
  284. }
  285. release_firmware(fw);
  286. return ret;
  287. }
  288. const struct iqs62x_event_desc iqs62x_events[IQS62X_NUM_EVENTS] = {
  289. [IQS62X_EVENT_PROX_CH0_T] = {
  290. .reg = IQS62X_EVENT_PROX,
  291. .mask = BIT(4),
  292. .val = BIT(4),
  293. },
  294. [IQS62X_EVENT_PROX_CH0_P] = {
  295. .reg = IQS62X_EVENT_PROX,
  296. .mask = BIT(0),
  297. .val = BIT(0),
  298. },
  299. [IQS62X_EVENT_PROX_CH1_T] = {
  300. .reg = IQS62X_EVENT_PROX,
  301. .mask = BIT(5),
  302. .val = BIT(5),
  303. },
  304. [IQS62X_EVENT_PROX_CH1_P] = {
  305. .reg = IQS62X_EVENT_PROX,
  306. .mask = BIT(1),
  307. .val = BIT(1),
  308. },
  309. [IQS62X_EVENT_PROX_CH2_T] = {
  310. .reg = IQS62X_EVENT_PROX,
  311. .mask = BIT(6),
  312. .val = BIT(6),
  313. },
  314. [IQS62X_EVENT_PROX_CH2_P] = {
  315. .reg = IQS62X_EVENT_PROX,
  316. .mask = BIT(2),
  317. .val = BIT(2),
  318. },
  319. [IQS62X_EVENT_HYST_POS_T] = {
  320. .reg = IQS62X_EVENT_HYST,
  321. .mask = BIT(6) | BIT(7),
  322. .val = BIT(6),
  323. },
  324. [IQS62X_EVENT_HYST_POS_P] = {
  325. .reg = IQS62X_EVENT_HYST,
  326. .mask = BIT(5) | BIT(7),
  327. .val = BIT(5),
  328. },
  329. [IQS62X_EVENT_HYST_NEG_T] = {
  330. .reg = IQS62X_EVENT_HYST,
  331. .mask = BIT(6) | BIT(7),
  332. .val = BIT(6) | BIT(7),
  333. },
  334. [IQS62X_EVENT_HYST_NEG_P] = {
  335. .reg = IQS62X_EVENT_HYST,
  336. .mask = BIT(5) | BIT(7),
  337. .val = BIT(5) | BIT(7),
  338. },
  339. [IQS62X_EVENT_SAR1_ACT] = {
  340. .reg = IQS62X_EVENT_HYST,
  341. .mask = BIT(4),
  342. .val = BIT(4),
  343. },
  344. [IQS62X_EVENT_SAR1_QRD] = {
  345. .reg = IQS62X_EVENT_HYST,
  346. .mask = BIT(2),
  347. .val = BIT(2),
  348. },
  349. [IQS62X_EVENT_SAR1_MOVE] = {
  350. .reg = IQS62X_EVENT_HYST,
  351. .mask = BIT(1),
  352. .val = BIT(1),
  353. },
  354. [IQS62X_EVENT_SAR1_HALT] = {
  355. .reg = IQS62X_EVENT_HYST,
  356. .mask = BIT(0),
  357. .val = BIT(0),
  358. },
  359. [IQS62X_EVENT_WHEEL_UP] = {
  360. .reg = IQS62X_EVENT_WHEEL,
  361. .mask = BIT(7) | BIT(6),
  362. .val = BIT(7),
  363. },
  364. [IQS62X_EVENT_WHEEL_DN] = {
  365. .reg = IQS62X_EVENT_WHEEL,
  366. .mask = BIT(7) | BIT(6),
  367. .val = BIT(7) | BIT(6),
  368. },
  369. [IQS62X_EVENT_HALL_N_T] = {
  370. .reg = IQS62X_EVENT_HALL,
  371. .mask = BIT(2) | BIT(0),
  372. .val = BIT(2),
  373. },
  374. [IQS62X_EVENT_HALL_N_P] = {
  375. .reg = IQS62X_EVENT_HALL,
  376. .mask = BIT(1) | BIT(0),
  377. .val = BIT(1),
  378. },
  379. [IQS62X_EVENT_HALL_S_T] = {
  380. .reg = IQS62X_EVENT_HALL,
  381. .mask = BIT(2) | BIT(0),
  382. .val = BIT(2) | BIT(0),
  383. },
  384. [IQS62X_EVENT_HALL_S_P] = {
  385. .reg = IQS62X_EVENT_HALL,
  386. .mask = BIT(1) | BIT(0),
  387. .val = BIT(1) | BIT(0),
  388. },
  389. [IQS62X_EVENT_SYS_RESET] = {
  390. .reg = IQS62X_EVENT_SYS,
  391. .mask = BIT(7),
  392. .val = BIT(7),
  393. },
  394. [IQS62X_EVENT_SYS_ATI] = {
  395. .reg = IQS62X_EVENT_SYS,
  396. .mask = BIT(2),
  397. .val = BIT(2),
  398. },
  399. };
  400. EXPORT_SYMBOL_GPL(iqs62x_events);
  401. static irqreturn_t iqs62x_irq(int irq, void *context)
  402. {
  403. struct iqs62x_core *iqs62x = context;
  404. struct i2c_client *client = iqs62x->client;
  405. struct iqs62x_event_data event_data;
  406. struct iqs62x_event_desc event_desc;
  407. enum iqs62x_event_reg event_reg;
  408. unsigned long event_flags = 0;
  409. int ret, i, j;
  410. u8 event_map[IQS62X_EVENT_SIZE];
  411. /*
  412. * The device asserts the RDY output to signal the beginning of a
  413. * communication window, which is closed by an I2C stop condition.
  414. * As such, all interrupt status is captured in a single read and
  415. * broadcast to any interested sub-device drivers.
  416. */
  417. ret = regmap_raw_read(iqs62x->regmap, IQS62X_SYS_FLAGS, event_map,
  418. sizeof(event_map));
  419. if (ret) {
  420. dev_err(&client->dev, "Failed to read device status: %d\n",
  421. ret);
  422. return IRQ_NONE;
  423. }
  424. for (i = 0; i < sizeof(event_map); i++) {
  425. event_reg = iqs62x->dev_desc->event_regs[iqs62x->ui_sel][i];
  426. switch (event_reg) {
  427. case IQS62X_EVENT_UI_LO:
  428. event_data.ui_data = get_unaligned_le16(&event_map[i]);
  429. fallthrough;
  430. case IQS62X_EVENT_UI_HI:
  431. case IQS62X_EVENT_NONE:
  432. continue;
  433. case IQS62X_EVENT_ALS:
  434. event_data.als_flags = event_map[i];
  435. continue;
  436. case IQS62X_EVENT_IR:
  437. event_data.ir_flags = event_map[i];
  438. continue;
  439. case IQS62X_EVENT_INTER:
  440. event_data.interval = event_map[i];
  441. continue;
  442. case IQS62X_EVENT_HYST:
  443. event_map[i] <<= iqs62x->dev_desc->hyst_shift;
  444. fallthrough;
  445. case IQS62X_EVENT_WHEEL:
  446. case IQS62X_EVENT_HALL:
  447. case IQS62X_EVENT_PROX:
  448. case IQS62X_EVENT_SYS:
  449. break;
  450. }
  451. for (j = 0; j < IQS62X_NUM_EVENTS; j++) {
  452. event_desc = iqs62x_events[j];
  453. if (event_desc.reg != event_reg)
  454. continue;
  455. if ((event_map[i] & event_desc.mask) == event_desc.val)
  456. event_flags |= BIT(j);
  457. }
  458. }
  459. /*
  460. * The device resets itself in response to the I2C master stalling
  461. * communication past a fixed timeout. In this case, all registers
  462. * are restored and any interested sub-device drivers are notified.
  463. */
  464. if (event_flags & BIT(IQS62X_EVENT_SYS_RESET)) {
  465. dev_err(&client->dev, "Unexpected device reset\n");
  466. ret = iqs62x_dev_init(iqs62x);
  467. if (ret) {
  468. dev_err(&client->dev,
  469. "Failed to re-initialize device: %d\n", ret);
  470. return IRQ_NONE;
  471. }
  472. iqs62x->event_cache |= BIT(IQS62X_EVENT_SYS_RESET);
  473. reinit_completion(&iqs62x->ati_done);
  474. } else if (event_flags & BIT(IQS62X_EVENT_SYS_ATI)) {
  475. iqs62x->event_cache |= BIT(IQS62X_EVENT_SYS_ATI);
  476. reinit_completion(&iqs62x->ati_done);
  477. } else if (!completion_done(&iqs62x->ati_done)) {
  478. ret = regmap_update_bits(iqs62x->regmap, IQS62X_SYS_SETTINGS,
  479. IQS62X_SYS_SETTINGS_EVENT_MODE, 0xFF);
  480. if (ret) {
  481. dev_err(&client->dev,
  482. "Failed to enable event mode: %d\n", ret);
  483. return IRQ_NONE;
  484. }
  485. msleep(IQS62X_FILT_SETTLE_MS);
  486. complete_all(&iqs62x->ati_done);
  487. }
  488. /*
  489. * Reset and ATI events are not broadcast to the sub-device drivers
  490. * until ATI has completed. Any other events that may have occurred
  491. * during ATI are ignored.
  492. */
  493. if (completion_done(&iqs62x->ati_done)) {
  494. event_flags |= iqs62x->event_cache;
  495. ret = blocking_notifier_call_chain(&iqs62x->nh, event_flags,
  496. &event_data);
  497. if (ret & NOTIFY_STOP_MASK)
  498. return IRQ_NONE;
  499. iqs62x->event_cache = 0;
  500. }
  501. /*
  502. * Once the communication window is closed, a small delay is added to
  503. * ensure the device's RDY output has been deasserted by the time the
  504. * interrupt handler returns.
  505. */
  506. usleep_range(150, 200);
  507. return IRQ_HANDLED;
  508. }
  509. static void iqs62x_firmware_load(const struct firmware *fw, void *context)
  510. {
  511. struct iqs62x_core *iqs62x = context;
  512. struct i2c_client *client = iqs62x->client;
  513. int ret;
  514. if (fw) {
  515. ret = iqs62x_firmware_parse(iqs62x, fw);
  516. if (ret) {
  517. dev_err(&client->dev, "Failed to parse firmware: %d\n",
  518. ret);
  519. goto err_out;
  520. }
  521. }
  522. ret = iqs62x_dev_init(iqs62x);
  523. if (ret) {
  524. dev_err(&client->dev, "Failed to initialize device: %d\n", ret);
  525. goto err_out;
  526. }
  527. ret = devm_request_threaded_irq(&client->dev, client->irq,
  528. NULL, iqs62x_irq, IRQF_ONESHOT,
  529. client->name, iqs62x);
  530. if (ret) {
  531. dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
  532. goto err_out;
  533. }
  534. if (!wait_for_completion_timeout(&iqs62x->ati_done,
  535. msecs_to_jiffies(2000))) {
  536. dev_err(&client->dev, "Failed to complete ATI\n");
  537. goto err_out;
  538. }
  539. ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
  540. iqs62x->dev_desc->sub_devs,
  541. iqs62x->dev_desc->num_sub_devs,
  542. NULL, 0, NULL);
  543. if (ret)
  544. dev_err(&client->dev, "Failed to add sub-devices: %d\n", ret);
  545. err_out:
  546. complete_all(&iqs62x->fw_done);
  547. }
  548. static const struct mfd_cell iqs620at_sub_devs[] = {
  549. {
  550. .name = "iqs62x-keys",
  551. .of_compatible = "azoteq,iqs620a-keys",
  552. },
  553. {
  554. .name = "iqs620a-pwm",
  555. .of_compatible = "azoteq,iqs620a-pwm",
  556. },
  557. { .name = "iqs620at-temp", },
  558. };
  559. static const struct mfd_cell iqs620a_sub_devs[] = {
  560. {
  561. .name = "iqs62x-keys",
  562. .of_compatible = "azoteq,iqs620a-keys",
  563. },
  564. {
  565. .name = "iqs620a-pwm",
  566. .of_compatible = "azoteq,iqs620a-pwm",
  567. },
  568. };
  569. static const struct mfd_cell iqs621_sub_devs[] = {
  570. {
  571. .name = "iqs62x-keys",
  572. .of_compatible = "azoteq,iqs621-keys",
  573. },
  574. { .name = "iqs621-als", },
  575. };
  576. static const struct mfd_cell iqs622_sub_devs[] = {
  577. {
  578. .name = "iqs62x-keys",
  579. .of_compatible = "azoteq,iqs622-keys",
  580. },
  581. { .name = "iqs621-als", },
  582. };
  583. static const struct mfd_cell iqs624_sub_devs[] = {
  584. {
  585. .name = "iqs62x-keys",
  586. .of_compatible = "azoteq,iqs624-keys",
  587. },
  588. { .name = "iqs624-pos", },
  589. };
  590. static const struct mfd_cell iqs625_sub_devs[] = {
  591. {
  592. .name = "iqs62x-keys",
  593. .of_compatible = "azoteq,iqs625-keys",
  594. },
  595. { .name = "iqs624-pos", },
  596. };
  597. static const u8 iqs620at_cal_regs[] = {
  598. IQS620_TEMP_CAL_MULT,
  599. IQS620_TEMP_CAL_DIV,
  600. IQS620_TEMP_CAL_OFFS,
  601. };
  602. static const u8 iqs621_cal_regs[] = {
  603. IQS621_ALS_CAL_DIV_LUX,
  604. IQS621_ALS_CAL_DIV_IR,
  605. };
  606. static const enum iqs62x_event_reg iqs620a_event_regs[][IQS62X_EVENT_SIZE] = {
  607. [IQS62X_UI_PROX] = {
  608. IQS62X_EVENT_SYS, /* 0x10 */
  609. IQS62X_EVENT_NONE,
  610. IQS62X_EVENT_PROX, /* 0x12 */
  611. IQS62X_EVENT_HYST, /* 0x13 */
  612. IQS62X_EVENT_NONE,
  613. IQS62X_EVENT_NONE,
  614. IQS62X_EVENT_HALL, /* 0x16 */
  615. IQS62X_EVENT_NONE,
  616. IQS62X_EVENT_NONE,
  617. IQS62X_EVENT_NONE,
  618. },
  619. [IQS62X_UI_SAR1] = {
  620. IQS62X_EVENT_SYS, /* 0x10 */
  621. IQS62X_EVENT_NONE,
  622. IQS62X_EVENT_NONE,
  623. IQS62X_EVENT_HYST, /* 0x13 */
  624. IQS62X_EVENT_NONE,
  625. IQS62X_EVENT_NONE,
  626. IQS62X_EVENT_HALL, /* 0x16 */
  627. IQS62X_EVENT_NONE,
  628. IQS62X_EVENT_NONE,
  629. IQS62X_EVENT_NONE,
  630. },
  631. };
  632. static const enum iqs62x_event_reg iqs621_event_regs[][IQS62X_EVENT_SIZE] = {
  633. [IQS62X_UI_PROX] = {
  634. IQS62X_EVENT_SYS, /* 0x10 */
  635. IQS62X_EVENT_NONE,
  636. IQS62X_EVENT_PROX, /* 0x12 */
  637. IQS62X_EVENT_HYST, /* 0x13 */
  638. IQS62X_EVENT_NONE,
  639. IQS62X_EVENT_NONE,
  640. IQS62X_EVENT_ALS, /* 0x16 */
  641. IQS62X_EVENT_UI_LO, /* 0x17 */
  642. IQS62X_EVENT_UI_HI, /* 0x18 */
  643. IQS62X_EVENT_HALL, /* 0x19 */
  644. },
  645. };
  646. static const enum iqs62x_event_reg iqs622_event_regs[][IQS62X_EVENT_SIZE] = {
  647. [IQS62X_UI_PROX] = {
  648. IQS62X_EVENT_SYS, /* 0x10 */
  649. IQS62X_EVENT_NONE,
  650. IQS62X_EVENT_PROX, /* 0x12 */
  651. IQS62X_EVENT_NONE,
  652. IQS62X_EVENT_ALS, /* 0x14 */
  653. IQS62X_EVENT_NONE,
  654. IQS62X_EVENT_IR, /* 0x16 */
  655. IQS62X_EVENT_UI_LO, /* 0x17 */
  656. IQS62X_EVENT_UI_HI, /* 0x18 */
  657. IQS62X_EVENT_HALL, /* 0x19 */
  658. },
  659. [IQS62X_UI_SAR1] = {
  660. IQS62X_EVENT_SYS, /* 0x10 */
  661. IQS62X_EVENT_NONE,
  662. IQS62X_EVENT_NONE,
  663. IQS62X_EVENT_HYST, /* 0x13 */
  664. IQS62X_EVENT_ALS, /* 0x14 */
  665. IQS62X_EVENT_NONE,
  666. IQS62X_EVENT_IR, /* 0x16 */
  667. IQS62X_EVENT_UI_LO, /* 0x17 */
  668. IQS62X_EVENT_UI_HI, /* 0x18 */
  669. IQS62X_EVENT_HALL, /* 0x19 */
  670. },
  671. };
  672. static const enum iqs62x_event_reg iqs624_event_regs[][IQS62X_EVENT_SIZE] = {
  673. [IQS62X_UI_PROX] = {
  674. IQS62X_EVENT_SYS, /* 0x10 */
  675. IQS62X_EVENT_NONE,
  676. IQS62X_EVENT_PROX, /* 0x12 */
  677. IQS62X_EVENT_NONE,
  678. IQS62X_EVENT_WHEEL, /* 0x14 */
  679. IQS62X_EVENT_NONE,
  680. IQS62X_EVENT_UI_LO, /* 0x16 */
  681. IQS62X_EVENT_UI_HI, /* 0x17 */
  682. IQS62X_EVENT_INTER, /* 0x18 */
  683. IQS62X_EVENT_NONE,
  684. },
  685. };
  686. static const enum iqs62x_event_reg iqs625_event_regs[][IQS62X_EVENT_SIZE] = {
  687. [IQS62X_UI_PROX] = {
  688. IQS62X_EVENT_SYS, /* 0x10 */
  689. IQS62X_EVENT_PROX, /* 0x11 */
  690. IQS62X_EVENT_INTER, /* 0x12 */
  691. IQS62X_EVENT_NONE,
  692. IQS62X_EVENT_NONE,
  693. IQS62X_EVENT_NONE,
  694. IQS62X_EVENT_NONE,
  695. IQS62X_EVENT_NONE,
  696. IQS62X_EVENT_NONE,
  697. IQS62X_EVENT_NONE,
  698. },
  699. };
  700. static const struct iqs62x_dev_desc iqs62x_devs[] = {
  701. {
  702. .dev_name = "iqs620at",
  703. .sub_devs = iqs620at_sub_devs,
  704. .num_sub_devs = ARRAY_SIZE(iqs620at_sub_devs),
  705. .prod_num = IQS620_PROD_NUM,
  706. .sw_num = 0x08,
  707. .cal_regs = iqs620at_cal_regs,
  708. .num_cal_regs = ARRAY_SIZE(iqs620at_cal_regs),
  709. .prox_mask = BIT(0),
  710. .sar_mask = BIT(1) | BIT(7),
  711. .hall_mask = BIT(2),
  712. .hyst_mask = BIT(3),
  713. .temp_mask = BIT(4),
  714. .prox_settings = IQS620_PROX_SETTINGS_4,
  715. .hall_flags = IQS620_HALL_FLAGS,
  716. .fw_name = "iqs620a.bin",
  717. .event_regs = &iqs620a_event_regs[IQS62X_UI_PROX],
  718. },
  719. {
  720. .dev_name = "iqs620a",
  721. .sub_devs = iqs620a_sub_devs,
  722. .num_sub_devs = ARRAY_SIZE(iqs620a_sub_devs),
  723. .prod_num = IQS620_PROD_NUM,
  724. .sw_num = 0x08,
  725. .prox_mask = BIT(0),
  726. .sar_mask = BIT(1) | BIT(7),
  727. .hall_mask = BIT(2),
  728. .hyst_mask = BIT(3),
  729. .temp_mask = BIT(4),
  730. .prox_settings = IQS620_PROX_SETTINGS_4,
  731. .hall_flags = IQS620_HALL_FLAGS,
  732. .fw_name = "iqs620a.bin",
  733. .event_regs = &iqs620a_event_regs[IQS62X_UI_PROX],
  734. },
  735. {
  736. .dev_name = "iqs621",
  737. .sub_devs = iqs621_sub_devs,
  738. .num_sub_devs = ARRAY_SIZE(iqs621_sub_devs),
  739. .prod_num = IQS621_PROD_NUM,
  740. .sw_num = 0x09,
  741. .cal_regs = iqs621_cal_regs,
  742. .num_cal_regs = ARRAY_SIZE(iqs621_cal_regs),
  743. .prox_mask = BIT(0),
  744. .hall_mask = BIT(1),
  745. .als_mask = BIT(2),
  746. .hyst_mask = BIT(3),
  747. .temp_mask = BIT(4),
  748. .als_flags = IQS621_ALS_FLAGS,
  749. .hall_flags = IQS621_HALL_FLAGS,
  750. .hyst_shift = 5,
  751. .fw_name = "iqs621.bin",
  752. .event_regs = &iqs621_event_regs[IQS62X_UI_PROX],
  753. },
  754. {
  755. .dev_name = "iqs622",
  756. .sub_devs = iqs622_sub_devs,
  757. .num_sub_devs = ARRAY_SIZE(iqs622_sub_devs),
  758. .prod_num = IQS622_PROD_NUM,
  759. .sw_num = 0x06,
  760. .prox_mask = BIT(0),
  761. .sar_mask = BIT(1),
  762. .hall_mask = BIT(2),
  763. .als_mask = BIT(3),
  764. .ir_mask = BIT(4),
  765. .prox_settings = IQS622_PROX_SETTINGS_4,
  766. .als_flags = IQS622_ALS_FLAGS,
  767. .hall_flags = IQS622_HALL_FLAGS,
  768. .fw_name = "iqs622.bin",
  769. .event_regs = &iqs622_event_regs[IQS62X_UI_PROX],
  770. },
  771. {
  772. .dev_name = "iqs624",
  773. .sub_devs = iqs624_sub_devs,
  774. .num_sub_devs = ARRAY_SIZE(iqs624_sub_devs),
  775. .prod_num = IQS624_PROD_NUM,
  776. .sw_num = 0x0B,
  777. .interval = IQS624_INTERVAL_NUM,
  778. .interval_div = 3,
  779. .fw_name = "iqs624.bin",
  780. .event_regs = &iqs624_event_regs[IQS62X_UI_PROX],
  781. },
  782. {
  783. .dev_name = "iqs625",
  784. .sub_devs = iqs625_sub_devs,
  785. .num_sub_devs = ARRAY_SIZE(iqs625_sub_devs),
  786. .prod_num = IQS625_PROD_NUM,
  787. .sw_num = 0x0B,
  788. .interval = IQS625_INTERVAL_NUM,
  789. .interval_div = 10,
  790. .fw_name = "iqs625.bin",
  791. .event_regs = &iqs625_event_regs[IQS62X_UI_PROX],
  792. },
  793. };
  794. static const struct regmap_config iqs62x_regmap_config = {
  795. .reg_bits = 8,
  796. .val_bits = 8,
  797. .max_register = IQS62X_MAX_REG,
  798. };
  799. static int iqs62x_probe(struct i2c_client *client)
  800. {
  801. struct iqs62x_core *iqs62x;
  802. struct iqs62x_info info;
  803. unsigned int val;
  804. int ret, i, j;
  805. const char *fw_name = NULL;
  806. iqs62x = devm_kzalloc(&client->dev, sizeof(*iqs62x), GFP_KERNEL);
  807. if (!iqs62x)
  808. return -ENOMEM;
  809. i2c_set_clientdata(client, iqs62x);
  810. iqs62x->client = client;
  811. BLOCKING_INIT_NOTIFIER_HEAD(&iqs62x->nh);
  812. INIT_LIST_HEAD(&iqs62x->fw_blk_head);
  813. init_completion(&iqs62x->ati_done);
  814. init_completion(&iqs62x->fw_done);
  815. iqs62x->regmap = devm_regmap_init_i2c(client, &iqs62x_regmap_config);
  816. if (IS_ERR(iqs62x->regmap)) {
  817. ret = PTR_ERR(iqs62x->regmap);
  818. dev_err(&client->dev, "Failed to initialize register map: %d\n",
  819. ret);
  820. return ret;
  821. }
  822. ret = regmap_raw_read(iqs62x->regmap, IQS62X_PROD_NUM, &info,
  823. sizeof(info));
  824. if (ret)
  825. return ret;
  826. /*
  827. * The following sequence validates the device's product and software
  828. * numbers. It then determines if the device is factory-calibrated by
  829. * checking for nonzero values in the device's designated calibration
  830. * registers (if applicable). Depending on the device, the absence of
  831. * calibration data indicates a reduced feature set or invalid device.
  832. *
  833. * For devices given in both calibrated and uncalibrated versions, the
  834. * calibrated version (e.g. IQS620AT) appears first in the iqs62x_devs
  835. * array. The uncalibrated version (e.g. IQS620A) appears next and has
  836. * the same product and software numbers, but no calibration registers
  837. * are specified.
  838. */
  839. for (i = 0; i < ARRAY_SIZE(iqs62x_devs); i++) {
  840. if (info.prod_num != iqs62x_devs[i].prod_num)
  841. continue;
  842. iqs62x->dev_desc = &iqs62x_devs[i];
  843. if (info.sw_num < iqs62x->dev_desc->sw_num)
  844. continue;
  845. iqs62x->sw_num = info.sw_num;
  846. iqs62x->hw_num = info.hw_num;
  847. /*
  848. * Read each of the device's designated calibration registers,
  849. * if any, and exit from the inner loop early if any are equal
  850. * to zero (indicating the device is uncalibrated). This could
  851. * be acceptable depending on the device (e.g. IQS620A instead
  852. * of IQS620AT).
  853. */
  854. for (j = 0; j < iqs62x->dev_desc->num_cal_regs; j++) {
  855. ret = regmap_read(iqs62x->regmap,
  856. iqs62x->dev_desc->cal_regs[j], &val);
  857. if (ret)
  858. return ret;
  859. if (!val)
  860. break;
  861. }
  862. /*
  863. * If the number of nonzero values read from the device equals
  864. * the number of designated calibration registers (which could
  865. * be zero), exit from the outer loop early to signal that the
  866. * device's product and software numbers match a known device,
  867. * and the device is calibrated (if applicable).
  868. */
  869. if (j == iqs62x->dev_desc->num_cal_regs)
  870. break;
  871. }
  872. if (!iqs62x->dev_desc) {
  873. dev_err(&client->dev, "Unrecognized product number: 0x%02X\n",
  874. info.prod_num);
  875. return -EINVAL;
  876. }
  877. if (!iqs62x->sw_num) {
  878. dev_err(&client->dev, "Unrecognized software number: 0x%02X\n",
  879. info.sw_num);
  880. return -EINVAL;
  881. }
  882. if (i == ARRAY_SIZE(iqs62x_devs)) {
  883. dev_err(&client->dev, "Uncalibrated device\n");
  884. return -ENODATA;
  885. }
  886. device_property_read_string(&client->dev, "firmware-name", &fw_name);
  887. ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
  888. fw_name ? : iqs62x->dev_desc->fw_name,
  889. &client->dev, GFP_KERNEL, iqs62x,
  890. iqs62x_firmware_load);
  891. if (ret)
  892. dev_err(&client->dev, "Failed to request firmware: %d\n", ret);
  893. return ret;
  894. }
  895. static void iqs62x_remove(struct i2c_client *client)
  896. {
  897. struct iqs62x_core *iqs62x = i2c_get_clientdata(client);
  898. wait_for_completion(&iqs62x->fw_done);
  899. }
  900. static int __maybe_unused iqs62x_suspend(struct device *dev)
  901. {
  902. struct iqs62x_core *iqs62x = dev_get_drvdata(dev);
  903. int ret;
  904. wait_for_completion(&iqs62x->fw_done);
  905. /*
  906. * As per the datasheet, automatic mode switching must be disabled
  907. * before the device is placed in or taken out of halt mode.
  908. */
  909. ret = regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
  910. IQS62X_PWR_SETTINGS_DIS_AUTO, 0xFF);
  911. if (ret)
  912. return ret;
  913. return regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
  914. IQS62X_PWR_SETTINGS_PWR_MODE_MASK,
  915. IQS62X_PWR_SETTINGS_PWR_MODE_HALT);
  916. }
  917. static int __maybe_unused iqs62x_resume(struct device *dev)
  918. {
  919. struct iqs62x_core *iqs62x = dev_get_drvdata(dev);
  920. int ret;
  921. ret = regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
  922. IQS62X_PWR_SETTINGS_PWR_MODE_MASK,
  923. IQS62X_PWR_SETTINGS_PWR_MODE_NORM);
  924. if (ret)
  925. return ret;
  926. return regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
  927. IQS62X_PWR_SETTINGS_DIS_AUTO, 0);
  928. }
  929. static SIMPLE_DEV_PM_OPS(iqs62x_pm, iqs62x_suspend, iqs62x_resume);
  930. static const struct of_device_id iqs62x_of_match[] = {
  931. { .compatible = "azoteq,iqs620a" },
  932. { .compatible = "azoteq,iqs621" },
  933. { .compatible = "azoteq,iqs622" },
  934. { .compatible = "azoteq,iqs624" },
  935. { .compatible = "azoteq,iqs625" },
  936. { }
  937. };
  938. MODULE_DEVICE_TABLE(of, iqs62x_of_match);
  939. static struct i2c_driver iqs62x_i2c_driver = {
  940. .driver = {
  941. .name = "iqs62x",
  942. .of_match_table = iqs62x_of_match,
  943. .pm = &iqs62x_pm,
  944. },
  945. .probe_new = iqs62x_probe,
  946. .remove = iqs62x_remove,
  947. };
  948. module_i2c_driver(iqs62x_i2c_driver);
  949. MODULE_AUTHOR("Jeff LaBundy <[email protected]>");
  950. MODULE_DESCRIPTION("Azoteq IQS620A/621/622/624/625 Multi-Function Sensors");
  951. MODULE_LICENSE("GPL");