omap-gpmc.c 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPMC support functions
  4. *
  5. * Copyright (C) 2005-2006 Nokia Corporation
  6. *
  7. * Author: Juha Yrjola
  8. *
  9. * Copyright (C) 2009 Texas Instruments
  10. * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  11. */
  12. #include <linux/cpu_pm.h>
  13. #include <linux/irq.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/ioport.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/io.h>
  22. #include <linux/gpio/driver.h>
  23. #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  24. #include <linux/gpio/machine.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_device.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/omap-gpmc.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/sizes.h>
  35. #include <linux/platform_data/mtd-nand-omap2.h>
  36. #define DEVICE_NAME "omap-gpmc"
  37. /* GPMC register offsets */
  38. #define GPMC_REVISION 0x00
  39. #define GPMC_SYSCONFIG 0x10
  40. #define GPMC_SYSSTATUS 0x14
  41. #define GPMC_IRQSTATUS 0x18
  42. #define GPMC_IRQENABLE 0x1c
  43. #define GPMC_TIMEOUT_CONTROL 0x40
  44. #define GPMC_ERR_ADDRESS 0x44
  45. #define GPMC_ERR_TYPE 0x48
  46. #define GPMC_CONFIG 0x50
  47. #define GPMC_STATUS 0x54
  48. #define GPMC_PREFETCH_CONFIG1 0x1e0
  49. #define GPMC_PREFETCH_CONFIG2 0x1e4
  50. #define GPMC_PREFETCH_CONTROL 0x1ec
  51. #define GPMC_PREFETCH_STATUS 0x1f0
  52. #define GPMC_ECC_CONFIG 0x1f4
  53. #define GPMC_ECC_CONTROL 0x1f8
  54. #define GPMC_ECC_SIZE_CONFIG 0x1fc
  55. #define GPMC_ECC1_RESULT 0x200
  56. #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
  57. #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
  58. #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
  59. #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
  60. #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
  61. #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
  62. #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
  63. /* GPMC ECC control settings */
  64. #define GPMC_ECC_CTRL_ECCCLEAR 0x100
  65. #define GPMC_ECC_CTRL_ECCDISABLE 0x000
  66. #define GPMC_ECC_CTRL_ECCREG1 0x001
  67. #define GPMC_ECC_CTRL_ECCREG2 0x002
  68. #define GPMC_ECC_CTRL_ECCREG3 0x003
  69. #define GPMC_ECC_CTRL_ECCREG4 0x004
  70. #define GPMC_ECC_CTRL_ECCREG5 0x005
  71. #define GPMC_ECC_CTRL_ECCREG6 0x006
  72. #define GPMC_ECC_CTRL_ECCREG7 0x007
  73. #define GPMC_ECC_CTRL_ECCREG8 0x008
  74. #define GPMC_ECC_CTRL_ECCREG9 0x009
  75. #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
  76. #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
  77. #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
  78. #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
  79. #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
  80. #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
  81. #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
  82. #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
  83. #define GPMC_CS0_OFFSET 0x60
  84. #define GPMC_CS_SIZE 0x30
  85. #define GPMC_BCH_SIZE 0x10
  86. /*
  87. * The first 1MB of GPMC address space is typically mapped to
  88. * the internal ROM. Never allocate the first page, to
  89. * facilitate bug detection; even if we didn't boot from ROM.
  90. * As GPMC minimum partition size is 16MB we can only start from
  91. * there.
  92. */
  93. #define GPMC_MEM_START 0x1000000
  94. #define GPMC_MEM_END 0x3FFFFFFF
  95. #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
  96. #define GPMC_SECTION_SHIFT 28 /* 128 MB */
  97. #define CS_NUM_SHIFT 24
  98. #define ENABLE_PREFETCH (0x1 << 7)
  99. #define DMA_MPU_MODE 2
  100. #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
  101. #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
  102. #define GPMC_HAS_WR_ACCESS 0x1
  103. #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
  104. #define GPMC_HAS_MUX_AAD 0x4
  105. #define GPMC_NR_WAITPINS 4
  106. #define GPMC_CS_CONFIG1 0x00
  107. #define GPMC_CS_CONFIG2 0x04
  108. #define GPMC_CS_CONFIG3 0x08
  109. #define GPMC_CS_CONFIG4 0x0c
  110. #define GPMC_CS_CONFIG5 0x10
  111. #define GPMC_CS_CONFIG6 0x14
  112. #define GPMC_CS_CONFIG7 0x18
  113. #define GPMC_CS_NAND_COMMAND 0x1c
  114. #define GPMC_CS_NAND_ADDRESS 0x20
  115. #define GPMC_CS_NAND_DATA 0x24
  116. /* Control Commands */
  117. #define GPMC_CONFIG_RDY_BSY 0x00000001
  118. #define GPMC_CONFIG_DEV_SIZE 0x00000002
  119. #define GPMC_CONFIG_DEV_TYPE 0x00000003
  120. #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
  121. #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
  122. #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
  123. #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
  124. #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
  125. #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
  126. #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
  127. #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
  128. /** CLKACTIVATIONTIME Max Ticks */
  129. #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
  130. #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
  131. /** ATTACHEDDEVICEPAGELENGTH Max Value */
  132. #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
  133. #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
  134. #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
  135. #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
  136. /** WAITMONITORINGTIME Max Ticks */
  137. #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
  138. #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
  139. #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
  140. #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
  141. /** DEVICESIZE Max Value */
  142. #define GPMC_CONFIG1_DEVICESIZE_MAX 1
  143. #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
  144. #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
  145. #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
  146. #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
  147. #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
  148. #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
  149. #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
  150. #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
  151. #define GPMC_CONFIG7_CSVALID (1 << 6)
  152. #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
  153. #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
  154. #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
  155. #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
  156. /* All CONFIG7 bits except reserved bits */
  157. #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
  158. GPMC_CONFIG7_CSVALID_MASK | \
  159. GPMC_CONFIG7_MASKADDRESS_MASK)
  160. #define GPMC_DEVICETYPE_NOR 0
  161. #define GPMC_DEVICETYPE_NAND 2
  162. #define GPMC_CONFIG_WRITEPROTECT 0x00000010
  163. #define WR_RD_PIN_MONITORING 0x00600000
  164. /* ECC commands */
  165. #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
  166. #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
  167. #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
  168. #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
  169. enum gpmc_clk_domain {
  170. GPMC_CD_FCLK,
  171. GPMC_CD_CLK
  172. };
  173. struct gpmc_cs_data {
  174. const char *name;
  175. #define GPMC_CS_RESERVED (1 << 0)
  176. u32 flags;
  177. struct resource mem;
  178. };
  179. /* Structure to save gpmc cs context */
  180. struct gpmc_cs_config {
  181. u32 config1;
  182. u32 config2;
  183. u32 config3;
  184. u32 config4;
  185. u32 config5;
  186. u32 config6;
  187. u32 config7;
  188. int is_valid;
  189. };
  190. /*
  191. * Structure to save/restore gpmc context
  192. * to support core off on OMAP3
  193. */
  194. struct omap3_gpmc_regs {
  195. u32 sysconfig;
  196. u32 irqenable;
  197. u32 timeout_ctrl;
  198. u32 config;
  199. u32 prefetch_config1;
  200. u32 prefetch_config2;
  201. u32 prefetch_control;
  202. struct gpmc_cs_config cs_context[GPMC_CS_NUM];
  203. };
  204. struct gpmc_device {
  205. struct device *dev;
  206. int irq;
  207. struct irq_chip irq_chip;
  208. struct gpio_chip gpio_chip;
  209. struct notifier_block nb;
  210. struct omap3_gpmc_regs context;
  211. int nirqs;
  212. unsigned int is_suspended:1;
  213. struct resource *data;
  214. };
  215. static struct irq_domain *gpmc_irq_domain;
  216. static struct resource gpmc_mem_root;
  217. static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
  218. static DEFINE_SPINLOCK(gpmc_mem_lock);
  219. /* Define chip-selects as reserved by default until probe completes */
  220. static unsigned int gpmc_cs_num = GPMC_CS_NUM;
  221. static unsigned int gpmc_nr_waitpins;
  222. static unsigned int gpmc_capability;
  223. static void __iomem *gpmc_base;
  224. static struct clk *gpmc_l3_clk;
  225. static irqreturn_t gpmc_handle_irq(int irq, void *dev);
  226. static void gpmc_write_reg(int idx, u32 val)
  227. {
  228. writel_relaxed(val, gpmc_base + idx);
  229. }
  230. static u32 gpmc_read_reg(int idx)
  231. {
  232. return readl_relaxed(gpmc_base + idx);
  233. }
  234. void gpmc_cs_write_reg(int cs, int idx, u32 val)
  235. {
  236. void __iomem *reg_addr;
  237. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  238. writel_relaxed(val, reg_addr);
  239. }
  240. static u32 gpmc_cs_read_reg(int cs, int idx)
  241. {
  242. void __iomem *reg_addr;
  243. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  244. return readl_relaxed(reg_addr);
  245. }
  246. /* TODO: Add support for gpmc_fck to clock framework and use it */
  247. static unsigned long gpmc_get_fclk_period(void)
  248. {
  249. unsigned long rate = clk_get_rate(gpmc_l3_clk);
  250. rate /= 1000;
  251. rate = 1000000000 / rate; /* In picoseconds */
  252. return rate;
  253. }
  254. /**
  255. * gpmc_get_clk_period - get period of selected clock domain in ps
  256. * @cs: Chip Select Region.
  257. * @cd: Clock Domain.
  258. *
  259. * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
  260. * prior to calling this function with GPMC_CD_CLK.
  261. */
  262. static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
  263. {
  264. unsigned long tick_ps = gpmc_get_fclk_period();
  265. u32 l;
  266. int div;
  267. switch (cd) {
  268. case GPMC_CD_CLK:
  269. /* get current clk divider */
  270. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  271. div = (l & 0x03) + 1;
  272. /* get GPMC_CLK period */
  273. tick_ps *= div;
  274. break;
  275. case GPMC_CD_FCLK:
  276. default:
  277. break;
  278. }
  279. return tick_ps;
  280. }
  281. static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
  282. enum gpmc_clk_domain cd)
  283. {
  284. unsigned long tick_ps;
  285. /* Calculate in picosecs to yield more exact results */
  286. tick_ps = gpmc_get_clk_period(cs, cd);
  287. return (time_ns * 1000 + tick_ps - 1) / tick_ps;
  288. }
  289. static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
  290. {
  291. return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
  292. }
  293. static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
  294. {
  295. unsigned long tick_ps;
  296. /* Calculate in picosecs to yield more exact results */
  297. tick_ps = gpmc_get_fclk_period();
  298. return (time_ps + tick_ps - 1) / tick_ps;
  299. }
  300. static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
  301. enum gpmc_clk_domain cd)
  302. {
  303. return ticks * gpmc_get_clk_period(cs, cd) / 1000;
  304. }
  305. unsigned int gpmc_ticks_to_ns(unsigned int ticks)
  306. {
  307. return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
  308. }
  309. static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
  310. {
  311. return ticks * gpmc_get_fclk_period();
  312. }
  313. static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
  314. {
  315. unsigned long ticks = gpmc_ps_to_ticks(time_ps);
  316. return ticks * gpmc_get_fclk_period();
  317. }
  318. static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
  319. {
  320. u32 l;
  321. l = gpmc_cs_read_reg(cs, reg);
  322. if (value)
  323. l |= mask;
  324. else
  325. l &= ~mask;
  326. gpmc_cs_write_reg(cs, reg, l);
  327. }
  328. static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
  329. {
  330. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
  331. GPMC_CONFIG1_TIME_PARA_GRAN,
  332. p->time_para_granularity);
  333. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
  334. GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
  335. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
  336. GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
  337. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  338. GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
  339. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  340. GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
  341. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  342. GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
  343. p->cycle2cyclesamecsen);
  344. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  345. GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
  346. p->cycle2cyclediffcsen);
  347. }
  348. #ifdef CONFIG_OMAP_GPMC_DEBUG
  349. /**
  350. * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
  351. * @cs: Chip Select Region
  352. * @reg: GPMC_CS_CONFIGn register offset.
  353. * @st_bit: Start Bit
  354. * @end_bit: End Bit. Must be >= @st_bit.
  355. * @max: Maximum parameter value (before optional @shift).
  356. * If 0, maximum is as high as @st_bit and @end_bit allow.
  357. * @name: DTS node name, w/o "gpmc,"
  358. * @cd: Clock Domain of timing parameter.
  359. * @shift: Parameter value left shifts @shift, which is then printed instead of value.
  360. * @raw: Raw Format Option.
  361. * raw format: gpmc,name = <value>
  362. * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
  363. * Where x ns -- y ns result in the same tick value.
  364. * When @max is exceeded, "invalid" is printed inside comment.
  365. * @noval: Parameter values equal to 0 are not printed.
  366. * @return: Specified timing parameter (after optional @shift).
  367. *
  368. */
  369. static int get_gpmc_timing_reg(
  370. /* timing specifiers */
  371. int cs, int reg, int st_bit, int end_bit, int max,
  372. const char *name, const enum gpmc_clk_domain cd,
  373. /* value transform */
  374. int shift,
  375. /* format specifiers */
  376. bool raw, bool noval)
  377. {
  378. u32 l;
  379. int nr_bits;
  380. int mask;
  381. bool invalid;
  382. l = gpmc_cs_read_reg(cs, reg);
  383. nr_bits = end_bit - st_bit + 1;
  384. mask = (1 << nr_bits) - 1;
  385. l = (l >> st_bit) & mask;
  386. if (!max)
  387. max = mask;
  388. invalid = l > max;
  389. if (shift)
  390. l = (shift << l);
  391. if (noval && (l == 0))
  392. return 0;
  393. if (!raw) {
  394. /* DTS tick format for timings in ns */
  395. unsigned int time_ns;
  396. unsigned int time_ns_min = 0;
  397. if (l)
  398. time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
  399. time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
  400. pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
  401. name, time_ns, time_ns_min, time_ns, l,
  402. invalid ? "; invalid " : " ");
  403. } else {
  404. /* raw format */
  405. pr_info("gpmc,%s = <%u>;%s\n", name, l,
  406. invalid ? " /* invalid */" : "");
  407. }
  408. return l;
  409. }
  410. #define GPMC_PRINT_CONFIG(cs, config) \
  411. pr_info("cs%i %s: 0x%08x\n", cs, #config, \
  412. gpmc_cs_read_reg(cs, config))
  413. #define GPMC_GET_RAW(reg, st, end, field) \
  414. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
  415. #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
  416. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
  417. #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
  418. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
  419. #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
  420. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
  421. #define GPMC_GET_TICKS(reg, st, end, field) \
  422. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
  423. #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
  424. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
  425. #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
  426. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
  427. static void gpmc_show_regs(int cs, const char *desc)
  428. {
  429. pr_info("gpmc cs%i %s:\n", cs, desc);
  430. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
  431. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
  432. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
  433. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
  434. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
  435. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
  436. }
  437. /*
  438. * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
  439. * see commit c9fb809.
  440. */
  441. static void gpmc_cs_show_timings(int cs, const char *desc)
  442. {
  443. gpmc_show_regs(cs, desc);
  444. pr_info("gpmc cs%i access configuration:\n", cs);
  445. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
  446. GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
  447. GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
  448. GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
  449. GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
  450. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
  451. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
  452. GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
  453. GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
  454. "burst-length");
  455. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
  456. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
  457. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
  458. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
  459. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
  460. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
  461. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
  462. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
  463. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
  464. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
  465. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
  466. pr_info("gpmc cs%i timings configuration:\n", cs);
  467. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
  468. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
  469. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
  470. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
  471. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
  472. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
  473. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  474. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
  475. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
  476. "adv-aad-mux-rd-off-ns");
  477. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
  478. "adv-aad-mux-wr-off-ns");
  479. }
  480. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
  481. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
  482. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  483. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
  484. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
  485. }
  486. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
  487. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
  488. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
  489. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
  490. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
  491. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
  492. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
  493. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
  494. GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
  495. GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
  496. "wait-monitoring-ns", GPMC_CD_CLK);
  497. GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
  498. GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
  499. "clk-activation-ns", GPMC_CD_FCLK);
  500. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
  501. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
  502. }
  503. #else
  504. static inline void gpmc_cs_show_timings(int cs, const char *desc)
  505. {
  506. }
  507. #endif
  508. /**
  509. * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
  510. * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
  511. * prior to calling this function with @cd equal to GPMC_CD_CLK.
  512. *
  513. * @cs: Chip Select Region.
  514. * @reg: GPMC_CS_CONFIGn register offset.
  515. * @st_bit: Start Bit
  516. * @end_bit: End Bit. Must be >= @st_bit.
  517. * @max: Maximum parameter value.
  518. * If 0, maximum is as high as @st_bit and @end_bit allow.
  519. * @time: Timing parameter in ns.
  520. * @cd: Timing parameter clock domain.
  521. * @name: Timing parameter name.
  522. * @return: 0 on success, -1 on error.
  523. */
  524. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
  525. int time, enum gpmc_clk_domain cd, const char *name)
  526. {
  527. u32 l;
  528. int ticks, mask, nr_bits;
  529. if (time == 0)
  530. ticks = 0;
  531. else
  532. ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
  533. nr_bits = end_bit - st_bit + 1;
  534. mask = (1 << nr_bits) - 1;
  535. if (!max)
  536. max = mask;
  537. if (ticks > max) {
  538. pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
  539. __func__, cs, name, time, ticks, max);
  540. return -1;
  541. }
  542. l = gpmc_cs_read_reg(cs, reg);
  543. #ifdef CONFIG_OMAP_GPMC_DEBUG
  544. pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
  545. cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
  546. (l >> st_bit) & mask, time);
  547. #endif
  548. l &= ~(mask << st_bit);
  549. l |= ticks << st_bit;
  550. gpmc_cs_write_reg(cs, reg, l);
  551. return 0;
  552. }
  553. /**
  554. * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
  555. * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
  556. * read --> don't sample bus too early
  557. * write --> data is longer on bus
  558. *
  559. * Formula:
  560. * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
  561. * / waitmonitoring_ticks)
  562. * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
  563. * div <= 0 check.
  564. *
  565. * @wait_monitoring: WAITMONITORINGTIME in ns.
  566. * @return: -1 on failure to scale, else proper divider > 0.
  567. */
  568. static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
  569. {
  570. int div = gpmc_ns_to_ticks(wait_monitoring);
  571. div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
  572. div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
  573. if (div > 4)
  574. return -1;
  575. if (div <= 0)
  576. div = 1;
  577. return div;
  578. }
  579. /**
  580. * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
  581. * @sync_clk: GPMC_CLK period in ps.
  582. * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
  583. * Else, returns -1.
  584. */
  585. int gpmc_calc_divider(unsigned int sync_clk)
  586. {
  587. int div = gpmc_ps_to_ticks(sync_clk);
  588. if (div > 4)
  589. return -1;
  590. if (div <= 0)
  591. div = 1;
  592. return div;
  593. }
  594. /**
  595. * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
  596. * @cs: Chip Select Region.
  597. * @t: GPMC timing parameters.
  598. * @s: GPMC timing settings.
  599. * @return: 0 on success, -1 on error.
  600. */
  601. int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
  602. const struct gpmc_settings *s)
  603. {
  604. int div, ret;
  605. u32 l;
  606. div = gpmc_calc_divider(t->sync_clk);
  607. if (div < 0)
  608. return -EINVAL;
  609. /*
  610. * See if we need to change the divider for waitmonitoringtime.
  611. *
  612. * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
  613. * pure asynchronous accesses, i.e. both read and write asynchronous.
  614. * However, only do so if WAITMONITORINGTIME is actually used, i.e.
  615. * either WAITREADMONITORING or WAITWRITEMONITORING is set.
  616. *
  617. * This statement must not change div to scale async WAITMONITORINGTIME
  618. * to protect mixed synchronous and asynchronous accesses.
  619. *
  620. * We raise an error later if WAITMONITORINGTIME does not fit.
  621. */
  622. if (!s->sync_read && !s->sync_write &&
  623. (s->wait_on_read || s->wait_on_write)
  624. ) {
  625. div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
  626. if (div < 0) {
  627. pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
  628. __func__,
  629. t->wait_monitoring
  630. );
  631. return -ENXIO;
  632. }
  633. }
  634. ret = 0;
  635. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
  636. GPMC_CD_FCLK, "cs_on");
  637. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
  638. GPMC_CD_FCLK, "cs_rd_off");
  639. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
  640. GPMC_CD_FCLK, "cs_wr_off");
  641. if (ret)
  642. return -ENXIO;
  643. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
  644. GPMC_CD_FCLK, "adv_on");
  645. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
  646. GPMC_CD_FCLK, "adv_rd_off");
  647. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
  648. GPMC_CD_FCLK, "adv_wr_off");
  649. if (ret)
  650. return -ENXIO;
  651. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  652. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
  653. t->adv_aad_mux_on, GPMC_CD_FCLK,
  654. "adv_aad_mux_on");
  655. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
  656. t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
  657. "adv_aad_mux_rd_off");
  658. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
  659. t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
  660. "adv_aad_mux_wr_off");
  661. if (ret)
  662. return -ENXIO;
  663. }
  664. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
  665. GPMC_CD_FCLK, "oe_on");
  666. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
  667. GPMC_CD_FCLK, "oe_off");
  668. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  669. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
  670. t->oe_aad_mux_on, GPMC_CD_FCLK,
  671. "oe_aad_mux_on");
  672. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
  673. t->oe_aad_mux_off, GPMC_CD_FCLK,
  674. "oe_aad_mux_off");
  675. }
  676. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
  677. GPMC_CD_FCLK, "we_on");
  678. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
  679. GPMC_CD_FCLK, "we_off");
  680. if (ret)
  681. return -ENXIO;
  682. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
  683. GPMC_CD_FCLK, "rd_cycle");
  684. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
  685. GPMC_CD_FCLK, "wr_cycle");
  686. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
  687. GPMC_CD_FCLK, "access");
  688. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
  689. t->page_burst_access, GPMC_CD_FCLK,
  690. "page_burst_access");
  691. if (ret)
  692. return -ENXIO;
  693. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
  694. t->bus_turnaround, GPMC_CD_FCLK,
  695. "bus_turnaround");
  696. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
  697. t->cycle2cycle_delay, GPMC_CD_FCLK,
  698. "cycle2cycle_delay");
  699. if (ret)
  700. return -ENXIO;
  701. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
  702. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
  703. t->wr_data_mux_bus, GPMC_CD_FCLK,
  704. "wr_data_mux_bus");
  705. if (ret)
  706. return -ENXIO;
  707. }
  708. if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
  709. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
  710. t->wr_access, GPMC_CD_FCLK,
  711. "wr_access");
  712. if (ret)
  713. return -ENXIO;
  714. }
  715. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  716. l &= ~0x03;
  717. l |= (div - 1);
  718. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
  719. ret = 0;
  720. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
  721. GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
  722. t->wait_monitoring, GPMC_CD_CLK,
  723. "wait_monitoring");
  724. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
  725. GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
  726. t->clk_activation, GPMC_CD_FCLK,
  727. "clk_activation");
  728. if (ret)
  729. return -ENXIO;
  730. #ifdef CONFIG_OMAP_GPMC_DEBUG
  731. pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
  732. cs, (div * gpmc_get_fclk_period()) / 1000, div);
  733. #endif
  734. gpmc_cs_bool_timings(cs, &t->bool_timings);
  735. gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
  736. return 0;
  737. }
  738. static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
  739. {
  740. u32 l;
  741. u32 mask;
  742. /*
  743. * Ensure that base address is aligned on a
  744. * boundary equal to or greater than size.
  745. */
  746. if (base & (size - 1))
  747. return -EINVAL;
  748. base >>= GPMC_CHUNK_SHIFT;
  749. mask = (1 << GPMC_SECTION_SHIFT) - size;
  750. mask >>= GPMC_CHUNK_SHIFT;
  751. mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
  752. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  753. l &= ~GPMC_CONFIG7_MASK;
  754. l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
  755. l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
  756. l |= GPMC_CONFIG7_CSVALID;
  757. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  758. return 0;
  759. }
  760. static void gpmc_cs_enable_mem(int cs)
  761. {
  762. u32 l;
  763. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  764. l |= GPMC_CONFIG7_CSVALID;
  765. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  766. }
  767. static void gpmc_cs_disable_mem(int cs)
  768. {
  769. u32 l;
  770. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  771. l &= ~GPMC_CONFIG7_CSVALID;
  772. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  773. }
  774. static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
  775. {
  776. u32 l;
  777. u32 mask;
  778. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  779. *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
  780. mask = (l >> 8) & 0x0f;
  781. *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
  782. }
  783. static int gpmc_cs_mem_enabled(int cs)
  784. {
  785. u32 l;
  786. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  787. return l & GPMC_CONFIG7_CSVALID;
  788. }
  789. static void gpmc_cs_set_reserved(int cs, int reserved)
  790. {
  791. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  792. gpmc->flags |= GPMC_CS_RESERVED;
  793. }
  794. static bool gpmc_cs_reserved(int cs)
  795. {
  796. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  797. return gpmc->flags & GPMC_CS_RESERVED;
  798. }
  799. static unsigned long gpmc_mem_align(unsigned long size)
  800. {
  801. int order;
  802. size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
  803. order = GPMC_CHUNK_SHIFT - 1;
  804. do {
  805. size >>= 1;
  806. order++;
  807. } while (size);
  808. size = 1 << order;
  809. return size;
  810. }
  811. static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
  812. {
  813. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  814. struct resource *res = &gpmc->mem;
  815. int r;
  816. size = gpmc_mem_align(size);
  817. spin_lock(&gpmc_mem_lock);
  818. res->start = base;
  819. res->end = base + size - 1;
  820. r = request_resource(&gpmc_mem_root, res);
  821. spin_unlock(&gpmc_mem_lock);
  822. return r;
  823. }
  824. static int gpmc_cs_delete_mem(int cs)
  825. {
  826. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  827. struct resource *res = &gpmc->mem;
  828. int r;
  829. spin_lock(&gpmc_mem_lock);
  830. r = release_resource(res);
  831. res->start = 0;
  832. res->end = 0;
  833. spin_unlock(&gpmc_mem_lock);
  834. return r;
  835. }
  836. int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
  837. {
  838. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  839. struct resource *res = &gpmc->mem;
  840. int r = -1;
  841. if (cs >= gpmc_cs_num) {
  842. pr_err("%s: requested chip-select is disabled\n", __func__);
  843. return -ENODEV;
  844. }
  845. size = gpmc_mem_align(size);
  846. if (size > (1 << GPMC_SECTION_SHIFT))
  847. return -ENOMEM;
  848. spin_lock(&gpmc_mem_lock);
  849. if (gpmc_cs_reserved(cs)) {
  850. r = -EBUSY;
  851. goto out;
  852. }
  853. if (gpmc_cs_mem_enabled(cs))
  854. r = adjust_resource(res, res->start & ~(size - 1), size);
  855. if (r < 0)
  856. r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
  857. size, NULL, NULL);
  858. if (r < 0)
  859. goto out;
  860. /* Disable CS while changing base address and size mask */
  861. gpmc_cs_disable_mem(cs);
  862. r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
  863. if (r < 0) {
  864. release_resource(res);
  865. goto out;
  866. }
  867. /* Enable CS */
  868. gpmc_cs_enable_mem(cs);
  869. *base = res->start;
  870. gpmc_cs_set_reserved(cs, 1);
  871. out:
  872. spin_unlock(&gpmc_mem_lock);
  873. return r;
  874. }
  875. EXPORT_SYMBOL(gpmc_cs_request);
  876. void gpmc_cs_free(int cs)
  877. {
  878. struct gpmc_cs_data *gpmc;
  879. struct resource *res;
  880. spin_lock(&gpmc_mem_lock);
  881. if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
  882. WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
  883. spin_unlock(&gpmc_mem_lock);
  884. return;
  885. }
  886. gpmc = &gpmc_cs[cs];
  887. res = &gpmc->mem;
  888. gpmc_cs_disable_mem(cs);
  889. if (res->flags)
  890. release_resource(res);
  891. gpmc_cs_set_reserved(cs, 0);
  892. spin_unlock(&gpmc_mem_lock);
  893. }
  894. EXPORT_SYMBOL(gpmc_cs_free);
  895. /**
  896. * gpmc_configure - write request to configure gpmc
  897. * @cmd: command type
  898. * @wval: value to write
  899. * @return status of the operation
  900. */
  901. int gpmc_configure(int cmd, int wval)
  902. {
  903. u32 regval;
  904. switch (cmd) {
  905. case GPMC_CONFIG_WP:
  906. regval = gpmc_read_reg(GPMC_CONFIG);
  907. if (wval)
  908. regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
  909. else
  910. regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
  911. gpmc_write_reg(GPMC_CONFIG, regval);
  912. break;
  913. default:
  914. pr_err("%s: command not supported\n", __func__);
  915. return -EINVAL;
  916. }
  917. return 0;
  918. }
  919. EXPORT_SYMBOL(gpmc_configure);
  920. static bool gpmc_nand_writebuffer_empty(void)
  921. {
  922. if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
  923. return true;
  924. return false;
  925. }
  926. static struct gpmc_nand_ops nand_ops = {
  927. .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
  928. };
  929. /**
  930. * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
  931. * @reg: the GPMC NAND register map exclusive for NAND use.
  932. * @cs: GPMC chip select number on which the NAND sits. The
  933. * register map returned will be specific to this chip select.
  934. *
  935. * Returns NULL on error e.g. invalid cs.
  936. */
  937. struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
  938. {
  939. int i;
  940. if (cs >= gpmc_cs_num)
  941. return NULL;
  942. reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
  943. GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
  944. reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
  945. GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
  946. reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
  947. GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
  948. reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
  949. reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
  950. reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
  951. reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
  952. reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
  953. reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
  954. reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
  955. reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
  956. for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
  957. reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
  958. GPMC_BCH_SIZE * i;
  959. reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
  960. GPMC_BCH_SIZE * i;
  961. reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
  962. GPMC_BCH_SIZE * i;
  963. reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
  964. GPMC_BCH_SIZE * i;
  965. reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
  966. i * GPMC_BCH_SIZE;
  967. reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
  968. i * GPMC_BCH_SIZE;
  969. reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
  970. i * GPMC_BCH_SIZE;
  971. }
  972. return &nand_ops;
  973. }
  974. EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
  975. static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
  976. struct gpmc_settings *s,
  977. int freq, int latency)
  978. {
  979. struct gpmc_device_timings dev_t;
  980. const int t_cer = 15;
  981. const int t_avdp = 12;
  982. const int t_cez = 20; /* max of t_cez, t_oez */
  983. const int t_wpl = 40;
  984. const int t_wph = 30;
  985. int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
  986. switch (freq) {
  987. case 104:
  988. min_gpmc_clk_period = 9600; /* 104 MHz */
  989. t_ces = 3;
  990. t_avds = 4;
  991. t_avdh = 2;
  992. t_ach = 3;
  993. t_aavdh = 6;
  994. t_rdyo = 6;
  995. break;
  996. case 83:
  997. min_gpmc_clk_period = 12000; /* 83 MHz */
  998. t_ces = 5;
  999. t_avds = 4;
  1000. t_avdh = 2;
  1001. t_ach = 6;
  1002. t_aavdh = 6;
  1003. t_rdyo = 9;
  1004. break;
  1005. case 66:
  1006. min_gpmc_clk_period = 15000; /* 66 MHz */
  1007. t_ces = 6;
  1008. t_avds = 5;
  1009. t_avdh = 2;
  1010. t_ach = 6;
  1011. t_aavdh = 6;
  1012. t_rdyo = 11;
  1013. break;
  1014. default:
  1015. min_gpmc_clk_period = 18500; /* 54 MHz */
  1016. t_ces = 7;
  1017. t_avds = 7;
  1018. t_avdh = 7;
  1019. t_ach = 9;
  1020. t_aavdh = 7;
  1021. t_rdyo = 15;
  1022. break;
  1023. }
  1024. /* Set synchronous read timings */
  1025. memset(&dev_t, 0, sizeof(dev_t));
  1026. if (!s->sync_write) {
  1027. dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
  1028. dev_t.t_wpl = t_wpl * 1000;
  1029. dev_t.t_wph = t_wph * 1000;
  1030. dev_t.t_aavdh = t_aavdh * 1000;
  1031. }
  1032. dev_t.ce_xdelay = true;
  1033. dev_t.avd_xdelay = true;
  1034. dev_t.oe_xdelay = true;
  1035. dev_t.we_xdelay = true;
  1036. dev_t.clk = min_gpmc_clk_period;
  1037. dev_t.t_bacc = dev_t.clk;
  1038. dev_t.t_ces = t_ces * 1000;
  1039. dev_t.t_avds = t_avds * 1000;
  1040. dev_t.t_avdh = t_avdh * 1000;
  1041. dev_t.t_ach = t_ach * 1000;
  1042. dev_t.cyc_iaa = (latency + 1);
  1043. dev_t.t_cez_r = t_cez * 1000;
  1044. dev_t.t_cez_w = dev_t.t_cez_r;
  1045. dev_t.cyc_aavdh_oe = 1;
  1046. dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
  1047. gpmc_calc_timings(t, s, &dev_t);
  1048. }
  1049. int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
  1050. int latency,
  1051. struct gpmc_onenand_info *info)
  1052. {
  1053. int ret;
  1054. struct gpmc_timings gpmc_t;
  1055. struct gpmc_settings gpmc_s;
  1056. gpmc_read_settings_dt(dev->of_node, &gpmc_s);
  1057. info->sync_read = gpmc_s.sync_read;
  1058. info->sync_write = gpmc_s.sync_write;
  1059. info->burst_len = gpmc_s.burst_len;
  1060. if (!gpmc_s.sync_read && !gpmc_s.sync_write)
  1061. return 0;
  1062. gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
  1063. ret = gpmc_cs_program_settings(cs, &gpmc_s);
  1064. if (ret < 0)
  1065. return ret;
  1066. return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
  1067. }
  1068. EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
  1069. int gpmc_get_client_irq(unsigned int irq_config)
  1070. {
  1071. if (!gpmc_irq_domain) {
  1072. pr_warn("%s called before GPMC IRQ domain available\n",
  1073. __func__);
  1074. return 0;
  1075. }
  1076. /* we restrict this to NAND IRQs only */
  1077. if (irq_config >= GPMC_NR_NAND_IRQS)
  1078. return 0;
  1079. return irq_create_mapping(gpmc_irq_domain, irq_config);
  1080. }
  1081. static int gpmc_irq_endis(unsigned long hwirq, bool endis)
  1082. {
  1083. u32 regval;
  1084. /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
  1085. if (hwirq >= GPMC_NR_NAND_IRQS)
  1086. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1087. regval = gpmc_read_reg(GPMC_IRQENABLE);
  1088. if (endis)
  1089. regval |= BIT(hwirq);
  1090. else
  1091. regval &= ~BIT(hwirq);
  1092. gpmc_write_reg(GPMC_IRQENABLE, regval);
  1093. return 0;
  1094. }
  1095. static void gpmc_irq_disable(struct irq_data *p)
  1096. {
  1097. gpmc_irq_endis(p->hwirq, false);
  1098. }
  1099. static void gpmc_irq_enable(struct irq_data *p)
  1100. {
  1101. gpmc_irq_endis(p->hwirq, true);
  1102. }
  1103. static void gpmc_irq_mask(struct irq_data *d)
  1104. {
  1105. gpmc_irq_endis(d->hwirq, false);
  1106. }
  1107. static void gpmc_irq_unmask(struct irq_data *d)
  1108. {
  1109. gpmc_irq_endis(d->hwirq, true);
  1110. }
  1111. static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
  1112. {
  1113. u32 regval;
  1114. /* NAND IRQs polarity is not configurable */
  1115. if (hwirq < GPMC_NR_NAND_IRQS)
  1116. return;
  1117. /* WAITPIN starts at BIT 8 */
  1118. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1119. regval = gpmc_read_reg(GPMC_CONFIG);
  1120. if (rising_edge)
  1121. regval &= ~BIT(hwirq);
  1122. else
  1123. regval |= BIT(hwirq);
  1124. gpmc_write_reg(GPMC_CONFIG, regval);
  1125. }
  1126. static void gpmc_irq_ack(struct irq_data *d)
  1127. {
  1128. unsigned int hwirq = d->hwirq;
  1129. /* skip reserved bits */
  1130. if (hwirq >= GPMC_NR_NAND_IRQS)
  1131. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1132. /* Setting bit to 1 clears (or Acks) the interrupt */
  1133. gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
  1134. }
  1135. static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
  1136. {
  1137. /* can't set type for NAND IRQs */
  1138. if (d->hwirq < GPMC_NR_NAND_IRQS)
  1139. return -EINVAL;
  1140. /* We can support either rising or falling edge at a time */
  1141. if (trigger == IRQ_TYPE_EDGE_FALLING)
  1142. gpmc_irq_edge_config(d->hwirq, false);
  1143. else if (trigger == IRQ_TYPE_EDGE_RISING)
  1144. gpmc_irq_edge_config(d->hwirq, true);
  1145. else
  1146. return -EINVAL;
  1147. return 0;
  1148. }
  1149. static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
  1150. irq_hw_number_t hw)
  1151. {
  1152. struct gpmc_device *gpmc = d->host_data;
  1153. irq_set_chip_data(virq, gpmc);
  1154. if (hw < GPMC_NR_NAND_IRQS) {
  1155. irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
  1156. irq_set_chip_and_handler(virq, &gpmc->irq_chip,
  1157. handle_simple_irq);
  1158. } else {
  1159. irq_set_chip_and_handler(virq, &gpmc->irq_chip,
  1160. handle_edge_irq);
  1161. }
  1162. return 0;
  1163. }
  1164. static const struct irq_domain_ops gpmc_irq_domain_ops = {
  1165. .map = gpmc_irq_map,
  1166. .xlate = irq_domain_xlate_twocell,
  1167. };
  1168. static irqreturn_t gpmc_handle_irq(int irq, void *data)
  1169. {
  1170. int hwirq, virq;
  1171. u32 regval, regvalx;
  1172. struct gpmc_device *gpmc = data;
  1173. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  1174. regvalx = regval;
  1175. if (!regval)
  1176. return IRQ_NONE;
  1177. for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
  1178. /* skip reserved status bits */
  1179. if (hwirq == GPMC_NR_NAND_IRQS)
  1180. regvalx >>= 8 - GPMC_NR_NAND_IRQS;
  1181. if (regvalx & BIT(hwirq)) {
  1182. virq = irq_find_mapping(gpmc_irq_domain, hwirq);
  1183. if (!virq) {
  1184. dev_warn(gpmc->dev,
  1185. "spurious irq detected hwirq %d, virq %d\n",
  1186. hwirq, virq);
  1187. }
  1188. generic_handle_irq(virq);
  1189. }
  1190. }
  1191. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  1192. return IRQ_HANDLED;
  1193. }
  1194. static int gpmc_setup_irq(struct gpmc_device *gpmc)
  1195. {
  1196. u32 regval;
  1197. int rc;
  1198. /* Disable interrupts */
  1199. gpmc_write_reg(GPMC_IRQENABLE, 0);
  1200. /* clear interrupts */
  1201. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  1202. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  1203. gpmc->irq_chip.name = "gpmc";
  1204. gpmc->irq_chip.irq_enable = gpmc_irq_enable;
  1205. gpmc->irq_chip.irq_disable = gpmc_irq_disable;
  1206. gpmc->irq_chip.irq_ack = gpmc_irq_ack;
  1207. gpmc->irq_chip.irq_mask = gpmc_irq_mask;
  1208. gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
  1209. gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
  1210. gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
  1211. gpmc->nirqs,
  1212. &gpmc_irq_domain_ops,
  1213. gpmc);
  1214. if (!gpmc_irq_domain) {
  1215. dev_err(gpmc->dev, "IRQ domain add failed\n");
  1216. return -ENODEV;
  1217. }
  1218. rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
  1219. if (rc) {
  1220. dev_err(gpmc->dev, "failed to request irq %d: %d\n",
  1221. gpmc->irq, rc);
  1222. irq_domain_remove(gpmc_irq_domain);
  1223. gpmc_irq_domain = NULL;
  1224. }
  1225. return rc;
  1226. }
  1227. static int gpmc_free_irq(struct gpmc_device *gpmc)
  1228. {
  1229. int hwirq;
  1230. free_irq(gpmc->irq, gpmc);
  1231. for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
  1232. irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
  1233. irq_domain_remove(gpmc_irq_domain);
  1234. gpmc_irq_domain = NULL;
  1235. return 0;
  1236. }
  1237. static void gpmc_mem_exit(void)
  1238. {
  1239. int cs;
  1240. for (cs = 0; cs < gpmc_cs_num; cs++) {
  1241. if (!gpmc_cs_mem_enabled(cs))
  1242. continue;
  1243. gpmc_cs_delete_mem(cs);
  1244. }
  1245. }
  1246. static void gpmc_mem_init(struct gpmc_device *gpmc)
  1247. {
  1248. int cs;
  1249. if (!gpmc->data) {
  1250. /* All legacy devices have same data IO window */
  1251. gpmc_mem_root.start = GPMC_MEM_START;
  1252. gpmc_mem_root.end = GPMC_MEM_END;
  1253. } else {
  1254. gpmc_mem_root.start = gpmc->data->start;
  1255. gpmc_mem_root.end = gpmc->data->end;
  1256. }
  1257. /* Reserve all regions that has been set up by bootloader */
  1258. for (cs = 0; cs < gpmc_cs_num; cs++) {
  1259. u32 base, size;
  1260. if (!gpmc_cs_mem_enabled(cs))
  1261. continue;
  1262. gpmc_cs_get_memconf(cs, &base, &size);
  1263. if (gpmc_cs_insert_mem(cs, base, size)) {
  1264. pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
  1265. __func__, cs, base, base + size);
  1266. gpmc_cs_disable_mem(cs);
  1267. }
  1268. }
  1269. }
  1270. static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
  1271. {
  1272. u32 temp;
  1273. int div;
  1274. div = gpmc_calc_divider(sync_clk);
  1275. temp = gpmc_ps_to_ticks(time_ps);
  1276. temp = (temp + div - 1) / div;
  1277. return gpmc_ticks_to_ps(temp * div);
  1278. }
  1279. /* XXX: can the cycles be avoided ? */
  1280. static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
  1281. struct gpmc_device_timings *dev_t,
  1282. bool mux)
  1283. {
  1284. u32 temp;
  1285. /* adv_rd_off */
  1286. temp = dev_t->t_avdp_r;
  1287. /* XXX: mux check required ? */
  1288. if (mux) {
  1289. /* XXX: t_avdp not to be required for sync, only added for tusb
  1290. * this indirectly necessitates requirement of t_avdp_r and
  1291. * t_avdp_w instead of having a single t_avdp
  1292. */
  1293. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
  1294. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1295. }
  1296. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  1297. /* oe_on */
  1298. temp = dev_t->t_oeasu; /* XXX: remove this ? */
  1299. if (mux) {
  1300. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
  1301. temp = max_t(u32, temp, gpmc_t->adv_rd_off +
  1302. gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
  1303. }
  1304. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  1305. /* access */
  1306. /* XXX: any scope for improvement ?, by combining oe_on
  1307. * and clk_activation, need to check whether
  1308. * access = clk_activation + round to sync clk ?
  1309. */
  1310. temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
  1311. temp += gpmc_t->clk_activation;
  1312. if (dev_t->cyc_oe)
  1313. temp = max_t(u32, temp, gpmc_t->oe_on +
  1314. gpmc_ticks_to_ps(dev_t->cyc_oe));
  1315. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  1316. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  1317. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  1318. /* rd_cycle */
  1319. temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
  1320. temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
  1321. gpmc_t->access;
  1322. /* XXX: barter t_ce_rdyz with t_cez_r ? */
  1323. if (dev_t->t_ce_rdyz)
  1324. temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
  1325. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  1326. return 0;
  1327. }
  1328. static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
  1329. struct gpmc_device_timings *dev_t,
  1330. bool mux)
  1331. {
  1332. u32 temp;
  1333. /* adv_wr_off */
  1334. temp = dev_t->t_avdp_w;
  1335. if (mux) {
  1336. temp = max_t(u32, temp,
  1337. gpmc_t->clk_activation + dev_t->t_avdh);
  1338. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1339. }
  1340. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  1341. /* wr_data_mux_bus */
  1342. temp = max_t(u32, dev_t->t_weasu,
  1343. gpmc_t->clk_activation + dev_t->t_rdyo);
  1344. /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
  1345. * and in that case remember to handle we_on properly
  1346. */
  1347. if (mux) {
  1348. temp = max_t(u32, temp,
  1349. gpmc_t->adv_wr_off + dev_t->t_aavdh);
  1350. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  1351. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  1352. }
  1353. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  1354. /* we_on */
  1355. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  1356. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  1357. else
  1358. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  1359. /* wr_access */
  1360. /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
  1361. gpmc_t->wr_access = gpmc_t->access;
  1362. /* we_off */
  1363. temp = gpmc_t->we_on + dev_t->t_wpl;
  1364. temp = max_t(u32, temp,
  1365. gpmc_t->wr_access + gpmc_ticks_to_ps(1));
  1366. temp = max_t(u32, temp,
  1367. gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
  1368. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  1369. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  1370. dev_t->t_wph);
  1371. /* wr_cycle */
  1372. temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
  1373. temp += gpmc_t->wr_access;
  1374. /* XXX: barter t_ce_rdyz with t_cez_w ? */
  1375. if (dev_t->t_ce_rdyz)
  1376. temp = max_t(u32, temp,
  1377. gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
  1378. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  1379. return 0;
  1380. }
  1381. static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
  1382. struct gpmc_device_timings *dev_t,
  1383. bool mux)
  1384. {
  1385. u32 temp;
  1386. /* adv_rd_off */
  1387. temp = dev_t->t_avdp_r;
  1388. if (mux)
  1389. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1390. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  1391. /* oe_on */
  1392. temp = dev_t->t_oeasu;
  1393. if (mux)
  1394. temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
  1395. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  1396. /* access */
  1397. temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
  1398. gpmc_t->oe_on + dev_t->t_oe);
  1399. temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
  1400. temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
  1401. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  1402. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  1403. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  1404. /* rd_cycle */
  1405. temp = max_t(u32, dev_t->t_rd_cycle,
  1406. gpmc_t->cs_rd_off + dev_t->t_cez_r);
  1407. temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
  1408. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  1409. return 0;
  1410. }
  1411. static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
  1412. struct gpmc_device_timings *dev_t,
  1413. bool mux)
  1414. {
  1415. u32 temp;
  1416. /* adv_wr_off */
  1417. temp = dev_t->t_avdp_w;
  1418. if (mux)
  1419. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1420. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  1421. /* wr_data_mux_bus */
  1422. temp = dev_t->t_weasu;
  1423. if (mux) {
  1424. temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
  1425. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  1426. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  1427. }
  1428. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  1429. /* we_on */
  1430. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  1431. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  1432. else
  1433. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  1434. /* we_off */
  1435. temp = gpmc_t->we_on + dev_t->t_wpl;
  1436. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  1437. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  1438. dev_t->t_wph);
  1439. /* wr_cycle */
  1440. temp = max_t(u32, dev_t->t_wr_cycle,
  1441. gpmc_t->cs_wr_off + dev_t->t_cez_w);
  1442. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  1443. return 0;
  1444. }
  1445. static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
  1446. struct gpmc_device_timings *dev_t)
  1447. {
  1448. u32 temp;
  1449. gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
  1450. gpmc_get_fclk_period();
  1451. gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
  1452. dev_t->t_bacc,
  1453. gpmc_t->sync_clk);
  1454. temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
  1455. gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
  1456. if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
  1457. return 0;
  1458. if (dev_t->ce_xdelay)
  1459. gpmc_t->bool_timings.cs_extra_delay = true;
  1460. if (dev_t->avd_xdelay)
  1461. gpmc_t->bool_timings.adv_extra_delay = true;
  1462. if (dev_t->oe_xdelay)
  1463. gpmc_t->bool_timings.oe_extra_delay = true;
  1464. if (dev_t->we_xdelay)
  1465. gpmc_t->bool_timings.we_extra_delay = true;
  1466. return 0;
  1467. }
  1468. static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
  1469. struct gpmc_device_timings *dev_t,
  1470. bool sync)
  1471. {
  1472. u32 temp;
  1473. /* cs_on */
  1474. gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
  1475. /* adv_on */
  1476. temp = dev_t->t_avdasu;
  1477. if (dev_t->t_ce_avd)
  1478. temp = max_t(u32, temp,
  1479. gpmc_t->cs_on + dev_t->t_ce_avd);
  1480. gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
  1481. if (sync)
  1482. gpmc_calc_sync_common_timings(gpmc_t, dev_t);
  1483. return 0;
  1484. }
  1485. /*
  1486. * TODO: remove this function once all peripherals are confirmed to
  1487. * work with generic timing. Simultaneously gpmc_cs_set_timings()
  1488. * has to be modified to handle timings in ps instead of ns
  1489. */
  1490. static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
  1491. {
  1492. t->cs_on /= 1000;
  1493. t->cs_rd_off /= 1000;
  1494. t->cs_wr_off /= 1000;
  1495. t->adv_on /= 1000;
  1496. t->adv_rd_off /= 1000;
  1497. t->adv_wr_off /= 1000;
  1498. t->we_on /= 1000;
  1499. t->we_off /= 1000;
  1500. t->oe_on /= 1000;
  1501. t->oe_off /= 1000;
  1502. t->page_burst_access /= 1000;
  1503. t->access /= 1000;
  1504. t->rd_cycle /= 1000;
  1505. t->wr_cycle /= 1000;
  1506. t->bus_turnaround /= 1000;
  1507. t->cycle2cycle_delay /= 1000;
  1508. t->wait_monitoring /= 1000;
  1509. t->clk_activation /= 1000;
  1510. t->wr_access /= 1000;
  1511. t->wr_data_mux_bus /= 1000;
  1512. }
  1513. int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
  1514. struct gpmc_settings *gpmc_s,
  1515. struct gpmc_device_timings *dev_t)
  1516. {
  1517. bool mux = false, sync = false;
  1518. if (gpmc_s) {
  1519. mux = gpmc_s->mux_add_data ? true : false;
  1520. sync = (gpmc_s->sync_read || gpmc_s->sync_write);
  1521. }
  1522. memset(gpmc_t, 0, sizeof(*gpmc_t));
  1523. gpmc_calc_common_timings(gpmc_t, dev_t, sync);
  1524. if (gpmc_s && gpmc_s->sync_read)
  1525. gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
  1526. else
  1527. gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
  1528. if (gpmc_s && gpmc_s->sync_write)
  1529. gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
  1530. else
  1531. gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
  1532. /* TODO: remove, see function definition */
  1533. gpmc_convert_ps_to_ns(gpmc_t);
  1534. return 0;
  1535. }
  1536. /**
  1537. * gpmc_cs_program_settings - programs non-timing related settings
  1538. * @cs: GPMC chip-select to program
  1539. * @p: pointer to GPMC settings structure
  1540. *
  1541. * Programs non-timing related settings for a GPMC chip-select, such as
  1542. * bus-width, burst configuration, etc. Function should be called once
  1543. * for each chip-select that is being used and must be called before
  1544. * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
  1545. * register will be initialised to zero by this function. Returns 0 on
  1546. * success and appropriate negative error code on failure.
  1547. */
  1548. int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
  1549. {
  1550. u32 config1;
  1551. if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
  1552. pr_err("%s: invalid width %d!", __func__, p->device_width);
  1553. return -EINVAL;
  1554. }
  1555. /* Address-data multiplexing not supported for NAND devices */
  1556. if (p->device_nand && p->mux_add_data) {
  1557. pr_err("%s: invalid configuration!\n", __func__);
  1558. return -EINVAL;
  1559. }
  1560. if ((p->mux_add_data > GPMC_MUX_AD) ||
  1561. ((p->mux_add_data == GPMC_MUX_AAD) &&
  1562. !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
  1563. pr_err("%s: invalid multiplex configuration!\n", __func__);
  1564. return -EINVAL;
  1565. }
  1566. /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
  1567. if (p->burst_read || p->burst_write) {
  1568. switch (p->burst_len) {
  1569. case GPMC_BURST_4:
  1570. case GPMC_BURST_8:
  1571. case GPMC_BURST_16:
  1572. break;
  1573. default:
  1574. pr_err("%s: invalid page/burst-length (%d)\n",
  1575. __func__, p->burst_len);
  1576. return -EINVAL;
  1577. }
  1578. }
  1579. if (p->wait_pin > gpmc_nr_waitpins) {
  1580. pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
  1581. return -EINVAL;
  1582. }
  1583. config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
  1584. if (p->sync_read)
  1585. config1 |= GPMC_CONFIG1_READTYPE_SYNC;
  1586. if (p->sync_write)
  1587. config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
  1588. if (p->wait_on_read)
  1589. config1 |= GPMC_CONFIG1_WAIT_READ_MON;
  1590. if (p->wait_on_write)
  1591. config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
  1592. if (p->wait_on_read || p->wait_on_write)
  1593. config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
  1594. if (p->device_nand)
  1595. config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
  1596. if (p->mux_add_data)
  1597. config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
  1598. if (p->burst_read)
  1599. config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
  1600. if (p->burst_write)
  1601. config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
  1602. if (p->burst_read || p->burst_write) {
  1603. config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
  1604. config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
  1605. }
  1606. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
  1607. return 0;
  1608. }
  1609. #ifdef CONFIG_OF
  1610. static void gpmc_cs_set_name(int cs, const char *name)
  1611. {
  1612. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  1613. gpmc->name = name;
  1614. }
  1615. static const char *gpmc_cs_get_name(int cs)
  1616. {
  1617. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  1618. return gpmc->name;
  1619. }
  1620. /**
  1621. * gpmc_cs_remap - remaps a chip-select physical base address
  1622. * @cs: chip-select to remap
  1623. * @base: physical base address to re-map chip-select to
  1624. *
  1625. * Re-maps a chip-select to a new physical base address specified by
  1626. * "base". Returns 0 on success and appropriate negative error code
  1627. * on failure.
  1628. */
  1629. static int gpmc_cs_remap(int cs, u32 base)
  1630. {
  1631. int ret;
  1632. u32 old_base, size;
  1633. if (cs >= gpmc_cs_num) {
  1634. pr_err("%s: requested chip-select is disabled\n", __func__);
  1635. return -ENODEV;
  1636. }
  1637. /*
  1638. * Make sure we ignore any device offsets from the GPMC partition
  1639. * allocated for the chip select and that the new base confirms
  1640. * to the GPMC 16MB minimum granularity.
  1641. */
  1642. base &= ~(SZ_16M - 1);
  1643. gpmc_cs_get_memconf(cs, &old_base, &size);
  1644. if (base == old_base)
  1645. return 0;
  1646. ret = gpmc_cs_delete_mem(cs);
  1647. if (ret < 0)
  1648. return ret;
  1649. ret = gpmc_cs_insert_mem(cs, base, size);
  1650. if (ret < 0)
  1651. return ret;
  1652. ret = gpmc_cs_set_memconf(cs, base, size);
  1653. return ret;
  1654. }
  1655. /**
  1656. * gpmc_read_settings_dt - read gpmc settings from device-tree
  1657. * @np: pointer to device-tree node for a gpmc child device
  1658. * @p: pointer to gpmc settings structure
  1659. *
  1660. * Reads the GPMC settings for a GPMC child device from device-tree and
  1661. * stores them in the GPMC settings structure passed. The GPMC settings
  1662. * structure is initialised to zero by this function and so any
  1663. * previously stored settings will be cleared.
  1664. */
  1665. void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
  1666. {
  1667. memset(p, 0, sizeof(struct gpmc_settings));
  1668. p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
  1669. p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
  1670. of_property_read_u32(np, "gpmc,device-width", &p->device_width);
  1671. of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
  1672. if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
  1673. p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
  1674. p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
  1675. p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
  1676. if (!p->burst_read && !p->burst_write)
  1677. pr_warn("%s: page/burst-length set but not used!\n",
  1678. __func__);
  1679. }
  1680. if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
  1681. p->wait_on_read = of_property_read_bool(np,
  1682. "gpmc,wait-on-read");
  1683. p->wait_on_write = of_property_read_bool(np,
  1684. "gpmc,wait-on-write");
  1685. if (!p->wait_on_read && !p->wait_on_write)
  1686. pr_debug("%s: rd/wr wait monitoring not enabled!\n",
  1687. __func__);
  1688. }
  1689. }
  1690. static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
  1691. struct gpmc_timings *gpmc_t)
  1692. {
  1693. struct gpmc_bool_timings *p;
  1694. if (!np || !gpmc_t)
  1695. return;
  1696. memset(gpmc_t, 0, sizeof(*gpmc_t));
  1697. /* minimum clock period for syncronous mode */
  1698. of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
  1699. /* chip select timtings */
  1700. of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
  1701. of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
  1702. of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
  1703. /* ADV signal timings */
  1704. of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
  1705. of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
  1706. of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
  1707. of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
  1708. &gpmc_t->adv_aad_mux_on);
  1709. of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
  1710. &gpmc_t->adv_aad_mux_rd_off);
  1711. of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
  1712. &gpmc_t->adv_aad_mux_wr_off);
  1713. /* WE signal timings */
  1714. of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
  1715. of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
  1716. /* OE signal timings */
  1717. of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
  1718. of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
  1719. of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
  1720. &gpmc_t->oe_aad_mux_on);
  1721. of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
  1722. &gpmc_t->oe_aad_mux_off);
  1723. /* access and cycle timings */
  1724. of_property_read_u32(np, "gpmc,page-burst-access-ns",
  1725. &gpmc_t->page_burst_access);
  1726. of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
  1727. of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
  1728. of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
  1729. of_property_read_u32(np, "gpmc,bus-turnaround-ns",
  1730. &gpmc_t->bus_turnaround);
  1731. of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
  1732. &gpmc_t->cycle2cycle_delay);
  1733. of_property_read_u32(np, "gpmc,wait-monitoring-ns",
  1734. &gpmc_t->wait_monitoring);
  1735. of_property_read_u32(np, "gpmc,clk-activation-ns",
  1736. &gpmc_t->clk_activation);
  1737. /* only applicable to OMAP3+ */
  1738. of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
  1739. of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
  1740. &gpmc_t->wr_data_mux_bus);
  1741. /* bool timing parameters */
  1742. p = &gpmc_t->bool_timings;
  1743. p->cycle2cyclediffcsen =
  1744. of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
  1745. p->cycle2cyclesamecsen =
  1746. of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
  1747. p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
  1748. p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
  1749. p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
  1750. p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
  1751. p->time_para_granularity =
  1752. of_property_read_bool(np, "gpmc,time-para-granularity");
  1753. }
  1754. /**
  1755. * gpmc_probe_generic_child - configures the gpmc for a child device
  1756. * @pdev: pointer to gpmc platform device
  1757. * @child: pointer to device-tree node for child device
  1758. *
  1759. * Allocates and configures a GPMC chip-select for a child device.
  1760. * Returns 0 on success and appropriate negative error code on failure.
  1761. */
  1762. static int gpmc_probe_generic_child(struct platform_device *pdev,
  1763. struct device_node *child)
  1764. {
  1765. struct gpmc_settings gpmc_s;
  1766. struct gpmc_timings gpmc_t;
  1767. struct resource res;
  1768. unsigned long base;
  1769. const char *name;
  1770. int ret, cs;
  1771. u32 val;
  1772. struct gpio_desc *waitpin_desc = NULL;
  1773. struct gpmc_device *gpmc = platform_get_drvdata(pdev);
  1774. if (of_property_read_u32(child, "reg", &cs) < 0) {
  1775. dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
  1776. child);
  1777. return -ENODEV;
  1778. }
  1779. if (of_address_to_resource(child, 0, &res) < 0) {
  1780. dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
  1781. child);
  1782. return -ENODEV;
  1783. }
  1784. /*
  1785. * Check if we have multiple instances of the same device
  1786. * on a single chip select. If so, use the already initialized
  1787. * timings.
  1788. */
  1789. name = gpmc_cs_get_name(cs);
  1790. if (name && of_node_name_eq(child, name))
  1791. goto no_timings;
  1792. ret = gpmc_cs_request(cs, resource_size(&res), &base);
  1793. if (ret < 0) {
  1794. dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
  1795. return ret;
  1796. }
  1797. gpmc_cs_set_name(cs, child->full_name);
  1798. gpmc_read_settings_dt(child, &gpmc_s);
  1799. gpmc_read_timings_dt(child, &gpmc_t);
  1800. /*
  1801. * For some GPMC devices we still need to rely on the bootloader
  1802. * timings because the devices can be connected via FPGA.
  1803. * REVISIT: Add timing support from slls644g.pdf.
  1804. */
  1805. if (!gpmc_t.cs_rd_off) {
  1806. WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
  1807. cs);
  1808. gpmc_cs_show_timings(cs,
  1809. "please add GPMC bootloader timings to .dts");
  1810. goto no_timings;
  1811. }
  1812. /* CS must be disabled while making changes to gpmc configuration */
  1813. gpmc_cs_disable_mem(cs);
  1814. /*
  1815. * FIXME: gpmc_cs_request() will map the CS to an arbitrary
  1816. * location in the gpmc address space. When booting with
  1817. * device-tree we want the NOR flash to be mapped to the
  1818. * location specified in the device-tree blob. So remap the
  1819. * CS to this location. Once DT migration is complete should
  1820. * just make gpmc_cs_request() map a specific address.
  1821. */
  1822. ret = gpmc_cs_remap(cs, res.start);
  1823. if (ret < 0) {
  1824. dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
  1825. cs, &res.start);
  1826. if (res.start < GPMC_MEM_START) {
  1827. dev_info(&pdev->dev,
  1828. "GPMC CS %d start cannot be lesser than 0x%x\n",
  1829. cs, GPMC_MEM_START);
  1830. } else if (res.end > GPMC_MEM_END) {
  1831. dev_info(&pdev->dev,
  1832. "GPMC CS %d end cannot be greater than 0x%x\n",
  1833. cs, GPMC_MEM_END);
  1834. }
  1835. goto err;
  1836. }
  1837. if (of_node_name_eq(child, "nand")) {
  1838. /* Warn about older DT blobs with no compatible property */
  1839. if (!of_property_read_bool(child, "compatible")) {
  1840. dev_warn(&pdev->dev,
  1841. "Incompatible NAND node: missing compatible");
  1842. ret = -EINVAL;
  1843. goto err;
  1844. }
  1845. }
  1846. if (of_node_name_eq(child, "onenand")) {
  1847. /* Warn about older DT blobs with no compatible property */
  1848. if (!of_property_read_bool(child, "compatible")) {
  1849. dev_warn(&pdev->dev,
  1850. "Incompatible OneNAND node: missing compatible");
  1851. ret = -EINVAL;
  1852. goto err;
  1853. }
  1854. }
  1855. if (of_match_node(omap_nand_ids, child)) {
  1856. /* NAND specific setup */
  1857. val = 8;
  1858. of_property_read_u32(child, "nand-bus-width", &val);
  1859. switch (val) {
  1860. case 8:
  1861. gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
  1862. break;
  1863. case 16:
  1864. gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
  1865. break;
  1866. default:
  1867. dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
  1868. child);
  1869. ret = -EINVAL;
  1870. goto err;
  1871. }
  1872. /* disable write protect */
  1873. gpmc_configure(GPMC_CONFIG_WP, 0);
  1874. gpmc_s.device_nand = true;
  1875. } else {
  1876. ret = of_property_read_u32(child, "bank-width",
  1877. &gpmc_s.device_width);
  1878. if (ret < 0 && !gpmc_s.device_width) {
  1879. dev_err(&pdev->dev,
  1880. "%pOF has no 'gpmc,device-width' property\n",
  1881. child);
  1882. goto err;
  1883. }
  1884. }
  1885. /* Reserve wait pin if it is required and valid */
  1886. if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
  1887. unsigned int wait_pin = gpmc_s.wait_pin;
  1888. waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
  1889. wait_pin, "WAITPIN",
  1890. GPIO_ACTIVE_HIGH,
  1891. GPIOD_IN);
  1892. if (IS_ERR(waitpin_desc)) {
  1893. dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
  1894. ret = PTR_ERR(waitpin_desc);
  1895. goto err;
  1896. }
  1897. }
  1898. gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
  1899. ret = gpmc_cs_program_settings(cs, &gpmc_s);
  1900. if (ret < 0)
  1901. goto err_cs;
  1902. ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
  1903. if (ret) {
  1904. dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
  1905. child);
  1906. goto err_cs;
  1907. }
  1908. /* Clear limited address i.e. enable A26-A11 */
  1909. val = gpmc_read_reg(GPMC_CONFIG);
  1910. val &= ~GPMC_CONFIG_LIMITEDADDRESS;
  1911. gpmc_write_reg(GPMC_CONFIG, val);
  1912. /* Enable CS region */
  1913. gpmc_cs_enable_mem(cs);
  1914. no_timings:
  1915. /* create platform device, NULL on error or when disabled */
  1916. if (!of_platform_device_create(child, NULL, &pdev->dev))
  1917. goto err_child_fail;
  1918. /* create children and other common bus children */
  1919. if (of_platform_default_populate(child, NULL, &pdev->dev))
  1920. goto err_child_fail;
  1921. return 0;
  1922. err_child_fail:
  1923. dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
  1924. ret = -ENODEV;
  1925. err_cs:
  1926. gpiochip_free_own_desc(waitpin_desc);
  1927. err:
  1928. gpmc_cs_free(cs);
  1929. return ret;
  1930. }
  1931. static const struct of_device_id gpmc_dt_ids[];
  1932. static int gpmc_probe_dt(struct platform_device *pdev)
  1933. {
  1934. int ret;
  1935. const struct of_device_id *of_id =
  1936. of_match_device(gpmc_dt_ids, &pdev->dev);
  1937. if (!of_id)
  1938. return 0;
  1939. ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
  1940. &gpmc_cs_num);
  1941. if (ret < 0) {
  1942. pr_err("%s: number of chip-selects not defined\n", __func__);
  1943. return ret;
  1944. } else if (gpmc_cs_num < 1) {
  1945. pr_err("%s: all chip-selects are disabled\n", __func__);
  1946. return -EINVAL;
  1947. } else if (gpmc_cs_num > GPMC_CS_NUM) {
  1948. pr_err("%s: number of supported chip-selects cannot be > %d\n",
  1949. __func__, GPMC_CS_NUM);
  1950. return -EINVAL;
  1951. }
  1952. ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
  1953. &gpmc_nr_waitpins);
  1954. if (ret < 0) {
  1955. pr_err("%s: number of wait pins not found!\n", __func__);
  1956. return ret;
  1957. }
  1958. return 0;
  1959. }
  1960. static void gpmc_probe_dt_children(struct platform_device *pdev)
  1961. {
  1962. int ret;
  1963. struct device_node *child;
  1964. for_each_available_child_of_node(pdev->dev.of_node, child) {
  1965. ret = gpmc_probe_generic_child(pdev, child);
  1966. if (ret) {
  1967. dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
  1968. child, ret);
  1969. }
  1970. }
  1971. }
  1972. #else
  1973. void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
  1974. {
  1975. memset(p, 0, sizeof(*p));
  1976. }
  1977. static int gpmc_probe_dt(struct platform_device *pdev)
  1978. {
  1979. return 0;
  1980. }
  1981. static void gpmc_probe_dt_children(struct platform_device *pdev)
  1982. {
  1983. }
  1984. #endif /* CONFIG_OF */
  1985. static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  1986. {
  1987. return 1; /* we're input only */
  1988. }
  1989. static int gpmc_gpio_direction_input(struct gpio_chip *chip,
  1990. unsigned int offset)
  1991. {
  1992. return 0; /* we're input only */
  1993. }
  1994. static int gpmc_gpio_direction_output(struct gpio_chip *chip,
  1995. unsigned int offset, int value)
  1996. {
  1997. return -EINVAL; /* we're input only */
  1998. }
  1999. static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
  2000. int value)
  2001. {
  2002. }
  2003. static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
  2004. {
  2005. u32 reg;
  2006. offset += 8;
  2007. reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
  2008. return !!reg;
  2009. }
  2010. static int gpmc_gpio_init(struct gpmc_device *gpmc)
  2011. {
  2012. int ret;
  2013. gpmc->gpio_chip.parent = gpmc->dev;
  2014. gpmc->gpio_chip.owner = THIS_MODULE;
  2015. gpmc->gpio_chip.label = DEVICE_NAME;
  2016. gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
  2017. gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
  2018. gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
  2019. gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
  2020. gpmc->gpio_chip.set = gpmc_gpio_set;
  2021. gpmc->gpio_chip.get = gpmc_gpio_get;
  2022. gpmc->gpio_chip.base = -1;
  2023. ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
  2024. if (ret < 0) {
  2025. dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
  2026. return ret;
  2027. }
  2028. return 0;
  2029. }
  2030. static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
  2031. {
  2032. struct omap3_gpmc_regs *gpmc_context;
  2033. int i;
  2034. if (!gpmc || !gpmc_base)
  2035. return;
  2036. gpmc_context = &gpmc->context;
  2037. gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
  2038. gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
  2039. gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
  2040. gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
  2041. gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
  2042. gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
  2043. gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
  2044. for (i = 0; i < gpmc_cs_num; i++) {
  2045. gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
  2046. if (gpmc_context->cs_context[i].is_valid) {
  2047. gpmc_context->cs_context[i].config1 =
  2048. gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
  2049. gpmc_context->cs_context[i].config2 =
  2050. gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
  2051. gpmc_context->cs_context[i].config3 =
  2052. gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
  2053. gpmc_context->cs_context[i].config4 =
  2054. gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
  2055. gpmc_context->cs_context[i].config5 =
  2056. gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
  2057. gpmc_context->cs_context[i].config6 =
  2058. gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
  2059. gpmc_context->cs_context[i].config7 =
  2060. gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
  2061. }
  2062. }
  2063. }
  2064. static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
  2065. {
  2066. struct omap3_gpmc_regs *gpmc_context;
  2067. int i;
  2068. if (!gpmc || !gpmc_base)
  2069. return;
  2070. gpmc_context = &gpmc->context;
  2071. gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
  2072. gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
  2073. gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
  2074. gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
  2075. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
  2076. gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
  2077. gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
  2078. for (i = 0; i < gpmc_cs_num; i++) {
  2079. if (gpmc_context->cs_context[i].is_valid) {
  2080. gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
  2081. gpmc_context->cs_context[i].config1);
  2082. gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
  2083. gpmc_context->cs_context[i].config2);
  2084. gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
  2085. gpmc_context->cs_context[i].config3);
  2086. gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
  2087. gpmc_context->cs_context[i].config4);
  2088. gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
  2089. gpmc_context->cs_context[i].config5);
  2090. gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
  2091. gpmc_context->cs_context[i].config6);
  2092. gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
  2093. gpmc_context->cs_context[i].config7);
  2094. } else {
  2095. gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
  2096. }
  2097. }
  2098. }
  2099. static int omap_gpmc_context_notifier(struct notifier_block *nb,
  2100. unsigned long cmd, void *v)
  2101. {
  2102. struct gpmc_device *gpmc;
  2103. gpmc = container_of(nb, struct gpmc_device, nb);
  2104. if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
  2105. return NOTIFY_OK;
  2106. switch (cmd) {
  2107. case CPU_CLUSTER_PM_ENTER:
  2108. omap3_gpmc_save_context(gpmc);
  2109. break;
  2110. case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
  2111. break;
  2112. case CPU_CLUSTER_PM_EXIT:
  2113. omap3_gpmc_restore_context(gpmc);
  2114. break;
  2115. }
  2116. return NOTIFY_OK;
  2117. }
  2118. static int gpmc_probe(struct platform_device *pdev)
  2119. {
  2120. int rc;
  2121. u32 l;
  2122. struct resource *res;
  2123. struct gpmc_device *gpmc;
  2124. gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
  2125. if (!gpmc)
  2126. return -ENOMEM;
  2127. gpmc->dev = &pdev->dev;
  2128. platform_set_drvdata(pdev, gpmc);
  2129. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
  2130. if (!res) {
  2131. /* legacy DT */
  2132. gpmc_base = devm_platform_ioremap_resource(pdev, 0);
  2133. if (IS_ERR(gpmc_base))
  2134. return PTR_ERR(gpmc_base);
  2135. } else {
  2136. gpmc_base = devm_ioremap_resource(&pdev->dev, res);
  2137. if (IS_ERR(gpmc_base))
  2138. return PTR_ERR(gpmc_base);
  2139. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
  2140. if (!res) {
  2141. dev_err(&pdev->dev, "couldn't get data reg resource\n");
  2142. return -ENOENT;
  2143. }
  2144. gpmc->data = res;
  2145. }
  2146. gpmc->irq = platform_get_irq(pdev, 0);
  2147. if (gpmc->irq < 0)
  2148. return gpmc->irq;
  2149. gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
  2150. if (IS_ERR(gpmc_l3_clk)) {
  2151. dev_err(&pdev->dev, "Failed to get GPMC fck\n");
  2152. return PTR_ERR(gpmc_l3_clk);
  2153. }
  2154. if (!clk_get_rate(gpmc_l3_clk)) {
  2155. dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
  2156. return -EINVAL;
  2157. }
  2158. if (pdev->dev.of_node) {
  2159. rc = gpmc_probe_dt(pdev);
  2160. if (rc)
  2161. return rc;
  2162. } else {
  2163. gpmc_cs_num = GPMC_CS_NUM;
  2164. gpmc_nr_waitpins = GPMC_NR_WAITPINS;
  2165. }
  2166. pm_runtime_enable(&pdev->dev);
  2167. pm_runtime_get_sync(&pdev->dev);
  2168. l = gpmc_read_reg(GPMC_REVISION);
  2169. /*
  2170. * FIXME: Once device-tree migration is complete the below flags
  2171. * should be populated based upon the device-tree compatible
  2172. * string. For now just use the IP revision. OMAP3+ devices have
  2173. * the wr_access and wr_data_mux_bus register fields. OMAP4+
  2174. * devices support the addr-addr-data multiplex protocol.
  2175. *
  2176. * GPMC IP revisions:
  2177. * - OMAP24xx = 2.0
  2178. * - OMAP3xxx = 5.0
  2179. * - OMAP44xx/54xx/AM335x = 6.0
  2180. */
  2181. if (GPMC_REVISION_MAJOR(l) > 0x4)
  2182. gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
  2183. if (GPMC_REVISION_MAJOR(l) > 0x5)
  2184. gpmc_capability |= GPMC_HAS_MUX_AAD;
  2185. dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
  2186. GPMC_REVISION_MINOR(l));
  2187. gpmc_mem_init(gpmc);
  2188. rc = gpmc_gpio_init(gpmc);
  2189. if (rc)
  2190. goto gpio_init_failed;
  2191. gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
  2192. rc = gpmc_setup_irq(gpmc);
  2193. if (rc) {
  2194. dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
  2195. goto gpio_init_failed;
  2196. }
  2197. gpmc_probe_dt_children(pdev);
  2198. gpmc->nb.notifier_call = omap_gpmc_context_notifier;
  2199. cpu_pm_register_notifier(&gpmc->nb);
  2200. return 0;
  2201. gpio_init_failed:
  2202. gpmc_mem_exit();
  2203. pm_runtime_put_sync(&pdev->dev);
  2204. pm_runtime_disable(&pdev->dev);
  2205. return rc;
  2206. }
  2207. static int gpmc_remove(struct platform_device *pdev)
  2208. {
  2209. struct gpmc_device *gpmc = platform_get_drvdata(pdev);
  2210. cpu_pm_unregister_notifier(&gpmc->nb);
  2211. gpmc_free_irq(gpmc);
  2212. gpmc_mem_exit();
  2213. pm_runtime_put_sync(&pdev->dev);
  2214. pm_runtime_disable(&pdev->dev);
  2215. return 0;
  2216. }
  2217. #ifdef CONFIG_PM_SLEEP
  2218. static int gpmc_suspend(struct device *dev)
  2219. {
  2220. struct gpmc_device *gpmc = dev_get_drvdata(dev);
  2221. omap3_gpmc_save_context(gpmc);
  2222. pm_runtime_put_sync(dev);
  2223. gpmc->is_suspended = 1;
  2224. return 0;
  2225. }
  2226. static int gpmc_resume(struct device *dev)
  2227. {
  2228. struct gpmc_device *gpmc = dev_get_drvdata(dev);
  2229. pm_runtime_get_sync(dev);
  2230. omap3_gpmc_restore_context(gpmc);
  2231. gpmc->is_suspended = 0;
  2232. return 0;
  2233. }
  2234. #endif
  2235. static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
  2236. #ifdef CONFIG_OF
  2237. static const struct of_device_id gpmc_dt_ids[] = {
  2238. { .compatible = "ti,omap2420-gpmc" },
  2239. { .compatible = "ti,omap2430-gpmc" },
  2240. { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
  2241. { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
  2242. { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
  2243. { .compatible = "ti,am64-gpmc" },
  2244. { }
  2245. };
  2246. MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
  2247. #endif
  2248. static struct platform_driver gpmc_driver = {
  2249. .probe = gpmc_probe,
  2250. .remove = gpmc_remove,
  2251. .driver = {
  2252. .name = DEVICE_NAME,
  2253. .of_match_table = of_match_ptr(gpmc_dt_ids),
  2254. .pm = &gpmc_pm_ops,
  2255. },
  2256. };
  2257. module_platform_driver(gpmc_driver);
  2258. MODULE_DESCRIPTION("Texas Instruments GPMC driver");
  2259. MODULE_LICENSE("GPL");