mailbox-mpfs.c 7.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver
  4. *
  5. * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
  6. *
  7. * Author: Conor Dooley <[email protected]>
  8. *
  9. */
  10. #include <linux/io.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mailbox_controller.h>
  18. #include <soc/microchip/mpfs.h>
  19. #define SERVICES_CR_OFFSET 0x50u
  20. #define SERVICES_SR_OFFSET 0x54u
  21. #define MAILBOX_REG_OFFSET 0x800u
  22. #define MSS_SYS_MAILBOX_DATA_OFFSET 0u
  23. #define SCB_MASK_WIDTH 16u
  24. /* SCBCTRL service control register */
  25. #define SCB_CTRL_REQ (0)
  26. #define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ)
  27. #define SCB_CTRL_BUSY (1)
  28. #define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY)
  29. #define SCB_CTRL_ABORT (2)
  30. #define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT)
  31. #define SCB_CTRL_NOTIFY (3)
  32. #define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
  33. #define SCB_CTRL_POS (16)
  34. #define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
  35. /* SCBCTRL service status register */
  36. #define SCB_STATUS_REQ (0)
  37. #define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ)
  38. #define SCB_STATUS_BUSY (1)
  39. #define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY)
  40. #define SCB_STATUS_ABORT (2)
  41. #define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT)
  42. #define SCB_STATUS_NOTIFY (3)
  43. #define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY)
  44. #define SCB_STATUS_POS (16)
  45. #define SCB_STATUS_MASK GENMASK(SCB_STATUS_POS + SCB_MASK_WIDTH - 1, SCB_STATUS_POS)
  46. struct mpfs_mbox {
  47. struct mbox_controller controller;
  48. struct device *dev;
  49. int irq;
  50. void __iomem *ctrl_base;
  51. void __iomem *mbox_base;
  52. void __iomem *int_reg;
  53. struct mbox_chan chans[1];
  54. struct mpfs_mss_response *response;
  55. u16 resp_offset;
  56. };
  57. static bool mpfs_mbox_busy(struct mpfs_mbox *mbox)
  58. {
  59. u32 status;
  60. status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);
  61. return status & SCB_STATUS_BUSY_MASK;
  62. }
  63. static bool mpfs_mbox_last_tx_done(struct mbox_chan *chan)
  64. {
  65. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  66. return !mpfs_mbox_busy(mbox);
  67. }
  68. static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
  69. {
  70. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  71. struct mpfs_mss_msg *msg = data;
  72. u32 tx_trigger;
  73. u16 opt_sel;
  74. u32 val = 0u;
  75. mbox->response = msg->response;
  76. mbox->resp_offset = msg->resp_offset;
  77. if (mpfs_mbox_busy(mbox))
  78. return -EBUSY;
  79. if (msg->cmd_data_size) {
  80. u32 index;
  81. u8 extra_bits = msg->cmd_data_size & 3;
  82. u32 *word_buf = (u32 *)msg->cmd_data;
  83. for (index = 0; index < (msg->cmd_data_size / 4); index++)
  84. writel_relaxed(word_buf[index],
  85. mbox->mbox_base + msg->mbox_offset + index * 0x4);
  86. if (extra_bits) {
  87. u8 i;
  88. u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
  89. u8 *byte_buf = msg->cmd_data + byte_off;
  90. val = readl_relaxed(mbox->mbox_base + msg->mbox_offset + index * 0x4);
  91. for (i = 0u; i < extra_bits; i++) {
  92. val &= ~(0xffu << (i * 8u));
  93. val |= (byte_buf[i] << (i * 8u));
  94. }
  95. writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
  96. }
  97. }
  98. opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
  99. tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
  100. tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
  101. writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
  102. return 0;
  103. }
  104. static void mpfs_mbox_rx_data(struct mbox_chan *chan)
  105. {
  106. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  107. struct mpfs_mss_response *response = mbox->response;
  108. u16 num_words = ALIGN((response->resp_size), (4)) / 4U;
  109. u32 i, status;
  110. if (!response->resp_msg) {
  111. dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM);
  112. return;
  113. }
  114. /*
  115. * The status is stored in bits 31:16 of the SERVICES_SR register.
  116. * It is only valid when BUSY == 0.
  117. * We should *never* get an interrupt while the controller is
  118. * still in the busy state. If we do, something has gone badly
  119. * wrong & the content of the mailbox would not be valid.
  120. */
  121. if (mpfs_mbox_busy(mbox)) {
  122. dev_err(mbox->dev, "got an interrupt but system controller is busy\n");
  123. response->resp_status = 0xDEAD;
  124. return;
  125. }
  126. status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);
  127. /*
  128. * If the status of the individual servers is non-zero, the service has
  129. * failed. The contents of the mailbox at this point are not be valid,
  130. * so don't bother reading them. Set the status so that the driver
  131. * implementing the service can handle the result.
  132. */
  133. response->resp_status = (status & SCB_STATUS_MASK) >> SCB_STATUS_POS;
  134. if (response->resp_status)
  135. return;
  136. if (!mpfs_mbox_busy(mbox)) {
  137. for (i = 0; i < num_words; i++) {
  138. response->resp_msg[i] =
  139. readl_relaxed(mbox->mbox_base
  140. + mbox->resp_offset + i * 0x4);
  141. }
  142. }
  143. mbox_chan_received_data(chan, response);
  144. }
  145. static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
  146. {
  147. struct mbox_chan *chan = data;
  148. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  149. writel_relaxed(0, mbox->int_reg);
  150. mpfs_mbox_rx_data(chan);
  151. return IRQ_HANDLED;
  152. }
  153. static int mpfs_mbox_startup(struct mbox_chan *chan)
  154. {
  155. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  156. int ret = 0;
  157. if (!mbox)
  158. return -EINVAL;
  159. ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan);
  160. if (ret)
  161. dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret);
  162. return ret;
  163. }
  164. static void mpfs_mbox_shutdown(struct mbox_chan *chan)
  165. {
  166. struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
  167. devm_free_irq(mbox->dev, mbox->irq, chan);
  168. }
  169. static const struct mbox_chan_ops mpfs_mbox_ops = {
  170. .send_data = mpfs_mbox_send_data,
  171. .startup = mpfs_mbox_startup,
  172. .shutdown = mpfs_mbox_shutdown,
  173. .last_tx_done = mpfs_mbox_last_tx_done,
  174. };
  175. static int mpfs_mbox_probe(struct platform_device *pdev)
  176. {
  177. struct mpfs_mbox *mbox;
  178. struct resource *regs;
  179. int ret;
  180. mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
  181. if (!mbox)
  182. return -ENOMEM;
  183. mbox->ctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
  184. if (IS_ERR(mbox->ctrl_base))
  185. return PTR_ERR(mbox->ctrl_base);
  186. mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, &regs);
  187. if (IS_ERR(mbox->int_reg))
  188. return PTR_ERR(mbox->int_reg);
  189. mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 2, &regs);
  190. if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs
  191. mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET;
  192. mbox->irq = platform_get_irq(pdev, 0);
  193. if (mbox->irq < 0)
  194. return mbox->irq;
  195. mbox->dev = &pdev->dev;
  196. mbox->chans[0].con_priv = mbox;
  197. mbox->controller.dev = mbox->dev;
  198. mbox->controller.num_chans = 1;
  199. mbox->controller.chans = mbox->chans;
  200. mbox->controller.ops = &mpfs_mbox_ops;
  201. mbox->controller.txdone_poll = true;
  202. mbox->controller.txpoll_period = 10u;
  203. ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
  204. if (ret) {
  205. dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
  206. return ret;
  207. }
  208. dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");
  209. return 0;
  210. }
  211. static const struct of_device_id mpfs_mbox_of_match[] = {
  212. {.compatible = "microchip,mpfs-mailbox", },
  213. {},
  214. };
  215. MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
  216. static struct platform_driver mpfs_mbox_driver = {
  217. .driver = {
  218. .name = "mpfs-mailbox",
  219. .of_match_table = mpfs_mbox_of_match,
  220. },
  221. .probe = mpfs_mbox_probe,
  222. };
  223. module_platform_driver(mpfs_mbox_driver);
  224. MODULE_LICENSE("GPL v2");
  225. MODULE_AUTHOR("Conor Dooley <[email protected]>");
  226. MODULE_DESCRIPTION("MPFS mailbox controller driver");