hideep.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012-2017 Hideep, Inc.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/of.h>
  7. #include <linux/firmware.h>
  8. #include <linux/delay.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/i2c.h>
  11. #include <linux/acpi.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/regmap.h>
  14. #include <linux/sysfs.h>
  15. #include <linux/input.h>
  16. #include <linux/input/mt.h>
  17. #include <linux/input/touchscreen.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <asm/unaligned.h>
  20. #define HIDEEP_TS_NAME "HiDeep Touchscreen"
  21. #define HIDEEP_I2C_NAME "hideep_ts"
  22. #define HIDEEP_MT_MAX 10
  23. #define HIDEEP_KEY_MAX 3
  24. /* count(2) + touch data(100) + key data(6) */
  25. #define HIDEEP_MAX_EVENT 108UL
  26. #define HIDEEP_TOUCH_EVENT_INDEX 2
  27. #define HIDEEP_KEY_EVENT_INDEX 102
  28. /* Touch & key event */
  29. #define HIDEEP_EVENT_ADDR 0x240
  30. /* command list */
  31. #define HIDEEP_RESET_CMD 0x9800
  32. /* event bit */
  33. #define HIDEEP_MT_RELEASED BIT(4)
  34. #define HIDEEP_KEY_PRESSED BIT(7)
  35. #define HIDEEP_KEY_FIRST_PRESSED BIT(8)
  36. #define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \
  37. HIDEEP_KEY_FIRST_PRESSED)
  38. #define HIDEEP_KEY_IDX_MASK 0x0f
  39. /* For NVM */
  40. #define HIDEEP_YRAM_BASE 0x40000000
  41. #define HIDEEP_PERIPHERAL_BASE 0x50000000
  42. #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000)
  43. #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000)
  44. #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000)
  45. #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000)
  46. #define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004)
  47. #define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008)
  48. #define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C)
  49. #define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010)
  50. #define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014)
  51. #define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018)
  52. #define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020)
  53. #define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4)
  54. #define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000)
  55. #define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004)
  56. #define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008)
  57. #define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C)
  58. #define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010)
  59. #define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000)
  60. #define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008)
  61. #define HIDEEP_PERASE 0x00040000
  62. #define HIDEEP_WRONLY 0x00100000
  63. #define HIDEEP_NVM_MASK_OFS 0x0000000C
  64. #define HIDEEP_NVM_DEFAULT_PAGE 0
  65. #define HIDEEP_NVM_SFR_WPAGE 1
  66. #define HIDEEP_NVM_SFR_RPAGE 2
  67. #define HIDEEP_PIO_SIG 0x00400000
  68. #define HIDEEP_PROT_MODE 0x03400000
  69. #define HIDEEP_NVM_PAGE_SIZE 128
  70. #define HIDEEP_DWZ_INFO 0x000002C0
  71. struct hideep_event {
  72. __le16 x;
  73. __le16 y;
  74. __le16 z;
  75. u8 w;
  76. u8 flag;
  77. u8 type;
  78. u8 index;
  79. };
  80. struct dwz_info {
  81. __be32 code_start;
  82. u8 code_crc[12];
  83. __be32 c_code_start;
  84. __be16 gen_ver;
  85. __be16 c_code_len;
  86. __be32 vr_start;
  87. __be16 rsv0;
  88. __be16 vr_len;
  89. __be32 ft_start;
  90. __be16 vr_version;
  91. __be16 ft_len;
  92. __be16 core_ver;
  93. __be16 boot_ver;
  94. __be16 release_ver;
  95. __be16 custom_ver;
  96. u8 factory_id;
  97. u8 panel_type;
  98. u8 model_name[6];
  99. __be16 extra_option;
  100. __be16 product_code;
  101. __be16 vendor_id;
  102. __be16 product_id;
  103. };
  104. struct pgm_packet {
  105. struct {
  106. u8 unused[3];
  107. u8 len;
  108. __be32 addr;
  109. } header;
  110. __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
  111. };
  112. #define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet)
  113. struct hideep_ts {
  114. struct i2c_client *client;
  115. struct input_dev *input_dev;
  116. struct regmap *reg;
  117. struct touchscreen_properties prop;
  118. struct gpio_desc *reset_gpio;
  119. struct regulator *vcc_vdd;
  120. struct regulator *vcc_vid;
  121. struct mutex dev_mutex;
  122. u32 tch_count;
  123. u32 lpm_count;
  124. /*
  125. * Data buffer to read packet from the device (contacts and key
  126. * states). We align it on double-word boundary to keep word-sized
  127. * fields in contact data and double-word-sized fields in program
  128. * packet aligned.
  129. */
  130. u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
  131. int key_num;
  132. u32 key_codes[HIDEEP_KEY_MAX];
  133. struct dwz_info dwz_info;
  134. unsigned int fw_size;
  135. u32 nvm_mask;
  136. };
  137. static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
  138. const __be32 *data, size_t count)
  139. {
  140. struct pgm_packet *packet = (void *)ts->xfer_buf;
  141. size_t len = count * sizeof(*data);
  142. struct i2c_msg msg = {
  143. .addr = ts->client->addr,
  144. .len = len + sizeof(packet->header.len) +
  145. sizeof(packet->header.addr),
  146. .buf = &packet->header.len,
  147. };
  148. int ret;
  149. if (len > HIDEEP_NVM_PAGE_SIZE)
  150. return -EINVAL;
  151. packet->header.len = 0x80 | (count - 1);
  152. packet->header.addr = cpu_to_be32(addr);
  153. memcpy(packet->payload, data, len);
  154. ret = i2c_transfer(ts->client->adapter, &msg, 1);
  155. if (ret != 1)
  156. return ret < 0 ? ret : -EIO;
  157. return 0;
  158. }
  159. static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
  160. __be32 *data, size_t count)
  161. {
  162. struct pgm_packet *packet = (void *)ts->xfer_buf;
  163. size_t len = count * sizeof(*data);
  164. struct i2c_msg msg[] = {
  165. {
  166. .addr = ts->client->addr,
  167. .len = sizeof(packet->header.len) +
  168. sizeof(packet->header.addr),
  169. .buf = &packet->header.len,
  170. },
  171. {
  172. .addr = ts->client->addr,
  173. .flags = I2C_M_RD,
  174. .len = len,
  175. .buf = (u8 *)data,
  176. },
  177. };
  178. int ret;
  179. if (len > HIDEEP_NVM_PAGE_SIZE)
  180. return -EINVAL;
  181. packet->header.len = count - 1;
  182. packet->header.addr = cpu_to_be32(addr);
  183. ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
  184. if (ret != ARRAY_SIZE(msg))
  185. return ret < 0 ? ret : -EIO;
  186. return 0;
  187. }
  188. static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
  189. {
  190. __be32 data;
  191. int error;
  192. error = hideep_pgm_r_mem(ts, addr, &data, 1);
  193. if (error) {
  194. dev_err(&ts->client->dev,
  195. "read of register %#08x failed: %d\n",
  196. addr, error);
  197. return error;
  198. }
  199. *val = be32_to_cpu(data);
  200. return 0;
  201. }
  202. static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
  203. {
  204. __be32 data = cpu_to_be32(val);
  205. int error;
  206. error = hideep_pgm_w_mem(ts, addr, &data, 1);
  207. if (error) {
  208. dev_err(&ts->client->dev,
  209. "write to register %#08x (%#08x) failed: %d\n",
  210. addr, val, error);
  211. return error;
  212. }
  213. return 0;
  214. }
  215. #define SW_RESET_IN_PGM(clk) \
  216. { \
  217. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
  218. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \
  219. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01); \
  220. }
  221. #define SET_FLASH_PIO(ce) \
  222. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \
  223. 0x01 | ((ce) << 1))
  224. #define SET_PIO_SIG(x, y) \
  225. hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
  226. #define SET_FLASH_HWCONTROL() \
  227. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
  228. #define NVM_W_SFR(x, y) \
  229. { \
  230. SET_FLASH_PIO(1); \
  231. SET_PIO_SIG(x, y); \
  232. SET_FLASH_PIO(0); \
  233. }
  234. static void hideep_pgm_set(struct hideep_ts *ts)
  235. {
  236. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
  237. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
  238. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
  239. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
  240. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
  241. hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
  242. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
  243. }
  244. static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
  245. {
  246. u16 p1 = 0xAF39;
  247. u16 p2 = 0xDF9D;
  248. int error;
  249. error = regmap_bulk_write(ts->reg, p1, &p2, 1);
  250. if (error) {
  251. dev_err(&ts->client->dev,
  252. "%s: regmap_bulk_write() failed with %d\n",
  253. __func__, error);
  254. return error;
  255. }
  256. usleep_range(1000, 1100);
  257. /* flush invalid Tx load register */
  258. error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
  259. if (error)
  260. return error;
  261. error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
  262. if (error)
  263. return error;
  264. return 0;
  265. }
  266. static int hideep_enter_pgm(struct hideep_ts *ts)
  267. {
  268. int retry_count = 10;
  269. u32 pattern;
  270. int error;
  271. while (retry_count--) {
  272. error = hideep_pgm_get_pattern(ts, &pattern);
  273. if (error) {
  274. dev_err(&ts->client->dev,
  275. "hideep_pgm_get_pattern failed: %d\n", error);
  276. } else if (pattern != 0x39AF9DDF) {
  277. dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
  278. __func__, pattern);
  279. } else {
  280. dev_dbg(&ts->client->dev, "found magic code");
  281. hideep_pgm_set(ts);
  282. usleep_range(1000, 1100);
  283. return 0;
  284. }
  285. }
  286. dev_err(&ts->client->dev, "failed to enter pgm mode\n");
  287. SW_RESET_IN_PGM(1000);
  288. return -EIO;
  289. }
  290. static int hideep_nvm_unlock(struct hideep_ts *ts)
  291. {
  292. u32 unmask_code;
  293. int error;
  294. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
  295. error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
  296. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  297. if (error)
  298. return error;
  299. /* make it unprotected code */
  300. unmask_code &= ~HIDEEP_PROT_MODE;
  301. /* compare unmask code */
  302. if (unmask_code != ts->nvm_mask)
  303. dev_warn(&ts->client->dev,
  304. "read mask code different %#08x vs %#08x",
  305. unmask_code, ts->nvm_mask);
  306. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
  307. SET_FLASH_PIO(0);
  308. NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
  309. SET_FLASH_HWCONTROL();
  310. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  311. return 0;
  312. }
  313. static int hideep_check_status(struct hideep_ts *ts)
  314. {
  315. int time_out = 100;
  316. int status;
  317. int error;
  318. while (time_out--) {
  319. error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
  320. if (!error && status)
  321. return 0;
  322. usleep_range(1000, 1100);
  323. }
  324. return -ETIMEDOUT;
  325. }
  326. static int hideep_program_page(struct hideep_ts *ts, u32 addr,
  327. const __be32 *ucode, size_t xfer_count)
  328. {
  329. u32 val;
  330. int error;
  331. error = hideep_check_status(ts);
  332. if (error)
  333. return -EBUSY;
  334. addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
  335. SET_FLASH_PIO(0);
  336. SET_FLASH_PIO(1);
  337. /* erase page */
  338. SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
  339. SET_FLASH_PIO(0);
  340. error = hideep_check_status(ts);
  341. if (error)
  342. return -EBUSY;
  343. /* write page */
  344. SET_FLASH_PIO(1);
  345. val = be32_to_cpu(ucode[0]);
  346. SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
  347. hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
  348. ucode, xfer_count);
  349. val = be32_to_cpu(ucode[xfer_count - 1]);
  350. SET_PIO_SIG(124, val);
  351. SET_FLASH_PIO(0);
  352. usleep_range(1000, 1100);
  353. error = hideep_check_status(ts);
  354. if (error)
  355. return -EBUSY;
  356. SET_FLASH_HWCONTROL();
  357. return 0;
  358. }
  359. static int hideep_program_nvm(struct hideep_ts *ts,
  360. const __be32 *ucode, size_t ucode_len)
  361. {
  362. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  363. __be32 *current_ucode = packet_r->payload;
  364. size_t xfer_len;
  365. size_t xfer_count;
  366. u32 addr = 0;
  367. int error;
  368. error = hideep_nvm_unlock(ts);
  369. if (error)
  370. return error;
  371. while (ucode_len > 0) {
  372. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  373. xfer_count = xfer_len / sizeof(*ucode);
  374. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  375. current_ucode, xfer_count);
  376. if (error) {
  377. dev_err(&ts->client->dev,
  378. "%s: failed to read page at offset %#08x: %d\n",
  379. __func__, addr, error);
  380. return error;
  381. }
  382. /* See if the page needs updating */
  383. if (memcmp(ucode, current_ucode, xfer_len)) {
  384. error = hideep_program_page(ts, addr,
  385. ucode, xfer_count);
  386. if (error) {
  387. dev_err(&ts->client->dev,
  388. "%s: iwrite failure @%#08x: %d\n",
  389. __func__, addr, error);
  390. return error;
  391. }
  392. usleep_range(1000, 1100);
  393. }
  394. ucode += xfer_count;
  395. addr += xfer_len;
  396. ucode_len -= xfer_len;
  397. }
  398. return 0;
  399. }
  400. static int hideep_verify_nvm(struct hideep_ts *ts,
  401. const __be32 *ucode, size_t ucode_len)
  402. {
  403. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  404. __be32 *current_ucode = packet_r->payload;
  405. size_t xfer_len;
  406. size_t xfer_count;
  407. u32 addr = 0;
  408. int i;
  409. int error;
  410. while (ucode_len > 0) {
  411. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  412. xfer_count = xfer_len / sizeof(*ucode);
  413. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  414. current_ucode, xfer_count);
  415. if (error) {
  416. dev_err(&ts->client->dev,
  417. "%s: failed to read page at offset %#08x: %d\n",
  418. __func__, addr, error);
  419. return error;
  420. }
  421. if (memcmp(ucode, current_ucode, xfer_len)) {
  422. const u8 *ucode_bytes = (const u8 *)ucode;
  423. const u8 *current_bytes = (const u8 *)current_ucode;
  424. for (i = 0; i < xfer_len; i++)
  425. if (ucode_bytes[i] != current_bytes[i])
  426. dev_err(&ts->client->dev,
  427. "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
  428. __func__, addr + i,
  429. ucode_bytes[i],
  430. current_bytes[i]);
  431. return -EIO;
  432. }
  433. ucode += xfer_count;
  434. addr += xfer_len;
  435. ucode_len -= xfer_len;
  436. }
  437. return 0;
  438. }
  439. static int hideep_load_dwz(struct hideep_ts *ts)
  440. {
  441. u16 product_code;
  442. int error;
  443. error = hideep_enter_pgm(ts);
  444. if (error)
  445. return error;
  446. msleep(50);
  447. error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
  448. (void *)&ts->dwz_info,
  449. sizeof(ts->dwz_info) / sizeof(__be32));
  450. SW_RESET_IN_PGM(10);
  451. msleep(50);
  452. if (error) {
  453. dev_err(&ts->client->dev,
  454. "failed to fetch DWZ data: %d\n", error);
  455. return error;
  456. }
  457. product_code = be16_to_cpu(ts->dwz_info.product_code);
  458. switch (product_code & 0xF0) {
  459. case 0x40:
  460. dev_dbg(&ts->client->dev, "used crimson IC");
  461. ts->fw_size = 1024 * 48;
  462. ts->nvm_mask = 0x00310000;
  463. break;
  464. case 0x60:
  465. dev_dbg(&ts->client->dev, "used lime IC");
  466. ts->fw_size = 1024 * 64;
  467. ts->nvm_mask = 0x0030027B;
  468. break;
  469. default:
  470. dev_err(&ts->client->dev, "product code is wrong: %#04x",
  471. product_code);
  472. return -EINVAL;
  473. }
  474. dev_dbg(&ts->client->dev, "firmware release version: %#04x",
  475. be16_to_cpu(ts->dwz_info.release_ver));
  476. return 0;
  477. }
  478. static int hideep_flash_firmware(struct hideep_ts *ts,
  479. const __be32 *ucode, size_t ucode_len)
  480. {
  481. int retry_cnt = 3;
  482. int error;
  483. while (retry_cnt--) {
  484. error = hideep_program_nvm(ts, ucode, ucode_len);
  485. if (!error) {
  486. error = hideep_verify_nvm(ts, ucode, ucode_len);
  487. if (!error)
  488. return 0;
  489. }
  490. }
  491. return error;
  492. }
  493. static int hideep_update_firmware(struct hideep_ts *ts,
  494. const __be32 *ucode, size_t ucode_len)
  495. {
  496. int error, error2;
  497. dev_dbg(&ts->client->dev, "starting firmware update");
  498. /* enter program mode */
  499. error = hideep_enter_pgm(ts);
  500. if (error)
  501. return error;
  502. error = hideep_flash_firmware(ts, ucode, ucode_len);
  503. if (error)
  504. dev_err(&ts->client->dev,
  505. "firmware update failed: %d\n", error);
  506. else
  507. dev_dbg(&ts->client->dev, "firmware updated successfully\n");
  508. SW_RESET_IN_PGM(1000);
  509. error2 = hideep_load_dwz(ts);
  510. if (error2)
  511. dev_err(&ts->client->dev,
  512. "failed to load dwz after firmware update: %d\n",
  513. error2);
  514. return error ?: error2;
  515. }
  516. static int hideep_power_on(struct hideep_ts *ts)
  517. {
  518. int error = 0;
  519. error = regulator_enable(ts->vcc_vdd);
  520. if (error)
  521. dev_err(&ts->client->dev,
  522. "failed to enable 'vdd' regulator: %d", error);
  523. usleep_range(999, 1000);
  524. error = regulator_enable(ts->vcc_vid);
  525. if (error)
  526. dev_err(&ts->client->dev,
  527. "failed to enable 'vcc_vid' regulator: %d",
  528. error);
  529. msleep(30);
  530. if (ts->reset_gpio) {
  531. gpiod_set_value_cansleep(ts->reset_gpio, 0);
  532. } else {
  533. error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
  534. if (error)
  535. dev_err(&ts->client->dev,
  536. "failed to send 'reset' command: %d\n", error);
  537. }
  538. msleep(50);
  539. return error;
  540. }
  541. static void hideep_power_off(void *data)
  542. {
  543. struct hideep_ts *ts = data;
  544. if (ts->reset_gpio)
  545. gpiod_set_value(ts->reset_gpio, 1);
  546. regulator_disable(ts->vcc_vid);
  547. regulator_disable(ts->vcc_vdd);
  548. }
  549. #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
  550. static void hideep_report_slot(struct input_dev *input,
  551. const struct hideep_event *event)
  552. {
  553. input_mt_slot(input, event->index & 0x0f);
  554. input_mt_report_slot_state(input,
  555. __GET_MT_TOOL_TYPE(event->type),
  556. !(event->flag & HIDEEP_MT_RELEASED));
  557. if (!(event->flag & HIDEEP_MT_RELEASED)) {
  558. input_report_abs(input, ABS_MT_POSITION_X,
  559. le16_to_cpup(&event->x));
  560. input_report_abs(input, ABS_MT_POSITION_Y,
  561. le16_to_cpup(&event->y));
  562. input_report_abs(input, ABS_MT_PRESSURE,
  563. le16_to_cpup(&event->z));
  564. input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
  565. }
  566. }
  567. static void hideep_parse_and_report(struct hideep_ts *ts)
  568. {
  569. const struct hideep_event *events =
  570. (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
  571. const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
  572. int touch_count = ts->xfer_buf[0];
  573. int key_count = ts->xfer_buf[1] & 0x0f;
  574. int lpm_count = ts->xfer_buf[1] & 0xf0;
  575. int i;
  576. /* get touch event count */
  577. dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
  578. touch_count, key_count, lpm_count);
  579. touch_count = min(touch_count, HIDEEP_MT_MAX);
  580. for (i = 0; i < touch_count; i++)
  581. hideep_report_slot(ts->input_dev, events + i);
  582. key_count = min(key_count, HIDEEP_KEY_MAX);
  583. for (i = 0; i < key_count; i++) {
  584. u8 key_data = keys[i * 2];
  585. input_report_key(ts->input_dev,
  586. ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
  587. key_data & HIDEEP_KEY_PRESSED_MASK);
  588. }
  589. input_mt_sync_frame(ts->input_dev);
  590. input_sync(ts->input_dev);
  591. }
  592. static irqreturn_t hideep_irq(int irq, void *handle)
  593. {
  594. struct hideep_ts *ts = handle;
  595. int error;
  596. BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
  597. error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
  598. ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
  599. if (error) {
  600. dev_err(&ts->client->dev, "failed to read events: %d\n", error);
  601. goto out;
  602. }
  603. hideep_parse_and_report(ts);
  604. out:
  605. return IRQ_HANDLED;
  606. }
  607. static int hideep_get_axis_info(struct hideep_ts *ts)
  608. {
  609. __le16 val[2];
  610. int error;
  611. error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
  612. if (error)
  613. return error;
  614. ts->prop.max_x = le16_to_cpup(val);
  615. ts->prop.max_y = le16_to_cpup(val + 1);
  616. dev_dbg(&ts->client->dev, "X: %d, Y: %d",
  617. ts->prop.max_x, ts->prop.max_y);
  618. return 0;
  619. }
  620. static int hideep_init_input(struct hideep_ts *ts)
  621. {
  622. struct device *dev = &ts->client->dev;
  623. int i;
  624. int error;
  625. ts->input_dev = devm_input_allocate_device(dev);
  626. if (!ts->input_dev) {
  627. dev_err(dev, "failed to allocate input device\n");
  628. return -ENOMEM;
  629. }
  630. ts->input_dev->name = HIDEEP_TS_NAME;
  631. ts->input_dev->id.bustype = BUS_I2C;
  632. input_set_drvdata(ts->input_dev, ts);
  633. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
  634. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
  635. input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
  636. input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
  637. input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
  638. 0, MT_TOOL_MAX, 0, 0);
  639. touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
  640. if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
  641. error = hideep_get_axis_info(ts);
  642. if (error)
  643. return error;
  644. }
  645. error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
  646. INPUT_MT_DIRECT);
  647. if (error)
  648. return error;
  649. ts->key_num = device_property_count_u32(dev, "linux,keycodes");
  650. if (ts->key_num > HIDEEP_KEY_MAX) {
  651. dev_err(dev, "too many keys defined: %d\n",
  652. ts->key_num);
  653. return -EINVAL;
  654. }
  655. if (ts->key_num <= 0) {
  656. dev_dbg(dev,
  657. "missing or malformed 'linux,keycodes' property\n");
  658. } else {
  659. error = device_property_read_u32_array(dev, "linux,keycodes",
  660. ts->key_codes,
  661. ts->key_num);
  662. if (error) {
  663. dev_dbg(dev, "failed to read keymap: %d", error);
  664. return error;
  665. }
  666. if (ts->key_num) {
  667. ts->input_dev->keycode = ts->key_codes;
  668. ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
  669. ts->input_dev->keycodemax = ts->key_num;
  670. for (i = 0; i < ts->key_num; i++)
  671. input_set_capability(ts->input_dev, EV_KEY,
  672. ts->key_codes[i]);
  673. }
  674. }
  675. error = input_register_device(ts->input_dev);
  676. if (error) {
  677. dev_err(dev, "failed to register input device: %d", error);
  678. return error;
  679. }
  680. return 0;
  681. }
  682. static ssize_t hideep_update_fw(struct device *dev,
  683. struct device_attribute *attr,
  684. const char *buf, size_t count)
  685. {
  686. struct i2c_client *client = to_i2c_client(dev);
  687. struct hideep_ts *ts = i2c_get_clientdata(client);
  688. const struct firmware *fw_entry;
  689. char *fw_name;
  690. int mode;
  691. int error;
  692. error = kstrtoint(buf, 0, &mode);
  693. if (error)
  694. return error;
  695. fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
  696. be16_to_cpu(ts->dwz_info.product_id));
  697. if (!fw_name)
  698. return -ENOMEM;
  699. error = request_firmware(&fw_entry, fw_name, dev);
  700. if (error) {
  701. dev_err(dev, "failed to request firmware %s: %d",
  702. fw_name, error);
  703. goto out_free_fw_name;
  704. }
  705. if (fw_entry->size % sizeof(__be32)) {
  706. dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
  707. error = -EINVAL;
  708. goto out_release_fw;
  709. }
  710. if (fw_entry->size > ts->fw_size) {
  711. dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
  712. fw_entry->size, ts->fw_size);
  713. error = -EFBIG;
  714. goto out_release_fw;
  715. }
  716. mutex_lock(&ts->dev_mutex);
  717. disable_irq(client->irq);
  718. error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
  719. fw_entry->size);
  720. enable_irq(client->irq);
  721. mutex_unlock(&ts->dev_mutex);
  722. out_release_fw:
  723. release_firmware(fw_entry);
  724. out_free_fw_name:
  725. kfree(fw_name);
  726. return error ?: count;
  727. }
  728. static ssize_t hideep_fw_version_show(struct device *dev,
  729. struct device_attribute *attr, char *buf)
  730. {
  731. struct i2c_client *client = to_i2c_client(dev);
  732. struct hideep_ts *ts = i2c_get_clientdata(client);
  733. ssize_t len;
  734. mutex_lock(&ts->dev_mutex);
  735. len = scnprintf(buf, PAGE_SIZE, "%04x\n",
  736. be16_to_cpu(ts->dwz_info.release_ver));
  737. mutex_unlock(&ts->dev_mutex);
  738. return len;
  739. }
  740. static ssize_t hideep_product_id_show(struct device *dev,
  741. struct device_attribute *attr, char *buf)
  742. {
  743. struct i2c_client *client = to_i2c_client(dev);
  744. struct hideep_ts *ts = i2c_get_clientdata(client);
  745. ssize_t len;
  746. mutex_lock(&ts->dev_mutex);
  747. len = scnprintf(buf, PAGE_SIZE, "%04x\n",
  748. be16_to_cpu(ts->dwz_info.product_id));
  749. mutex_unlock(&ts->dev_mutex);
  750. return len;
  751. }
  752. static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
  753. static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
  754. static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
  755. static struct attribute *hideep_ts_sysfs_entries[] = {
  756. &dev_attr_version.attr,
  757. &dev_attr_product_id.attr,
  758. &dev_attr_update_fw.attr,
  759. NULL,
  760. };
  761. static const struct attribute_group hideep_ts_attr_group = {
  762. .attrs = hideep_ts_sysfs_entries,
  763. };
  764. static int __maybe_unused hideep_suspend(struct device *dev)
  765. {
  766. struct i2c_client *client = to_i2c_client(dev);
  767. struct hideep_ts *ts = i2c_get_clientdata(client);
  768. disable_irq(client->irq);
  769. hideep_power_off(ts);
  770. return 0;
  771. }
  772. static int __maybe_unused hideep_resume(struct device *dev)
  773. {
  774. struct i2c_client *client = to_i2c_client(dev);
  775. struct hideep_ts *ts = i2c_get_clientdata(client);
  776. int error;
  777. error = hideep_power_on(ts);
  778. if (error) {
  779. dev_err(&client->dev, "power on failed");
  780. return error;
  781. }
  782. enable_irq(client->irq);
  783. return 0;
  784. }
  785. static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
  786. static const struct regmap_config hideep_regmap_config = {
  787. .reg_bits = 16,
  788. .reg_format_endian = REGMAP_ENDIAN_LITTLE,
  789. .val_bits = 16,
  790. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  791. .max_register = 0xffff,
  792. };
  793. static int hideep_probe(struct i2c_client *client,
  794. const struct i2c_device_id *id)
  795. {
  796. struct hideep_ts *ts;
  797. int error;
  798. /* check i2c bus */
  799. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  800. dev_err(&client->dev, "check i2c device error");
  801. return -ENODEV;
  802. }
  803. if (client->irq <= 0) {
  804. dev_err(&client->dev, "missing irq: %d\n", client->irq);
  805. return -EINVAL;
  806. }
  807. ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
  808. if (!ts)
  809. return -ENOMEM;
  810. ts->client = client;
  811. i2c_set_clientdata(client, ts);
  812. mutex_init(&ts->dev_mutex);
  813. ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
  814. if (IS_ERR(ts->reg)) {
  815. error = PTR_ERR(ts->reg);
  816. dev_err(&client->dev,
  817. "failed to initialize regmap: %d\n", error);
  818. return error;
  819. }
  820. ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
  821. if (IS_ERR(ts->vcc_vdd))
  822. return PTR_ERR(ts->vcc_vdd);
  823. ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
  824. if (IS_ERR(ts->vcc_vid))
  825. return PTR_ERR(ts->vcc_vid);
  826. ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
  827. "reset", GPIOD_OUT_HIGH);
  828. if (IS_ERR(ts->reset_gpio))
  829. return PTR_ERR(ts->reset_gpio);
  830. error = hideep_power_on(ts);
  831. if (error) {
  832. dev_err(&client->dev, "power on failed: %d\n", error);
  833. return error;
  834. }
  835. error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
  836. if (error)
  837. return error;
  838. error = hideep_load_dwz(ts);
  839. if (error) {
  840. dev_err(&client->dev, "failed to load dwz: %d", error);
  841. return error;
  842. }
  843. error = hideep_init_input(ts);
  844. if (error)
  845. return error;
  846. error = devm_request_threaded_irq(&client->dev, client->irq,
  847. NULL, hideep_irq, IRQF_ONESHOT,
  848. client->name, ts);
  849. if (error) {
  850. dev_err(&client->dev, "failed to request irq %d: %d\n",
  851. client->irq, error);
  852. return error;
  853. }
  854. error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
  855. if (error) {
  856. dev_err(&client->dev,
  857. "failed to add sysfs attributes: %d\n", error);
  858. return error;
  859. }
  860. return 0;
  861. }
  862. static const struct i2c_device_id hideep_i2c_id[] = {
  863. { HIDEEP_I2C_NAME, 0 },
  864. { }
  865. };
  866. MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
  867. #ifdef CONFIG_ACPI
  868. static const struct acpi_device_id hideep_acpi_id[] = {
  869. { "HIDP0001", 0 },
  870. { }
  871. };
  872. MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
  873. #endif
  874. #ifdef CONFIG_OF
  875. static const struct of_device_id hideep_match_table[] = {
  876. { .compatible = "hideep,hideep-ts" },
  877. { }
  878. };
  879. MODULE_DEVICE_TABLE(of, hideep_match_table);
  880. #endif
  881. static struct i2c_driver hideep_driver = {
  882. .driver = {
  883. .name = HIDEEP_I2C_NAME,
  884. .of_match_table = of_match_ptr(hideep_match_table),
  885. .acpi_match_table = ACPI_PTR(hideep_acpi_id),
  886. .pm = &hideep_pm_ops,
  887. },
  888. .id_table = hideep_i2c_id,
  889. .probe = hideep_probe,
  890. };
  891. module_i2c_driver(hideep_driver);
  892. MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
  893. MODULE_AUTHOR("[email protected]");
  894. MODULE_LICENSE("GPL v2");