verbs.c 126 KB

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  1. // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
  2. /* Copyright (c) 2015 - 2021 Intel Corporation */
  3. #include "main.h"
  4. /**
  5. * irdma_query_device - get device attributes
  6. * @ibdev: device pointer from stack
  7. * @props: returning device attributes
  8. * @udata: user data
  9. */
  10. static int irdma_query_device(struct ib_device *ibdev,
  11. struct ib_device_attr *props,
  12. struct ib_udata *udata)
  13. {
  14. struct irdma_device *iwdev = to_iwdev(ibdev);
  15. struct irdma_pci_f *rf = iwdev->rf;
  16. struct pci_dev *pcidev = iwdev->rf->pcidev;
  17. struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs;
  18. if (udata->inlen || udata->outlen)
  19. return -EINVAL;
  20. memset(props, 0, sizeof(*props));
  21. addrconf_addr_eui48((u8 *)&props->sys_image_guid,
  22. iwdev->netdev->dev_addr);
  23. props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 |
  24. irdma_fw_minor_ver(&rf->sc_dev);
  25. props->device_cap_flags = IB_DEVICE_MEM_WINDOW |
  26. IB_DEVICE_MEM_MGT_EXTENSIONS;
  27. props->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
  28. props->vendor_id = pcidev->vendor;
  29. props->vendor_part_id = pcidev->device;
  30. props->hw_ver = rf->pcidev->revision;
  31. props->page_size_cap = hw_attrs->page_size_cap;
  32. props->max_mr_size = hw_attrs->max_mr_size;
  33. props->max_qp = rf->max_qp - rf->used_qps;
  34. props->max_qp_wr = hw_attrs->max_qp_wr;
  35. props->max_send_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
  36. props->max_recv_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
  37. props->max_cq = rf->max_cq - rf->used_cqs;
  38. props->max_cqe = rf->max_cqe - 1;
  39. props->max_mr = rf->max_mr - rf->used_mrs;
  40. props->max_mw = props->max_mr;
  41. props->max_pd = rf->max_pd - rf->used_pds;
  42. props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges;
  43. props->max_qp_rd_atom = hw_attrs->max_hw_ird;
  44. props->max_qp_init_rd_atom = hw_attrs->max_hw_ord;
  45. if (rdma_protocol_roce(ibdev, 1)) {
  46. props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN;
  47. props->max_pkeys = IRDMA_PKEY_TBL_SZ;
  48. }
  49. props->max_ah = rf->max_ah;
  50. props->max_mcast_grp = rf->max_mcg;
  51. props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX;
  52. props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX;
  53. props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR;
  54. #define HCA_CLOCK_TIMESTAMP_MASK 0x1ffff
  55. if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_2)
  56. props->timestamp_mask = HCA_CLOCK_TIMESTAMP_MASK;
  57. return 0;
  58. }
  59. /**
  60. * irdma_query_port - get port attributes
  61. * @ibdev: device pointer from stack
  62. * @port: port number for query
  63. * @props: returning device attributes
  64. */
  65. static int irdma_query_port(struct ib_device *ibdev, u32 port,
  66. struct ib_port_attr *props)
  67. {
  68. struct irdma_device *iwdev = to_iwdev(ibdev);
  69. struct net_device *netdev = iwdev->netdev;
  70. /* no need to zero out pros here. done by caller */
  71. props->max_mtu = IB_MTU_4096;
  72. props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
  73. props->lid = 1;
  74. props->lmc = 0;
  75. props->sm_lid = 0;
  76. props->sm_sl = 0;
  77. if (netif_carrier_ok(netdev) && netif_running(netdev)) {
  78. props->state = IB_PORT_ACTIVE;
  79. props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
  80. } else {
  81. props->state = IB_PORT_DOWN;
  82. props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
  83. }
  84. ib_get_eth_speed(ibdev, port, &props->active_speed,
  85. &props->active_width);
  86. if (rdma_protocol_roce(ibdev, 1)) {
  87. props->gid_tbl_len = 32;
  88. props->ip_gids = true;
  89. props->pkey_tbl_len = IRDMA_PKEY_TBL_SZ;
  90. } else {
  91. props->gid_tbl_len = 1;
  92. }
  93. props->qkey_viol_cntr = 0;
  94. props->port_cap_flags |= IB_PORT_CM_SUP | IB_PORT_REINIT_SUP;
  95. props->max_msg_sz = iwdev->rf->sc_dev.hw_attrs.max_hw_outbound_msg_size;
  96. return 0;
  97. }
  98. /**
  99. * irdma_disassociate_ucontext - Disassociate user context
  100. * @context: ib user context
  101. */
  102. static void irdma_disassociate_ucontext(struct ib_ucontext *context)
  103. {
  104. }
  105. static int irdma_mmap_legacy(struct irdma_ucontext *ucontext,
  106. struct vm_area_struct *vma)
  107. {
  108. u64 pfn;
  109. if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
  110. return -EINVAL;
  111. vma->vm_private_data = ucontext;
  112. pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] +
  113. pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
  114. return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE,
  115. pgprot_noncached(vma->vm_page_prot), NULL);
  116. }
  117. static void irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
  118. {
  119. struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry);
  120. kfree(entry);
  121. }
  122. static struct rdma_user_mmap_entry*
  123. irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset,
  124. enum irdma_mmap_flag mmap_flag, u64 *mmap_offset)
  125. {
  126. struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  127. int ret;
  128. if (!entry)
  129. return NULL;
  130. entry->bar_offset = bar_offset;
  131. entry->mmap_flag = mmap_flag;
  132. ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext,
  133. &entry->rdma_entry, PAGE_SIZE);
  134. if (ret) {
  135. kfree(entry);
  136. return NULL;
  137. }
  138. *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
  139. return &entry->rdma_entry;
  140. }
  141. /**
  142. * irdma_mmap - user memory map
  143. * @context: context created during alloc
  144. * @vma: kernel info for user memory map
  145. */
  146. static int irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  147. {
  148. struct rdma_user_mmap_entry *rdma_entry;
  149. struct irdma_user_mmap_entry *entry;
  150. struct irdma_ucontext *ucontext;
  151. u64 pfn;
  152. int ret;
  153. ucontext = to_ucontext(context);
  154. /* Legacy support for libi40iw with hard-coded mmap key */
  155. if (ucontext->legacy_mode)
  156. return irdma_mmap_legacy(ucontext, vma);
  157. rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma);
  158. if (!rdma_entry) {
  159. ibdev_dbg(&ucontext->iwdev->ibdev,
  160. "VERBS: pgoff[0x%lx] does not have valid entry\n",
  161. vma->vm_pgoff);
  162. return -EINVAL;
  163. }
  164. entry = to_irdma_mmap_entry(rdma_entry);
  165. ibdev_dbg(&ucontext->iwdev->ibdev,
  166. "VERBS: bar_offset [0x%llx] mmap_flag [%d]\n",
  167. entry->bar_offset, entry->mmap_flag);
  168. pfn = (entry->bar_offset +
  169. pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
  170. switch (entry->mmap_flag) {
  171. case IRDMA_MMAP_IO_NC:
  172. ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
  173. pgprot_noncached(vma->vm_page_prot),
  174. rdma_entry);
  175. break;
  176. case IRDMA_MMAP_IO_WC:
  177. ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
  178. pgprot_writecombine(vma->vm_page_prot),
  179. rdma_entry);
  180. break;
  181. default:
  182. ret = -EINVAL;
  183. }
  184. if (ret)
  185. ibdev_dbg(&ucontext->iwdev->ibdev,
  186. "VERBS: bar_offset [0x%llx] mmap_flag[%d] err[%d]\n",
  187. entry->bar_offset, entry->mmap_flag, ret);
  188. rdma_user_mmap_entry_put(rdma_entry);
  189. return ret;
  190. }
  191. /**
  192. * irdma_alloc_push_page - allocate a push page for qp
  193. * @iwqp: qp pointer
  194. */
  195. static void irdma_alloc_push_page(struct irdma_qp *iwqp)
  196. {
  197. struct irdma_cqp_request *cqp_request;
  198. struct cqp_cmds_info *cqp_info;
  199. struct irdma_device *iwdev = iwqp->iwdev;
  200. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  201. int status;
  202. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  203. if (!cqp_request)
  204. return;
  205. cqp_info = &cqp_request->info;
  206. cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
  207. cqp_info->post_sq = 1;
  208. cqp_info->in.u.manage_push_page.info.push_idx = 0;
  209. cqp_info->in.u.manage_push_page.info.qs_handle =
  210. qp->vsi->qos[qp->user_pri].qs_handle;
  211. cqp_info->in.u.manage_push_page.info.free_page = 0;
  212. cqp_info->in.u.manage_push_page.info.push_page_type = 0;
  213. cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp;
  214. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  215. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  216. if (!status && cqp_request->compl_info.op_ret_val <
  217. iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) {
  218. qp->push_idx = cqp_request->compl_info.op_ret_val;
  219. qp->push_offset = 0;
  220. }
  221. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  222. }
  223. /**
  224. * irdma_alloc_ucontext - Allocate the user context data structure
  225. * @uctx: uverbs context pointer
  226. * @udata: user data
  227. *
  228. * This keeps track of all objects associated with a particular
  229. * user-mode client.
  230. */
  231. static int irdma_alloc_ucontext(struct ib_ucontext *uctx,
  232. struct ib_udata *udata)
  233. {
  234. #define IRDMA_ALLOC_UCTX_MIN_REQ_LEN offsetofend(struct irdma_alloc_ucontext_req, rsvd8)
  235. #define IRDMA_ALLOC_UCTX_MIN_RESP_LEN offsetofend(struct irdma_alloc_ucontext_resp, rsvd)
  236. struct ib_device *ibdev = uctx->device;
  237. struct irdma_device *iwdev = to_iwdev(ibdev);
  238. struct irdma_alloc_ucontext_req req = {};
  239. struct irdma_alloc_ucontext_resp uresp = {};
  240. struct irdma_ucontext *ucontext = to_ucontext(uctx);
  241. struct irdma_uk_attrs *uk_attrs;
  242. if (udata->inlen < IRDMA_ALLOC_UCTX_MIN_REQ_LEN ||
  243. udata->outlen < IRDMA_ALLOC_UCTX_MIN_RESP_LEN)
  244. return -EINVAL;
  245. if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen)))
  246. return -EINVAL;
  247. if (req.userspace_ver < 4 || req.userspace_ver > IRDMA_ABI_VER)
  248. goto ver_error;
  249. ucontext->iwdev = iwdev;
  250. ucontext->abi_ver = req.userspace_ver;
  251. uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;
  252. /* GEN_1 legacy support with libi40iw */
  253. if (udata->outlen == IRDMA_ALLOC_UCTX_MIN_RESP_LEN) {
  254. if (uk_attrs->hw_rev != IRDMA_GEN_1)
  255. return -EOPNOTSUPP;
  256. ucontext->legacy_mode = true;
  257. uresp.max_qps = iwdev->rf->max_qp;
  258. uresp.max_pds = iwdev->rf->sc_dev.hw_attrs.max_hw_pds;
  259. uresp.wq_size = iwdev->rf->sc_dev.hw_attrs.max_qp_wr * 2;
  260. uresp.kernel_ver = req.userspace_ver;
  261. if (ib_copy_to_udata(udata, &uresp,
  262. min(sizeof(uresp), udata->outlen)))
  263. return -EFAULT;
  264. } else {
  265. u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
  266. ucontext->db_mmap_entry =
  267. irdma_user_mmap_entry_insert(ucontext, bar_off,
  268. IRDMA_MMAP_IO_NC,
  269. &uresp.db_mmap_key);
  270. if (!ucontext->db_mmap_entry)
  271. return -ENOMEM;
  272. uresp.kernel_ver = IRDMA_ABI_VER;
  273. uresp.feature_flags = uk_attrs->feature_flags;
  274. uresp.max_hw_wq_frags = uk_attrs->max_hw_wq_frags;
  275. uresp.max_hw_read_sges = uk_attrs->max_hw_read_sges;
  276. uresp.max_hw_inline = uk_attrs->max_hw_inline;
  277. uresp.max_hw_rq_quanta = uk_attrs->max_hw_rq_quanta;
  278. uresp.max_hw_wq_quanta = uk_attrs->max_hw_wq_quanta;
  279. uresp.max_hw_sq_chunk = uk_attrs->max_hw_sq_chunk;
  280. uresp.max_hw_cq_size = uk_attrs->max_hw_cq_size;
  281. uresp.min_hw_cq_size = uk_attrs->min_hw_cq_size;
  282. uresp.hw_rev = uk_attrs->hw_rev;
  283. if (ib_copy_to_udata(udata, &uresp,
  284. min(sizeof(uresp), udata->outlen))) {
  285. rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
  286. return -EFAULT;
  287. }
  288. }
  289. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  290. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  291. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  292. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  293. return 0;
  294. ver_error:
  295. ibdev_err(&iwdev->ibdev,
  296. "Invalid userspace driver version detected. Detected version %d, should be %d\n",
  297. req.userspace_ver, IRDMA_ABI_VER);
  298. return -EINVAL;
  299. }
  300. /**
  301. * irdma_dealloc_ucontext - deallocate the user context data structure
  302. * @context: user context created during alloc
  303. */
  304. static void irdma_dealloc_ucontext(struct ib_ucontext *context)
  305. {
  306. struct irdma_ucontext *ucontext = to_ucontext(context);
  307. rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
  308. }
  309. /**
  310. * irdma_alloc_pd - allocate protection domain
  311. * @pd: PD pointer
  312. * @udata: user data
  313. */
  314. static int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata)
  315. {
  316. #define IRDMA_ALLOC_PD_MIN_RESP_LEN offsetofend(struct irdma_alloc_pd_resp, rsvd)
  317. struct irdma_pd *iwpd = to_iwpd(pd);
  318. struct irdma_device *iwdev = to_iwdev(pd->device);
  319. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  320. struct irdma_pci_f *rf = iwdev->rf;
  321. struct irdma_alloc_pd_resp uresp = {};
  322. struct irdma_sc_pd *sc_pd;
  323. u32 pd_id = 0;
  324. int err;
  325. if (udata && udata->outlen < IRDMA_ALLOC_PD_MIN_RESP_LEN)
  326. return -EINVAL;
  327. err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id,
  328. &rf->next_pd);
  329. if (err)
  330. return err;
  331. sc_pd = &iwpd->sc_pd;
  332. if (udata) {
  333. struct irdma_ucontext *ucontext =
  334. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  335. ibucontext);
  336. irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
  337. uresp.pd_id = pd_id;
  338. if (ib_copy_to_udata(udata, &uresp,
  339. min(sizeof(uresp), udata->outlen))) {
  340. err = -EFAULT;
  341. goto error;
  342. }
  343. } else {
  344. irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER);
  345. }
  346. return 0;
  347. error:
  348. irdma_free_rsrc(rf, rf->allocated_pds, pd_id);
  349. return err;
  350. }
  351. /**
  352. * irdma_dealloc_pd - deallocate pd
  353. * @ibpd: ptr of pd to be deallocated
  354. * @udata: user data
  355. */
  356. static int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  357. {
  358. struct irdma_pd *iwpd = to_iwpd(ibpd);
  359. struct irdma_device *iwdev = to_iwdev(ibpd->device);
  360. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id);
  361. return 0;
  362. }
  363. /**
  364. * irdma_get_pbl - Retrieve pbl from a list given a virtual
  365. * address
  366. * @va: user virtual address
  367. * @pbl_list: pbl list to search in (QP's or CQ's)
  368. */
  369. static struct irdma_pbl *irdma_get_pbl(unsigned long va,
  370. struct list_head *pbl_list)
  371. {
  372. struct irdma_pbl *iwpbl;
  373. list_for_each_entry (iwpbl, pbl_list, list) {
  374. if (iwpbl->user_base == va) {
  375. list_del(&iwpbl->list);
  376. iwpbl->on_list = false;
  377. return iwpbl;
  378. }
  379. }
  380. return NULL;
  381. }
  382. /**
  383. * irdma_clean_cqes - clean cq entries for qp
  384. * @iwqp: qp ptr (user or kernel)
  385. * @iwcq: cq ptr
  386. */
  387. static void irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq)
  388. {
  389. struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  390. unsigned long flags;
  391. spin_lock_irqsave(&iwcq->lock, flags);
  392. irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq);
  393. spin_unlock_irqrestore(&iwcq->lock, flags);
  394. }
  395. static void irdma_remove_push_mmap_entries(struct irdma_qp *iwqp)
  396. {
  397. if (iwqp->push_db_mmap_entry) {
  398. rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry);
  399. iwqp->push_db_mmap_entry = NULL;
  400. }
  401. if (iwqp->push_wqe_mmap_entry) {
  402. rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
  403. iwqp->push_wqe_mmap_entry = NULL;
  404. }
  405. }
  406. static int irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext,
  407. struct irdma_qp *iwqp,
  408. u64 *push_wqe_mmap_key,
  409. u64 *push_db_mmap_key)
  410. {
  411. struct irdma_device *iwdev = ucontext->iwdev;
  412. u64 rsvd, bar_off;
  413. rsvd = IRDMA_PF_BAR_RSVD;
  414. bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
  415. /* skip over db page */
  416. bar_off += IRDMA_HW_PAGE_SIZE;
  417. /* push wqe page */
  418. bar_off += rsvd + iwqp->sc_qp.push_idx * IRDMA_HW_PAGE_SIZE;
  419. iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
  420. bar_off, IRDMA_MMAP_IO_WC,
  421. push_wqe_mmap_key);
  422. if (!iwqp->push_wqe_mmap_entry)
  423. return -ENOMEM;
  424. /* push doorbell page */
  425. bar_off += IRDMA_HW_PAGE_SIZE;
  426. iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
  427. bar_off, IRDMA_MMAP_IO_NC,
  428. push_db_mmap_key);
  429. if (!iwqp->push_db_mmap_entry) {
  430. rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
  431. return -ENOMEM;
  432. }
  433. return 0;
  434. }
  435. /**
  436. * irdma_destroy_qp - destroy qp
  437. * @ibqp: qp's ib pointer also to get to device's qp address
  438. * @udata: user data
  439. */
  440. static int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
  441. {
  442. struct irdma_qp *iwqp = to_iwqp(ibqp);
  443. struct irdma_device *iwdev = iwqp->iwdev;
  444. iwqp->sc_qp.qp_uk.destroy_pending = true;
  445. if (iwqp->iwarp_state == IRDMA_QP_STATE_RTS)
  446. irdma_modify_qp_to_err(&iwqp->sc_qp);
  447. if (!iwqp->user_mode)
  448. cancel_delayed_work_sync(&iwqp->dwork_flush);
  449. if (!iwqp->user_mode) {
  450. if (iwqp->iwscq) {
  451. irdma_clean_cqes(iwqp, iwqp->iwscq);
  452. if (iwqp->iwrcq != iwqp->iwscq)
  453. irdma_clean_cqes(iwqp, iwqp->iwrcq);
  454. }
  455. }
  456. irdma_qp_rem_ref(&iwqp->ibqp);
  457. wait_for_completion(&iwqp->free_qp);
  458. irdma_free_lsmm_rsrc(iwqp);
  459. irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp);
  460. irdma_remove_push_mmap_entries(iwqp);
  461. irdma_free_qp_rsrc(iwqp);
  462. return 0;
  463. }
  464. /**
  465. * irdma_setup_virt_qp - setup for allocation of virtual qp
  466. * @iwdev: irdma device
  467. * @iwqp: qp ptr
  468. * @init_info: initialize info to return
  469. */
  470. static void irdma_setup_virt_qp(struct irdma_device *iwdev,
  471. struct irdma_qp *iwqp,
  472. struct irdma_qp_init_info *init_info)
  473. {
  474. struct irdma_pbl *iwpbl = iwqp->iwpbl;
  475. struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
  476. iwqp->page = qpmr->sq_page;
  477. init_info->shadow_area_pa = qpmr->shadow;
  478. if (iwpbl->pbl_allocated) {
  479. init_info->virtual_map = true;
  480. init_info->sq_pa = qpmr->sq_pbl.idx;
  481. init_info->rq_pa = qpmr->rq_pbl.idx;
  482. } else {
  483. init_info->sq_pa = qpmr->sq_pbl.addr;
  484. init_info->rq_pa = qpmr->rq_pbl.addr;
  485. }
  486. }
  487. /**
  488. * irdma_setup_kmode_qp - setup initialization for kernel mode qp
  489. * @iwdev: iwarp device
  490. * @iwqp: qp ptr (user or kernel)
  491. * @info: initialize info to return
  492. * @init_attr: Initial QP create attributes
  493. */
  494. static int irdma_setup_kmode_qp(struct irdma_device *iwdev,
  495. struct irdma_qp *iwqp,
  496. struct irdma_qp_init_info *info,
  497. struct ib_qp_init_attr *init_attr)
  498. {
  499. struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem;
  500. u32 sqdepth, rqdepth;
  501. u8 sqshift, rqshift;
  502. u32 size;
  503. int status;
  504. struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  505. struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;
  506. irdma_get_wqe_shift(uk_attrs,
  507. uk_attrs->hw_rev >= IRDMA_GEN_2 ? ukinfo->max_sq_frag_cnt + 1 :
  508. ukinfo->max_sq_frag_cnt,
  509. ukinfo->max_inline_data, &sqshift);
  510. status = irdma_get_sqdepth(uk_attrs, ukinfo->sq_size, sqshift,
  511. &sqdepth);
  512. if (status)
  513. return status;
  514. if (uk_attrs->hw_rev == IRDMA_GEN_1)
  515. rqshift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1;
  516. else
  517. irdma_get_wqe_shift(uk_attrs, ukinfo->max_rq_frag_cnt, 0,
  518. &rqshift);
  519. status = irdma_get_rqdepth(uk_attrs, ukinfo->rq_size, rqshift,
  520. &rqdepth);
  521. if (status)
  522. return status;
  523. iwqp->kqp.sq_wrid_mem =
  524. kcalloc(sqdepth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL);
  525. if (!iwqp->kqp.sq_wrid_mem)
  526. return -ENOMEM;
  527. iwqp->kqp.rq_wrid_mem =
  528. kcalloc(rqdepth, sizeof(*iwqp->kqp.rq_wrid_mem), GFP_KERNEL);
  529. if (!iwqp->kqp.rq_wrid_mem) {
  530. kfree(iwqp->kqp.sq_wrid_mem);
  531. iwqp->kqp.sq_wrid_mem = NULL;
  532. return -ENOMEM;
  533. }
  534. ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem;
  535. ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem;
  536. size = (sqdepth + rqdepth) * IRDMA_QP_WQE_MIN_SIZE;
  537. size += (IRDMA_SHADOW_AREA_SIZE << 3);
  538. mem->size = ALIGN(size, 256);
  539. mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size,
  540. &mem->pa, GFP_KERNEL);
  541. if (!mem->va) {
  542. kfree(iwqp->kqp.sq_wrid_mem);
  543. iwqp->kqp.sq_wrid_mem = NULL;
  544. kfree(iwqp->kqp.rq_wrid_mem);
  545. iwqp->kqp.rq_wrid_mem = NULL;
  546. return -ENOMEM;
  547. }
  548. ukinfo->sq = mem->va;
  549. info->sq_pa = mem->pa;
  550. ukinfo->rq = &ukinfo->sq[sqdepth];
  551. info->rq_pa = info->sq_pa + (sqdepth * IRDMA_QP_WQE_MIN_SIZE);
  552. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  553. info->shadow_area_pa = info->rq_pa + (rqdepth * IRDMA_QP_WQE_MIN_SIZE);
  554. ukinfo->sq_size = sqdepth >> sqshift;
  555. ukinfo->rq_size = rqdepth >> rqshift;
  556. ukinfo->qp_id = iwqp->ibqp.qp_num;
  557. init_attr->cap.max_send_wr = (sqdepth - IRDMA_SQ_RSVD) >> sqshift;
  558. init_attr->cap.max_recv_wr = (rqdepth - IRDMA_RQ_RSVD) >> rqshift;
  559. return 0;
  560. }
  561. static int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp)
  562. {
  563. struct irdma_pci_f *rf = iwqp->iwdev->rf;
  564. struct irdma_cqp_request *cqp_request;
  565. struct cqp_cmds_info *cqp_info;
  566. struct irdma_create_qp_info *qp_info;
  567. int status;
  568. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  569. if (!cqp_request)
  570. return -ENOMEM;
  571. cqp_info = &cqp_request->info;
  572. qp_info = &cqp_request->info.in.u.qp_create.info;
  573. memset(qp_info, 0, sizeof(*qp_info));
  574. qp_info->mac_valid = true;
  575. qp_info->cq_num_valid = true;
  576. qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE;
  577. cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
  578. cqp_info->post_sq = 1;
  579. cqp_info->in.u.qp_create.qp = &iwqp->sc_qp;
  580. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  581. status = irdma_handle_cqp_op(rf, cqp_request);
  582. irdma_put_cqp_request(&rf->cqp, cqp_request);
  583. return status;
  584. }
  585. static void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
  586. struct irdma_qp_host_ctx_info *ctx_info)
  587. {
  588. struct irdma_device *iwdev = iwqp->iwdev;
  589. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  590. struct irdma_roce_offload_info *roce_info;
  591. struct irdma_udp_offload_info *udp_info;
  592. udp_info = &iwqp->udp_info;
  593. udp_info->snd_mss = ib_mtu_enum_to_int(ib_mtu_int_to_enum(iwdev->vsi.mtu));
  594. udp_info->cwnd = iwdev->roce_cwnd;
  595. udp_info->rexmit_thresh = 2;
  596. udp_info->rnr_nak_thresh = 2;
  597. udp_info->src_port = 0xc000;
  598. udp_info->dst_port = ROCE_V2_UDP_DPORT;
  599. roce_info = &iwqp->roce_info;
  600. ether_addr_copy(roce_info->mac_addr, iwdev->netdev->dev_addr);
  601. roce_info->rd_en = true;
  602. roce_info->wr_rdresp_en = true;
  603. roce_info->bind_en = true;
  604. roce_info->dcqcn_en = false;
  605. roce_info->rtomin = 5;
  606. roce_info->ack_credits = iwdev->roce_ackcreds;
  607. roce_info->ird_size = dev->hw_attrs.max_hw_ird;
  608. roce_info->ord_size = dev->hw_attrs.max_hw_ord;
  609. if (!iwqp->user_mode) {
  610. roce_info->priv_mode_en = true;
  611. roce_info->fast_reg_en = true;
  612. roce_info->udprivcq_en = true;
  613. }
  614. roce_info->roce_tver = 0;
  615. ctx_info->roce_info = &iwqp->roce_info;
  616. ctx_info->udp_info = &iwqp->udp_info;
  617. irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  618. }
  619. static void irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
  620. struct irdma_qp_host_ctx_info *ctx_info)
  621. {
  622. struct irdma_device *iwdev = iwqp->iwdev;
  623. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  624. struct irdma_iwarp_offload_info *iwarp_info;
  625. iwarp_info = &iwqp->iwarp_info;
  626. ether_addr_copy(iwarp_info->mac_addr, iwdev->netdev->dev_addr);
  627. iwarp_info->rd_en = true;
  628. iwarp_info->wr_rdresp_en = true;
  629. iwarp_info->bind_en = true;
  630. iwarp_info->ecn_en = true;
  631. iwarp_info->rtomin = 5;
  632. if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  633. iwarp_info->ib_rd_en = true;
  634. if (!iwqp->user_mode) {
  635. iwarp_info->priv_mode_en = true;
  636. iwarp_info->fast_reg_en = true;
  637. }
  638. iwarp_info->ddp_ver = 1;
  639. iwarp_info->rdmap_ver = 1;
  640. ctx_info->iwarp_info = &iwqp->iwarp_info;
  641. ctx_info->iwarp_info_valid = true;
  642. irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  643. ctx_info->iwarp_info_valid = false;
  644. }
  645. static int irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr,
  646. struct irdma_device *iwdev)
  647. {
  648. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  649. struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
  650. if (init_attr->create_flags)
  651. return -EOPNOTSUPP;
  652. if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline ||
  653. init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags ||
  654. init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags)
  655. return -EINVAL;
  656. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  657. if (init_attr->qp_type != IB_QPT_RC &&
  658. init_attr->qp_type != IB_QPT_UD &&
  659. init_attr->qp_type != IB_QPT_GSI)
  660. return -EOPNOTSUPP;
  661. } else {
  662. if (init_attr->qp_type != IB_QPT_RC)
  663. return -EOPNOTSUPP;
  664. }
  665. return 0;
  666. }
  667. static void irdma_flush_worker(struct work_struct *work)
  668. {
  669. struct delayed_work *dwork = to_delayed_work(work);
  670. struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush);
  671. irdma_generate_flush_completions(iwqp);
  672. }
  673. /**
  674. * irdma_create_qp - create qp
  675. * @ibqp: ptr of qp
  676. * @init_attr: attributes for qp
  677. * @udata: user data for create qp
  678. */
  679. static int irdma_create_qp(struct ib_qp *ibqp,
  680. struct ib_qp_init_attr *init_attr,
  681. struct ib_udata *udata)
  682. {
  683. #define IRDMA_CREATE_QP_MIN_REQ_LEN offsetofend(struct irdma_create_qp_req, user_compl_ctx)
  684. #define IRDMA_CREATE_QP_MIN_RESP_LEN offsetofend(struct irdma_create_qp_resp, rsvd)
  685. struct ib_pd *ibpd = ibqp->pd;
  686. struct irdma_pd *iwpd = to_iwpd(ibpd);
  687. struct irdma_device *iwdev = to_iwdev(ibpd->device);
  688. struct irdma_pci_f *rf = iwdev->rf;
  689. struct irdma_qp *iwqp = to_iwqp(ibqp);
  690. struct irdma_create_qp_req req = {};
  691. struct irdma_create_qp_resp uresp = {};
  692. u32 qp_num = 0;
  693. int err_code;
  694. int sq_size;
  695. int rq_size;
  696. struct irdma_sc_qp *qp;
  697. struct irdma_sc_dev *dev = &rf->sc_dev;
  698. struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
  699. struct irdma_qp_init_info init_info = {};
  700. struct irdma_qp_host_ctx_info *ctx_info;
  701. unsigned long flags;
  702. err_code = irdma_validate_qp_attrs(init_attr, iwdev);
  703. if (err_code)
  704. return err_code;
  705. if (udata && (udata->inlen < IRDMA_CREATE_QP_MIN_REQ_LEN ||
  706. udata->outlen < IRDMA_CREATE_QP_MIN_RESP_LEN))
  707. return -EINVAL;
  708. sq_size = init_attr->cap.max_send_wr;
  709. rq_size = init_attr->cap.max_recv_wr;
  710. init_info.vsi = &iwdev->vsi;
  711. init_info.qp_uk_init_info.uk_attrs = uk_attrs;
  712. init_info.qp_uk_init_info.sq_size = sq_size;
  713. init_info.qp_uk_init_info.rq_size = rq_size;
  714. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  715. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  716. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  717. qp = &iwqp->sc_qp;
  718. qp->qp_uk.back_qp = iwqp;
  719. qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;
  720. iwqp->iwdev = iwdev;
  721. iwqp->q2_ctx_mem.size = ALIGN(IRDMA_Q2_BUF_SIZE + IRDMA_QP_CTX_SIZE,
  722. 256);
  723. iwqp->q2_ctx_mem.va = dma_alloc_coherent(dev->hw->device,
  724. iwqp->q2_ctx_mem.size,
  725. &iwqp->q2_ctx_mem.pa,
  726. GFP_KERNEL);
  727. if (!iwqp->q2_ctx_mem.va)
  728. return -ENOMEM;
  729. init_info.q2 = iwqp->q2_ctx_mem.va;
  730. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  731. init_info.host_ctx = (__le64 *)(init_info.q2 + IRDMA_Q2_BUF_SIZE);
  732. init_info.host_ctx_pa = init_info.q2_pa + IRDMA_Q2_BUF_SIZE;
  733. if (init_attr->qp_type == IB_QPT_GSI)
  734. qp_num = 1;
  735. else
  736. err_code = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp,
  737. &qp_num, &rf->next_qp);
  738. if (err_code)
  739. goto error;
  740. iwqp->iwpd = iwpd;
  741. iwqp->ibqp.qp_num = qp_num;
  742. qp = &iwqp->sc_qp;
  743. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  744. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  745. iwqp->host_ctx.va = init_info.host_ctx;
  746. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  747. iwqp->host_ctx.size = IRDMA_QP_CTX_SIZE;
  748. init_info.pd = &iwpd->sc_pd;
  749. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  750. if (!rdma_protocol_roce(&iwdev->ibdev, 1))
  751. init_info.qp_uk_init_info.first_sq_wq = 1;
  752. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  753. init_waitqueue_head(&iwqp->waitq);
  754. init_waitqueue_head(&iwqp->mod_qp_waitq);
  755. if (udata) {
  756. err_code = ib_copy_from_udata(&req, udata,
  757. min(sizeof(req), udata->inlen));
  758. if (err_code) {
  759. ibdev_dbg(&iwdev->ibdev,
  760. "VERBS: ib_copy_from_data fail\n");
  761. goto error;
  762. }
  763. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  764. iwqp->user_mode = 1;
  765. if (req.user_wqe_bufs) {
  766. struct irdma_ucontext *ucontext =
  767. rdma_udata_to_drv_context(udata,
  768. struct irdma_ucontext,
  769. ibucontext);
  770. init_info.qp_uk_init_info.legacy_mode = ucontext->legacy_mode;
  771. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  772. iwqp->iwpbl = irdma_get_pbl((unsigned long)req.user_wqe_bufs,
  773. &ucontext->qp_reg_mem_list);
  774. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  775. if (!iwqp->iwpbl) {
  776. err_code = -ENODATA;
  777. ibdev_dbg(&iwdev->ibdev, "VERBS: no pbl info\n");
  778. goto error;
  779. }
  780. }
  781. init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver;
  782. irdma_setup_virt_qp(iwdev, iwqp, &init_info);
  783. } else {
  784. INIT_DELAYED_WORK(&iwqp->dwork_flush, irdma_flush_worker);
  785. init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER;
  786. err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr);
  787. }
  788. if (err_code) {
  789. ibdev_dbg(&iwdev->ibdev, "VERBS: setup qp failed\n");
  790. goto error;
  791. }
  792. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  793. if (init_attr->qp_type == IB_QPT_RC) {
  794. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_RC;
  795. init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
  796. IRDMA_WRITE_WITH_IMM |
  797. IRDMA_ROCE;
  798. } else {
  799. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_UD;
  800. init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
  801. IRDMA_ROCE;
  802. }
  803. } else {
  804. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_IWARP;
  805. init_info.qp_uk_init_info.qp_caps = IRDMA_WRITE_WITH_IMM;
  806. }
  807. if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1)
  808. init_info.qp_uk_init_info.qp_caps |= IRDMA_PUSH_MODE;
  809. err_code = irdma_sc_qp_init(qp, &init_info);
  810. if (err_code) {
  811. ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n");
  812. goto error;
  813. }
  814. ctx_info = &iwqp->ctx_info;
  815. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  816. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  817. if (rdma_protocol_roce(&iwdev->ibdev, 1))
  818. irdma_roce_fill_and_set_qpctx_info(iwqp, ctx_info);
  819. else
  820. irdma_iw_fill_and_set_qpctx_info(iwqp, ctx_info);
  821. err_code = irdma_cqp_create_qp_cmd(iwqp);
  822. if (err_code)
  823. goto error;
  824. refcount_set(&iwqp->refcnt, 1);
  825. spin_lock_init(&iwqp->lock);
  826. spin_lock_init(&iwqp->sc_qp.pfpdu.lock);
  827. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  828. rf->qp_table[qp_num] = iwqp;
  829. iwqp->max_send_wr = sq_size;
  830. iwqp->max_recv_wr = rq_size;
  831. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  832. if (dev->ws_add(&iwdev->vsi, 0)) {
  833. irdma_cqp_qp_destroy_cmd(&rf->sc_dev, &iwqp->sc_qp);
  834. err_code = -EINVAL;
  835. goto error;
  836. }
  837. irdma_qp_add_qos(&iwqp->sc_qp);
  838. }
  839. if (udata) {
  840. /* GEN_1 legacy support with libi40iw does not have expanded uresp struct */
  841. if (udata->outlen < sizeof(uresp)) {
  842. uresp.lsmm = 1;
  843. uresp.push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1;
  844. } else {
  845. if (rdma_protocol_iwarp(&iwdev->ibdev, 1))
  846. uresp.lsmm = 1;
  847. }
  848. uresp.actual_sq_size = sq_size;
  849. uresp.actual_rq_size = rq_size;
  850. uresp.qp_id = qp_num;
  851. uresp.qp_caps = qp->qp_uk.qp_caps;
  852. err_code = ib_copy_to_udata(udata, &uresp,
  853. min(sizeof(uresp), udata->outlen));
  854. if (err_code) {
  855. ibdev_dbg(&iwdev->ibdev, "VERBS: copy_to_udata failed\n");
  856. irdma_destroy_qp(&iwqp->ibqp, udata);
  857. return err_code;
  858. }
  859. }
  860. init_completion(&iwqp->free_qp);
  861. return 0;
  862. error:
  863. irdma_free_qp_rsrc(iwqp);
  864. return err_code;
  865. }
  866. static int irdma_get_ib_acc_flags(struct irdma_qp *iwqp)
  867. {
  868. int acc_flags = 0;
  869. if (rdma_protocol_roce(iwqp->ibqp.device, 1)) {
  870. if (iwqp->roce_info.wr_rdresp_en) {
  871. acc_flags |= IB_ACCESS_LOCAL_WRITE;
  872. acc_flags |= IB_ACCESS_REMOTE_WRITE;
  873. }
  874. if (iwqp->roce_info.rd_en)
  875. acc_flags |= IB_ACCESS_REMOTE_READ;
  876. if (iwqp->roce_info.bind_en)
  877. acc_flags |= IB_ACCESS_MW_BIND;
  878. } else {
  879. if (iwqp->iwarp_info.wr_rdresp_en) {
  880. acc_flags |= IB_ACCESS_LOCAL_WRITE;
  881. acc_flags |= IB_ACCESS_REMOTE_WRITE;
  882. }
  883. if (iwqp->iwarp_info.rd_en)
  884. acc_flags |= IB_ACCESS_REMOTE_READ;
  885. if (iwqp->iwarp_info.bind_en)
  886. acc_flags |= IB_ACCESS_MW_BIND;
  887. }
  888. return acc_flags;
  889. }
  890. /**
  891. * irdma_query_qp - query qp attributes
  892. * @ibqp: qp pointer
  893. * @attr: attributes pointer
  894. * @attr_mask: Not used
  895. * @init_attr: qp attributes to return
  896. */
  897. static int irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  898. int attr_mask, struct ib_qp_init_attr *init_attr)
  899. {
  900. struct irdma_qp *iwqp = to_iwqp(ibqp);
  901. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  902. memset(attr, 0, sizeof(*attr));
  903. memset(init_attr, 0, sizeof(*init_attr));
  904. attr->qp_state = iwqp->ibqp_state;
  905. attr->cur_qp_state = iwqp->ibqp_state;
  906. attr->cap.max_send_wr = iwqp->max_send_wr;
  907. attr->cap.max_recv_wr = iwqp->max_recv_wr;
  908. attr->cap.max_inline_data = qp->qp_uk.max_inline_data;
  909. attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt;
  910. attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt;
  911. attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp);
  912. attr->port_num = 1;
  913. if (rdma_protocol_roce(ibqp->device, 1)) {
  914. attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss);
  915. attr->qkey = iwqp->roce_info.qkey;
  916. attr->rq_psn = iwqp->udp_info.epsn;
  917. attr->sq_psn = iwqp->udp_info.psn_nxt;
  918. attr->dest_qp_num = iwqp->roce_info.dest_qp;
  919. attr->pkey_index = iwqp->roce_info.p_key;
  920. attr->retry_cnt = iwqp->udp_info.rexmit_thresh;
  921. attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh;
  922. attr->max_rd_atomic = iwqp->roce_info.ord_size;
  923. attr->max_dest_rd_atomic = iwqp->roce_info.ird_size;
  924. }
  925. init_attr->event_handler = iwqp->ibqp.event_handler;
  926. init_attr->qp_context = iwqp->ibqp.qp_context;
  927. init_attr->send_cq = iwqp->ibqp.send_cq;
  928. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  929. init_attr->cap = attr->cap;
  930. return 0;
  931. }
  932. /**
  933. * irdma_query_pkey - Query partition key
  934. * @ibdev: device pointer from stack
  935. * @port: port number
  936. * @index: index of pkey
  937. * @pkey: pointer to store the pkey
  938. */
  939. static int irdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
  940. u16 *pkey)
  941. {
  942. if (index >= IRDMA_PKEY_TBL_SZ)
  943. return -EINVAL;
  944. *pkey = IRDMA_DEFAULT_PKEY;
  945. return 0;
  946. }
  947. static int irdma_wait_for_suspend(struct irdma_qp *iwqp)
  948. {
  949. if (!wait_event_timeout(iwqp->iwdev->suspend_wq,
  950. !iwqp->suspend_pending,
  951. msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) {
  952. iwqp->suspend_pending = false;
  953. ibdev_warn(&iwqp->iwdev->ibdev,
  954. "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n",
  955. iwqp->ibqp.qp_num, iwqp->last_aeq);
  956. return -EBUSY;
  957. }
  958. return 0;
  959. }
  960. /**
  961. * irdma_modify_qp_roce - modify qp request
  962. * @ibqp: qp's pointer for modify
  963. * @attr: access attributes
  964. * @attr_mask: state mask
  965. * @udata: user data
  966. */
  967. int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  968. int attr_mask, struct ib_udata *udata)
  969. {
  970. #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
  971. #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
  972. struct irdma_pd *iwpd = to_iwpd(ibqp->pd);
  973. struct irdma_qp *iwqp = to_iwqp(ibqp);
  974. struct irdma_device *iwdev = iwqp->iwdev;
  975. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  976. struct irdma_qp_host_ctx_info *ctx_info;
  977. struct irdma_roce_offload_info *roce_info;
  978. struct irdma_udp_offload_info *udp_info;
  979. struct irdma_modify_qp_info info = {};
  980. struct irdma_modify_qp_resp uresp = {};
  981. struct irdma_modify_qp_req ureq = {};
  982. unsigned long flags;
  983. u8 issue_modify_qp = 0;
  984. int ret = 0;
  985. ctx_info = &iwqp->ctx_info;
  986. roce_info = &iwqp->roce_info;
  987. udp_info = &iwqp->udp_info;
  988. if (udata) {
  989. /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
  990. if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
  991. (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
  992. return -EINVAL;
  993. }
  994. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  995. return -EOPNOTSUPP;
  996. if (attr_mask & IB_QP_DEST_QPN)
  997. roce_info->dest_qp = attr->dest_qp_num;
  998. if (attr_mask & IB_QP_PKEY_INDEX) {
  999. ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index,
  1000. &roce_info->p_key);
  1001. if (ret)
  1002. return ret;
  1003. }
  1004. if (attr_mask & IB_QP_QKEY)
  1005. roce_info->qkey = attr->qkey;
  1006. if (attr_mask & IB_QP_PATH_MTU)
  1007. udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu);
  1008. if (attr_mask & IB_QP_SQ_PSN) {
  1009. udp_info->psn_nxt = attr->sq_psn;
  1010. udp_info->lsn = 0xffff;
  1011. udp_info->psn_una = attr->sq_psn;
  1012. udp_info->psn_max = attr->sq_psn;
  1013. }
  1014. if (attr_mask & IB_QP_RQ_PSN)
  1015. udp_info->epsn = attr->rq_psn;
  1016. if (attr_mask & IB_QP_RNR_RETRY)
  1017. udp_info->rnr_nak_thresh = attr->rnr_retry;
  1018. if (attr_mask & IB_QP_RETRY_CNT)
  1019. udp_info->rexmit_thresh = attr->retry_cnt;
  1020. ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id;
  1021. if (attr_mask & IB_QP_AV) {
  1022. struct irdma_av *av = &iwqp->roce_ah.av;
  1023. const struct ib_gid_attr *sgid_attr;
  1024. u16 vlan_id = VLAN_N_VID;
  1025. u32 local_ip[4];
  1026. memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah));
  1027. if (attr->ah_attr.ah_flags & IB_AH_GRH) {
  1028. udp_info->ttl = attr->ah_attr.grh.hop_limit;
  1029. udp_info->flow_label = attr->ah_attr.grh.flow_label;
  1030. udp_info->tos = attr->ah_attr.grh.traffic_class;
  1031. udp_info->src_port =
  1032. rdma_get_udp_sport(udp_info->flow_label,
  1033. ibqp->qp_num,
  1034. roce_info->dest_qp);
  1035. irdma_qp_rem_qos(&iwqp->sc_qp);
  1036. dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri);
  1037. ctx_info->user_pri = rt_tos2priority(udp_info->tos);
  1038. iwqp->sc_qp.user_pri = ctx_info->user_pri;
  1039. if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri))
  1040. return -ENOMEM;
  1041. irdma_qp_add_qos(&iwqp->sc_qp);
  1042. }
  1043. sgid_attr = attr->ah_attr.grh.sgid_attr;
  1044. ret = rdma_read_gid_l2_fields(sgid_attr, &vlan_id,
  1045. ctx_info->roce_info->mac_addr);
  1046. if (ret)
  1047. return ret;
  1048. if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
  1049. vlan_id = 0;
  1050. if (vlan_id < VLAN_N_VID) {
  1051. udp_info->insert_vlan_tag = true;
  1052. udp_info->vlan_tag = vlan_id |
  1053. ctx_info->user_pri << VLAN_PRIO_SHIFT;
  1054. } else {
  1055. udp_info->insert_vlan_tag = false;
  1056. }
  1057. av->attrs = attr->ah_attr;
  1058. rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);
  1059. rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid);
  1060. av->net_type = rdma_gid_attr_network_type(sgid_attr);
  1061. if (av->net_type == RDMA_NETWORK_IPV6) {
  1062. __be32 *daddr =
  1063. av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
  1064. __be32 *saddr =
  1065. av->sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
  1066. irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr);
  1067. irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr);
  1068. udp_info->ipv4 = false;
  1069. irdma_copy_ip_ntohl(local_ip, daddr);
  1070. udp_info->arp_idx = irdma_arp_table(iwdev->rf,
  1071. &local_ip[0],
  1072. false, NULL,
  1073. IRDMA_ARP_RESOLVE);
  1074. } else if (av->net_type == RDMA_NETWORK_IPV4) {
  1075. __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;
  1076. __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;
  1077. local_ip[0] = ntohl(daddr);
  1078. udp_info->ipv4 = true;
  1079. udp_info->dest_ip_addr[0] = 0;
  1080. udp_info->dest_ip_addr[1] = 0;
  1081. udp_info->dest_ip_addr[2] = 0;
  1082. udp_info->dest_ip_addr[3] = local_ip[0];
  1083. udp_info->local_ipaddr[0] = 0;
  1084. udp_info->local_ipaddr[1] = 0;
  1085. udp_info->local_ipaddr[2] = 0;
  1086. udp_info->local_ipaddr[3] = ntohl(saddr);
  1087. }
  1088. udp_info->arp_idx =
  1089. irdma_add_arp(iwdev->rf, local_ip, udp_info->ipv4,
  1090. attr->ah_attr.roce.dmac);
  1091. }
  1092. if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
  1093. if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) {
  1094. ibdev_err(&iwdev->ibdev,
  1095. "rd_atomic = %d, above max_hw_ord=%d\n",
  1096. attr->max_rd_atomic,
  1097. dev->hw_attrs.max_hw_ord);
  1098. return -EINVAL;
  1099. }
  1100. if (attr->max_rd_atomic)
  1101. roce_info->ord_size = attr->max_rd_atomic;
  1102. info.ord_valid = true;
  1103. }
  1104. if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
  1105. if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) {
  1106. ibdev_err(&iwdev->ibdev,
  1107. "rd_atomic = %d, above max_hw_ird=%d\n",
  1108. attr->max_rd_atomic,
  1109. dev->hw_attrs.max_hw_ird);
  1110. return -EINVAL;
  1111. }
  1112. if (attr->max_dest_rd_atomic)
  1113. roce_info->ird_size = attr->max_dest_rd_atomic;
  1114. }
  1115. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  1116. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  1117. roce_info->wr_rdresp_en = true;
  1118. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  1119. roce_info->wr_rdresp_en = true;
  1120. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  1121. roce_info->rd_en = true;
  1122. }
  1123. wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
  1124. ibdev_dbg(&iwdev->ibdev,
  1125. "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n",
  1126. __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
  1127. iwqp->ibqp_state, iwqp->iwarp_state, attr_mask);
  1128. spin_lock_irqsave(&iwqp->lock, flags);
  1129. if (attr_mask & IB_QP_STATE) {
  1130. if (!ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state,
  1131. iwqp->ibqp.qp_type, attr_mask)) {
  1132. ibdev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n",
  1133. iwqp->ibqp.qp_num, iwqp->ibqp_state,
  1134. attr->qp_state);
  1135. ret = -EINVAL;
  1136. goto exit;
  1137. }
  1138. info.curr_iwarp_state = iwqp->iwarp_state;
  1139. switch (attr->qp_state) {
  1140. case IB_QPS_INIT:
  1141. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1142. ret = -EINVAL;
  1143. goto exit;
  1144. }
  1145. if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
  1146. info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
  1147. issue_modify_qp = 1;
  1148. }
  1149. break;
  1150. case IB_QPS_RTR:
  1151. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1152. ret = -EINVAL;
  1153. goto exit;
  1154. }
  1155. info.arp_cache_idx_valid = true;
  1156. info.cq_num_valid = true;
  1157. info.next_iwarp_state = IRDMA_QP_STATE_RTR;
  1158. issue_modify_qp = 1;
  1159. break;
  1160. case IB_QPS_RTS:
  1161. if (iwqp->ibqp_state < IB_QPS_RTR ||
  1162. iwqp->ibqp_state == IB_QPS_ERR) {
  1163. ret = -EINVAL;
  1164. goto exit;
  1165. }
  1166. info.arp_cache_idx_valid = true;
  1167. info.cq_num_valid = true;
  1168. info.ord_valid = true;
  1169. info.next_iwarp_state = IRDMA_QP_STATE_RTS;
  1170. issue_modify_qp = 1;
  1171. if (iwdev->push_mode && udata &&
  1172. iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1173. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1174. spin_unlock_irqrestore(&iwqp->lock, flags);
  1175. irdma_alloc_push_page(iwqp);
  1176. spin_lock_irqsave(&iwqp->lock, flags);
  1177. }
  1178. break;
  1179. case IB_QPS_SQD:
  1180. if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD)
  1181. goto exit;
  1182. if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) {
  1183. ret = -EINVAL;
  1184. goto exit;
  1185. }
  1186. info.next_iwarp_state = IRDMA_QP_STATE_SQD;
  1187. issue_modify_qp = 1;
  1188. iwqp->suspend_pending = true;
  1189. break;
  1190. case IB_QPS_SQE:
  1191. case IB_QPS_ERR:
  1192. case IB_QPS_RESET:
  1193. if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
  1194. spin_unlock_irqrestore(&iwqp->lock, flags);
  1195. if (udata && udata->inlen) {
  1196. if (ib_copy_from_udata(&ureq, udata,
  1197. min(sizeof(ureq), udata->inlen)))
  1198. return -EINVAL;
  1199. irdma_flush_wqes(iwqp,
  1200. (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
  1201. (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
  1202. IRDMA_REFLUSH);
  1203. }
  1204. return 0;
  1205. }
  1206. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1207. issue_modify_qp = 1;
  1208. break;
  1209. default:
  1210. ret = -EINVAL;
  1211. goto exit;
  1212. }
  1213. iwqp->ibqp_state = attr->qp_state;
  1214. }
  1215. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  1216. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  1217. irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  1218. spin_unlock_irqrestore(&iwqp->lock, flags);
  1219. if (attr_mask & IB_QP_STATE) {
  1220. if (issue_modify_qp) {
  1221. ctx_info->rem_endpoint_idx = udp_info->arp_idx;
  1222. if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
  1223. return -EINVAL;
  1224. if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) {
  1225. ret = irdma_wait_for_suspend(iwqp);
  1226. if (ret)
  1227. return ret;
  1228. }
  1229. spin_lock_irqsave(&iwqp->lock, flags);
  1230. if (iwqp->iwarp_state == info.curr_iwarp_state) {
  1231. iwqp->iwarp_state = info.next_iwarp_state;
  1232. iwqp->ibqp_state = attr->qp_state;
  1233. }
  1234. if (iwqp->ibqp_state > IB_QPS_RTS &&
  1235. !iwqp->flush_issued) {
  1236. spin_unlock_irqrestore(&iwqp->lock, flags);
  1237. irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ |
  1238. IRDMA_FLUSH_RQ |
  1239. IRDMA_FLUSH_WAIT);
  1240. iwqp->flush_issued = 1;
  1241. } else {
  1242. spin_unlock_irqrestore(&iwqp->lock, flags);
  1243. }
  1244. } else {
  1245. iwqp->ibqp_state = attr->qp_state;
  1246. }
  1247. if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1248. struct irdma_ucontext *ucontext;
  1249. ucontext = rdma_udata_to_drv_context(udata,
  1250. struct irdma_ucontext, ibucontext);
  1251. if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1252. !iwqp->push_wqe_mmap_entry &&
  1253. !irdma_setup_push_mmap_entries(ucontext, iwqp,
  1254. &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
  1255. uresp.push_valid = 1;
  1256. uresp.push_offset = iwqp->sc_qp.push_offset;
  1257. }
  1258. ret = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
  1259. udata->outlen));
  1260. if (ret) {
  1261. irdma_remove_push_mmap_entries(iwqp);
  1262. ibdev_dbg(&iwdev->ibdev,
  1263. "VERBS: copy_to_udata failed\n");
  1264. return ret;
  1265. }
  1266. }
  1267. }
  1268. return 0;
  1269. exit:
  1270. spin_unlock_irqrestore(&iwqp->lock, flags);
  1271. return ret;
  1272. }
  1273. /**
  1274. * irdma_modify_qp - modify qp request
  1275. * @ibqp: qp's pointer for modify
  1276. * @attr: access attributes
  1277. * @attr_mask: state mask
  1278. * @udata: user data
  1279. */
  1280. int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
  1281. struct ib_udata *udata)
  1282. {
  1283. #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
  1284. #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
  1285. struct irdma_qp *iwqp = to_iwqp(ibqp);
  1286. struct irdma_device *iwdev = iwqp->iwdev;
  1287. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  1288. struct irdma_qp_host_ctx_info *ctx_info;
  1289. struct irdma_tcp_offload_info *tcp_info;
  1290. struct irdma_iwarp_offload_info *offload_info;
  1291. struct irdma_modify_qp_info info = {};
  1292. struct irdma_modify_qp_resp uresp = {};
  1293. struct irdma_modify_qp_req ureq = {};
  1294. u8 issue_modify_qp = 0;
  1295. u8 dont_wait = 0;
  1296. int err;
  1297. unsigned long flags;
  1298. if (udata) {
  1299. /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
  1300. if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
  1301. (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
  1302. return -EINVAL;
  1303. }
  1304. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  1305. return -EOPNOTSUPP;
  1306. ctx_info = &iwqp->ctx_info;
  1307. offload_info = &iwqp->iwarp_info;
  1308. tcp_info = &iwqp->tcp_info;
  1309. wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
  1310. ibdev_dbg(&iwdev->ibdev,
  1311. "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n",
  1312. __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
  1313. iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq,
  1314. iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask);
  1315. spin_lock_irqsave(&iwqp->lock, flags);
  1316. if (attr_mask & IB_QP_STATE) {
  1317. info.curr_iwarp_state = iwqp->iwarp_state;
  1318. switch (attr->qp_state) {
  1319. case IB_QPS_INIT:
  1320. case IB_QPS_RTR:
  1321. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1322. err = -EINVAL;
  1323. goto exit;
  1324. }
  1325. if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
  1326. info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
  1327. issue_modify_qp = 1;
  1328. }
  1329. if (iwdev->push_mode && udata &&
  1330. iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1331. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1332. spin_unlock_irqrestore(&iwqp->lock, flags);
  1333. irdma_alloc_push_page(iwqp);
  1334. spin_lock_irqsave(&iwqp->lock, flags);
  1335. }
  1336. break;
  1337. case IB_QPS_RTS:
  1338. if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS ||
  1339. !iwqp->cm_id) {
  1340. err = -EINVAL;
  1341. goto exit;
  1342. }
  1343. issue_modify_qp = 1;
  1344. iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED;
  1345. iwqp->hte_added = 1;
  1346. info.next_iwarp_state = IRDMA_QP_STATE_RTS;
  1347. info.tcp_ctx_valid = true;
  1348. info.ord_valid = true;
  1349. info.arp_cache_idx_valid = true;
  1350. info.cq_num_valid = true;
  1351. break;
  1352. case IB_QPS_SQD:
  1353. if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) {
  1354. err = 0;
  1355. goto exit;
  1356. }
  1357. if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING ||
  1358. iwqp->iwarp_state < IRDMA_QP_STATE_RTS) {
  1359. err = 0;
  1360. goto exit;
  1361. }
  1362. if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) {
  1363. err = -EINVAL;
  1364. goto exit;
  1365. }
  1366. info.next_iwarp_state = IRDMA_QP_STATE_CLOSING;
  1367. issue_modify_qp = 1;
  1368. break;
  1369. case IB_QPS_SQE:
  1370. if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) {
  1371. err = -EINVAL;
  1372. goto exit;
  1373. }
  1374. info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE;
  1375. issue_modify_qp = 1;
  1376. break;
  1377. case IB_QPS_ERR:
  1378. case IB_QPS_RESET:
  1379. if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
  1380. spin_unlock_irqrestore(&iwqp->lock, flags);
  1381. if (udata && udata->inlen) {
  1382. if (ib_copy_from_udata(&ureq, udata,
  1383. min(sizeof(ureq), udata->inlen)))
  1384. return -EINVAL;
  1385. irdma_flush_wqes(iwqp,
  1386. (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
  1387. (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
  1388. IRDMA_REFLUSH);
  1389. }
  1390. return 0;
  1391. }
  1392. if (iwqp->sc_qp.term_flags) {
  1393. spin_unlock_irqrestore(&iwqp->lock, flags);
  1394. irdma_terminate_del_timer(&iwqp->sc_qp);
  1395. spin_lock_irqsave(&iwqp->lock, flags);
  1396. }
  1397. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1398. if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED &&
  1399. iwdev->iw_status &&
  1400. iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT)
  1401. info.reset_tcp_conn = true;
  1402. else
  1403. dont_wait = 1;
  1404. issue_modify_qp = 1;
  1405. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1406. break;
  1407. default:
  1408. err = -EINVAL;
  1409. goto exit;
  1410. }
  1411. iwqp->ibqp_state = attr->qp_state;
  1412. }
  1413. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  1414. ctx_info->iwarp_info_valid = true;
  1415. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  1416. offload_info->wr_rdresp_en = true;
  1417. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  1418. offload_info->wr_rdresp_en = true;
  1419. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  1420. offload_info->rd_en = true;
  1421. }
  1422. if (ctx_info->iwarp_info_valid) {
  1423. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  1424. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  1425. irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  1426. }
  1427. spin_unlock_irqrestore(&iwqp->lock, flags);
  1428. if (attr_mask & IB_QP_STATE) {
  1429. if (issue_modify_qp) {
  1430. ctx_info->rem_endpoint_idx = tcp_info->arp_idx;
  1431. if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
  1432. return -EINVAL;
  1433. }
  1434. spin_lock_irqsave(&iwqp->lock, flags);
  1435. if (iwqp->iwarp_state == info.curr_iwarp_state) {
  1436. iwqp->iwarp_state = info.next_iwarp_state;
  1437. iwqp->ibqp_state = attr->qp_state;
  1438. }
  1439. spin_unlock_irqrestore(&iwqp->lock, flags);
  1440. }
  1441. if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) {
  1442. if (dont_wait) {
  1443. if (iwqp->hw_tcp_state) {
  1444. spin_lock_irqsave(&iwqp->lock, flags);
  1445. iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED;
  1446. iwqp->last_aeq = IRDMA_AE_RESET_SENT;
  1447. spin_unlock_irqrestore(&iwqp->lock, flags);
  1448. }
  1449. irdma_cm_disconn(iwqp);
  1450. } else {
  1451. int close_timer_started;
  1452. spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags);
  1453. if (iwqp->cm_node) {
  1454. refcount_inc(&iwqp->cm_node->refcnt);
  1455. spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
  1456. close_timer_started = atomic_inc_return(&iwqp->close_timer_started);
  1457. if (iwqp->cm_id && close_timer_started == 1)
  1458. irdma_schedule_cm_timer(iwqp->cm_node,
  1459. (struct irdma_puda_buf *)iwqp,
  1460. IRDMA_TIMER_TYPE_CLOSE, 1, 0);
  1461. irdma_rem_ref_cm_node(iwqp->cm_node);
  1462. } else {
  1463. spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
  1464. }
  1465. }
  1466. }
  1467. if (attr_mask & IB_QP_STATE && udata && udata->outlen &&
  1468. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1469. struct irdma_ucontext *ucontext;
  1470. ucontext = rdma_udata_to_drv_context(udata,
  1471. struct irdma_ucontext, ibucontext);
  1472. if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1473. !iwqp->push_wqe_mmap_entry &&
  1474. !irdma_setup_push_mmap_entries(ucontext, iwqp,
  1475. &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
  1476. uresp.push_valid = 1;
  1477. uresp.push_offset = iwqp->sc_qp.push_offset;
  1478. }
  1479. err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
  1480. udata->outlen));
  1481. if (err) {
  1482. irdma_remove_push_mmap_entries(iwqp);
  1483. ibdev_dbg(&iwdev->ibdev,
  1484. "VERBS: copy_to_udata failed\n");
  1485. return err;
  1486. }
  1487. }
  1488. return 0;
  1489. exit:
  1490. spin_unlock_irqrestore(&iwqp->lock, flags);
  1491. return err;
  1492. }
  1493. /**
  1494. * irdma_cq_free_rsrc - free up resources for cq
  1495. * @rf: RDMA PCI function
  1496. * @iwcq: cq ptr
  1497. */
  1498. static void irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq)
  1499. {
  1500. struct irdma_sc_cq *cq = &iwcq->sc_cq;
  1501. if (!iwcq->user_mode) {
  1502. dma_free_coherent(rf->sc_dev.hw->device, iwcq->kmem.size,
  1503. iwcq->kmem.va, iwcq->kmem.pa);
  1504. iwcq->kmem.va = NULL;
  1505. dma_free_coherent(rf->sc_dev.hw->device,
  1506. iwcq->kmem_shadow.size,
  1507. iwcq->kmem_shadow.va, iwcq->kmem_shadow.pa);
  1508. iwcq->kmem_shadow.va = NULL;
  1509. }
  1510. irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id);
  1511. }
  1512. /**
  1513. * irdma_free_cqbuf - worker to free a cq buffer
  1514. * @work: provides access to the cq buffer to free
  1515. */
  1516. static void irdma_free_cqbuf(struct work_struct *work)
  1517. {
  1518. struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work);
  1519. dma_free_coherent(cq_buf->hw->device, cq_buf->kmem_buf.size,
  1520. cq_buf->kmem_buf.va, cq_buf->kmem_buf.pa);
  1521. cq_buf->kmem_buf.va = NULL;
  1522. kfree(cq_buf);
  1523. }
  1524. /**
  1525. * irdma_process_resize_list - remove resized cq buffers from the resize_list
  1526. * @iwcq: cq which owns the resize_list
  1527. * @iwdev: irdma device
  1528. * @lcqe_buf: the buffer where the last cqe is received
  1529. */
  1530. static int irdma_process_resize_list(struct irdma_cq *iwcq,
  1531. struct irdma_device *iwdev,
  1532. struct irdma_cq_buf *lcqe_buf)
  1533. {
  1534. struct list_head *tmp_node, *list_node;
  1535. struct irdma_cq_buf *cq_buf;
  1536. int cnt = 0;
  1537. list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
  1538. cq_buf = list_entry(list_node, struct irdma_cq_buf, list);
  1539. if (cq_buf == lcqe_buf)
  1540. return cnt;
  1541. list_del(&cq_buf->list);
  1542. queue_work(iwdev->cleanup_wq, &cq_buf->work);
  1543. cnt++;
  1544. }
  1545. return cnt;
  1546. }
  1547. /**
  1548. * irdma_destroy_cq - destroy cq
  1549. * @ib_cq: cq pointer
  1550. * @udata: user data
  1551. */
  1552. static int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
  1553. {
  1554. struct irdma_device *iwdev = to_iwdev(ib_cq->device);
  1555. struct irdma_cq *iwcq = to_iwcq(ib_cq);
  1556. struct irdma_sc_cq *cq = &iwcq->sc_cq;
  1557. struct irdma_sc_dev *dev = cq->dev;
  1558. struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id];
  1559. struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq);
  1560. unsigned long flags;
  1561. spin_lock_irqsave(&iwcq->lock, flags);
  1562. if (!list_empty(&iwcq->cmpl_generated))
  1563. irdma_remove_cmpls_list(iwcq);
  1564. if (!list_empty(&iwcq->resize_list))
  1565. irdma_process_resize_list(iwcq, iwdev, NULL);
  1566. spin_unlock_irqrestore(&iwcq->lock, flags);
  1567. irdma_cq_wq_destroy(iwdev->rf, cq);
  1568. spin_lock_irqsave(&iwceq->ce_lock, flags);
  1569. irdma_sc_cleanup_ceqes(cq, ceq);
  1570. spin_unlock_irqrestore(&iwceq->ce_lock, flags);
  1571. irdma_cq_free_rsrc(iwdev->rf, iwcq);
  1572. return 0;
  1573. }
  1574. /**
  1575. * irdma_resize_cq - resize cq
  1576. * @ibcq: cq to be resized
  1577. * @entries: desired cq size
  1578. * @udata: user data
  1579. */
  1580. static int irdma_resize_cq(struct ib_cq *ibcq, int entries,
  1581. struct ib_udata *udata)
  1582. {
  1583. #define IRDMA_RESIZE_CQ_MIN_REQ_LEN offsetofend(struct irdma_resize_cq_req, user_cq_buffer)
  1584. struct irdma_cq *iwcq = to_iwcq(ibcq);
  1585. struct irdma_sc_dev *dev = iwcq->sc_cq.dev;
  1586. struct irdma_cqp_request *cqp_request;
  1587. struct cqp_cmds_info *cqp_info;
  1588. struct irdma_modify_cq_info *m_info;
  1589. struct irdma_modify_cq_info info = {};
  1590. struct irdma_dma_mem kmem_buf;
  1591. struct irdma_cq_mr *cqmr_buf;
  1592. struct irdma_pbl *iwpbl_buf;
  1593. struct irdma_device *iwdev;
  1594. struct irdma_pci_f *rf;
  1595. struct irdma_cq_buf *cq_buf = NULL;
  1596. unsigned long flags;
  1597. int ret;
  1598. iwdev = to_iwdev(ibcq->device);
  1599. rf = iwdev->rf;
  1600. if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
  1601. IRDMA_FEATURE_CQ_RESIZE))
  1602. return -EOPNOTSUPP;
  1603. if (udata && udata->inlen < IRDMA_RESIZE_CQ_MIN_REQ_LEN)
  1604. return -EINVAL;
  1605. if (entries > rf->max_cqe)
  1606. return -EINVAL;
  1607. if (!iwcq->user_mode) {
  1608. entries++;
  1609. if (rf->sc_dev.hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1610. entries *= 2;
  1611. }
  1612. info.cq_size = max(entries, 4);
  1613. if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1)
  1614. return 0;
  1615. if (udata) {
  1616. struct irdma_resize_cq_req req = {};
  1617. struct irdma_ucontext *ucontext =
  1618. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  1619. ibucontext);
  1620. /* CQ resize not supported with legacy GEN_1 libi40iw */
  1621. if (ucontext->legacy_mode)
  1622. return -EOPNOTSUPP;
  1623. if (ib_copy_from_udata(&req, udata,
  1624. min(sizeof(req), udata->inlen)))
  1625. return -EINVAL;
  1626. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1627. iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer,
  1628. &ucontext->cq_reg_mem_list);
  1629. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1630. if (!iwpbl_buf)
  1631. return -ENOMEM;
  1632. cqmr_buf = &iwpbl_buf->cq_mr;
  1633. if (iwpbl_buf->pbl_allocated) {
  1634. info.virtual_map = true;
  1635. info.pbl_chunk_size = 1;
  1636. info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx;
  1637. } else {
  1638. info.cq_pa = cqmr_buf->cq_pbl.addr;
  1639. }
  1640. } else {
  1641. /* Kmode CQ resize */
  1642. int rsize;
  1643. rsize = info.cq_size * sizeof(struct irdma_cqe);
  1644. kmem_buf.size = ALIGN(round_up(rsize, 256), 256);
  1645. kmem_buf.va = dma_alloc_coherent(dev->hw->device,
  1646. kmem_buf.size, &kmem_buf.pa,
  1647. GFP_KERNEL);
  1648. if (!kmem_buf.va)
  1649. return -ENOMEM;
  1650. info.cq_base = kmem_buf.va;
  1651. info.cq_pa = kmem_buf.pa;
  1652. cq_buf = kzalloc(sizeof(*cq_buf), GFP_KERNEL);
  1653. if (!cq_buf) {
  1654. ret = -ENOMEM;
  1655. goto error;
  1656. }
  1657. }
  1658. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1659. if (!cqp_request) {
  1660. ret = -ENOMEM;
  1661. goto error;
  1662. }
  1663. info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold;
  1664. info.cq_resize = true;
  1665. cqp_info = &cqp_request->info;
  1666. m_info = &cqp_info->in.u.cq_modify.info;
  1667. memcpy(m_info, &info, sizeof(*m_info));
  1668. cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY;
  1669. cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;
  1670. cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;
  1671. cqp_info->post_sq = 1;
  1672. ret = irdma_handle_cqp_op(rf, cqp_request);
  1673. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1674. if (ret)
  1675. goto error;
  1676. spin_lock_irqsave(&iwcq->lock, flags);
  1677. if (cq_buf) {
  1678. cq_buf->kmem_buf = iwcq->kmem;
  1679. cq_buf->hw = dev->hw;
  1680. memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk));
  1681. INIT_WORK(&cq_buf->work, irdma_free_cqbuf);
  1682. list_add_tail(&cq_buf->list, &iwcq->resize_list);
  1683. iwcq->kmem = kmem_buf;
  1684. }
  1685. irdma_sc_cq_resize(&iwcq->sc_cq, &info);
  1686. ibcq->cqe = info.cq_size - 1;
  1687. spin_unlock_irqrestore(&iwcq->lock, flags);
  1688. return 0;
  1689. error:
  1690. if (!udata) {
  1691. dma_free_coherent(dev->hw->device, kmem_buf.size, kmem_buf.va,
  1692. kmem_buf.pa);
  1693. kmem_buf.va = NULL;
  1694. }
  1695. kfree(cq_buf);
  1696. return ret;
  1697. }
  1698. static inline int cq_validate_flags(u32 flags, u8 hw_rev)
  1699. {
  1700. /* GEN1 does not support CQ create flags */
  1701. if (hw_rev == IRDMA_GEN_1)
  1702. return flags ? -EOPNOTSUPP : 0;
  1703. return flags & ~IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION ? -EOPNOTSUPP : 0;
  1704. }
  1705. /**
  1706. * irdma_create_cq - create cq
  1707. * @ibcq: CQ allocated
  1708. * @attr: attributes for cq
  1709. * @udata: user data
  1710. */
  1711. static int irdma_create_cq(struct ib_cq *ibcq,
  1712. const struct ib_cq_init_attr *attr,
  1713. struct ib_udata *udata)
  1714. {
  1715. #define IRDMA_CREATE_CQ_MIN_REQ_LEN offsetofend(struct irdma_create_cq_req, user_cq_buf)
  1716. #define IRDMA_CREATE_CQ_MIN_RESP_LEN offsetofend(struct irdma_create_cq_resp, cq_size)
  1717. struct ib_device *ibdev = ibcq->device;
  1718. struct irdma_device *iwdev = to_iwdev(ibdev);
  1719. struct irdma_pci_f *rf = iwdev->rf;
  1720. struct irdma_cq *iwcq = to_iwcq(ibcq);
  1721. u32 cq_num = 0;
  1722. struct irdma_sc_cq *cq;
  1723. struct irdma_sc_dev *dev = &rf->sc_dev;
  1724. struct irdma_cq_init_info info = {};
  1725. struct irdma_cqp_request *cqp_request;
  1726. struct cqp_cmds_info *cqp_info;
  1727. struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  1728. unsigned long flags;
  1729. int err_code;
  1730. int entries = attr->cqe;
  1731. err_code = cq_validate_flags(attr->flags, dev->hw_attrs.uk_attrs.hw_rev);
  1732. if (err_code)
  1733. return err_code;
  1734. if (udata && (udata->inlen < IRDMA_CREATE_CQ_MIN_REQ_LEN ||
  1735. udata->outlen < IRDMA_CREATE_CQ_MIN_RESP_LEN))
  1736. return -EINVAL;
  1737. err_code = irdma_alloc_rsrc(rf, rf->allocated_cqs, rf->max_cq, &cq_num,
  1738. &rf->next_cq);
  1739. if (err_code)
  1740. return err_code;
  1741. cq = &iwcq->sc_cq;
  1742. cq->back_cq = iwcq;
  1743. spin_lock_init(&iwcq->lock);
  1744. INIT_LIST_HEAD(&iwcq->resize_list);
  1745. INIT_LIST_HEAD(&iwcq->cmpl_generated);
  1746. info.dev = dev;
  1747. ukinfo->cq_size = max(entries, 4);
  1748. ukinfo->cq_id = cq_num;
  1749. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1750. if (attr->comp_vector < rf->ceqs_count)
  1751. info.ceq_id = attr->comp_vector;
  1752. info.ceq_id_valid = true;
  1753. info.ceqe_mask = 1;
  1754. info.type = IRDMA_CQ_TYPE_IWARP;
  1755. info.vsi = &iwdev->vsi;
  1756. if (udata) {
  1757. struct irdma_ucontext *ucontext;
  1758. struct irdma_create_cq_req req = {};
  1759. struct irdma_cq_mr *cqmr;
  1760. struct irdma_pbl *iwpbl;
  1761. struct irdma_pbl *iwpbl_shadow;
  1762. struct irdma_cq_mr *cqmr_shadow;
  1763. iwcq->user_mode = true;
  1764. ucontext =
  1765. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  1766. ibucontext);
  1767. if (ib_copy_from_udata(&req, udata,
  1768. min(sizeof(req), udata->inlen))) {
  1769. err_code = -EFAULT;
  1770. goto cq_free_rsrc;
  1771. }
  1772. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1773. iwpbl = irdma_get_pbl((unsigned long)req.user_cq_buf,
  1774. &ucontext->cq_reg_mem_list);
  1775. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1776. if (!iwpbl) {
  1777. err_code = -EPROTO;
  1778. goto cq_free_rsrc;
  1779. }
  1780. iwcq->iwpbl = iwpbl;
  1781. iwcq->cq_mem_size = 0;
  1782. cqmr = &iwpbl->cq_mr;
  1783. if (rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
  1784. IRDMA_FEATURE_CQ_RESIZE && !ucontext->legacy_mode) {
  1785. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1786. iwpbl_shadow = irdma_get_pbl(
  1787. (unsigned long)req.user_shadow_area,
  1788. &ucontext->cq_reg_mem_list);
  1789. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1790. if (!iwpbl_shadow) {
  1791. err_code = -EPROTO;
  1792. goto cq_free_rsrc;
  1793. }
  1794. iwcq->iwpbl_shadow = iwpbl_shadow;
  1795. cqmr_shadow = &iwpbl_shadow->cq_mr;
  1796. info.shadow_area_pa = cqmr_shadow->cq_pbl.addr;
  1797. cqmr->split = true;
  1798. } else {
  1799. info.shadow_area_pa = cqmr->shadow;
  1800. }
  1801. if (iwpbl->pbl_allocated) {
  1802. info.virtual_map = true;
  1803. info.pbl_chunk_size = 1;
  1804. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1805. } else {
  1806. info.cq_base_pa = cqmr->cq_pbl.addr;
  1807. }
  1808. } else {
  1809. /* Kmode allocations */
  1810. int rsize;
  1811. if (entries < 1 || entries > rf->max_cqe) {
  1812. err_code = -EINVAL;
  1813. goto cq_free_rsrc;
  1814. }
  1815. entries++;
  1816. if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1817. entries *= 2;
  1818. ukinfo->cq_size = entries;
  1819. rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_cqe);
  1820. iwcq->kmem.size = ALIGN(round_up(rsize, 256), 256);
  1821. iwcq->kmem.va = dma_alloc_coherent(dev->hw->device,
  1822. iwcq->kmem.size,
  1823. &iwcq->kmem.pa, GFP_KERNEL);
  1824. if (!iwcq->kmem.va) {
  1825. err_code = -ENOMEM;
  1826. goto cq_free_rsrc;
  1827. }
  1828. iwcq->kmem_shadow.size = ALIGN(IRDMA_SHADOW_AREA_SIZE << 3,
  1829. 64);
  1830. iwcq->kmem_shadow.va = dma_alloc_coherent(dev->hw->device,
  1831. iwcq->kmem_shadow.size,
  1832. &iwcq->kmem_shadow.pa,
  1833. GFP_KERNEL);
  1834. if (!iwcq->kmem_shadow.va) {
  1835. err_code = -ENOMEM;
  1836. goto cq_free_rsrc;
  1837. }
  1838. info.shadow_area_pa = iwcq->kmem_shadow.pa;
  1839. ukinfo->shadow_area = iwcq->kmem_shadow.va;
  1840. ukinfo->cq_base = iwcq->kmem.va;
  1841. info.cq_base_pa = iwcq->kmem.pa;
  1842. }
  1843. if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1844. info.shadow_read_threshold = min(info.cq_uk_init_info.cq_size / 2,
  1845. (u32)IRDMA_MAX_CQ_READ_THRESH);
  1846. if (irdma_sc_cq_init(cq, &info)) {
  1847. ibdev_dbg(&iwdev->ibdev, "VERBS: init cq fail\n");
  1848. err_code = -EPROTO;
  1849. goto cq_free_rsrc;
  1850. }
  1851. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1852. if (!cqp_request) {
  1853. err_code = -ENOMEM;
  1854. goto cq_free_rsrc;
  1855. }
  1856. cqp_info = &cqp_request->info;
  1857. cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
  1858. cqp_info->post_sq = 1;
  1859. cqp_info->in.u.cq_create.cq = cq;
  1860. cqp_info->in.u.cq_create.check_overflow = true;
  1861. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1862. err_code = irdma_handle_cqp_op(rf, cqp_request);
  1863. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1864. if (err_code)
  1865. goto cq_free_rsrc;
  1866. if (udata) {
  1867. struct irdma_create_cq_resp resp = {};
  1868. resp.cq_id = info.cq_uk_init_info.cq_id;
  1869. resp.cq_size = info.cq_uk_init_info.cq_size;
  1870. if (ib_copy_to_udata(udata, &resp,
  1871. min(sizeof(resp), udata->outlen))) {
  1872. ibdev_dbg(&iwdev->ibdev,
  1873. "VERBS: copy to user data\n");
  1874. err_code = -EPROTO;
  1875. goto cq_destroy;
  1876. }
  1877. }
  1878. return 0;
  1879. cq_destroy:
  1880. irdma_cq_wq_destroy(rf, cq);
  1881. cq_free_rsrc:
  1882. irdma_cq_free_rsrc(rf, iwcq);
  1883. return err_code;
  1884. }
  1885. /**
  1886. * irdma_get_mr_access - get hw MR access permissions from IB access flags
  1887. * @access: IB access flags
  1888. */
  1889. static inline u16 irdma_get_mr_access(int access)
  1890. {
  1891. u16 hw_access = 0;
  1892. hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ?
  1893. IRDMA_ACCESS_FLAGS_LOCALWRITE : 0;
  1894. hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ?
  1895. IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0;
  1896. hw_access |= (access & IB_ACCESS_REMOTE_READ) ?
  1897. IRDMA_ACCESS_FLAGS_REMOTEREAD : 0;
  1898. hw_access |= (access & IB_ACCESS_MW_BIND) ?
  1899. IRDMA_ACCESS_FLAGS_BIND_WINDOW : 0;
  1900. hw_access |= (access & IB_ZERO_BASED) ?
  1901. IRDMA_ACCESS_FLAGS_ZERO_BASED : 0;
  1902. hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD;
  1903. return hw_access;
  1904. }
  1905. /**
  1906. * irdma_free_stag - free stag resource
  1907. * @iwdev: irdma device
  1908. * @stag: stag to free
  1909. */
  1910. static void irdma_free_stag(struct irdma_device *iwdev, u32 stag)
  1911. {
  1912. u32 stag_idx;
  1913. stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S;
  1914. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx);
  1915. }
  1916. /**
  1917. * irdma_create_stag - create random stag
  1918. * @iwdev: irdma device
  1919. */
  1920. static u32 irdma_create_stag(struct irdma_device *iwdev)
  1921. {
  1922. u32 stag = 0;
  1923. u32 stag_index = 0;
  1924. u32 next_stag_index;
  1925. u32 driver_key;
  1926. u32 random;
  1927. u8 consumer_key;
  1928. int ret;
  1929. get_random_bytes(&random, sizeof(random));
  1930. consumer_key = (u8)random;
  1931. driver_key = random & ~iwdev->rf->mr_stagmask;
  1932. next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8;
  1933. next_stag_index %= iwdev->rf->max_mr;
  1934. ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs,
  1935. iwdev->rf->max_mr, &stag_index,
  1936. &next_stag_index);
  1937. if (ret)
  1938. return stag;
  1939. stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S;
  1940. stag |= driver_key;
  1941. stag += (u32)consumer_key;
  1942. return stag;
  1943. }
  1944. /**
  1945. * irdma_next_pbl_addr - Get next pbl address
  1946. * @pbl: pointer to a pble
  1947. * @pinfo: info pointer
  1948. * @idx: index
  1949. */
  1950. static inline u64 *irdma_next_pbl_addr(u64 *pbl, struct irdma_pble_info **pinfo,
  1951. u32 *idx)
  1952. {
  1953. *idx += 1;
  1954. if (!(*pinfo) || *idx != (*pinfo)->cnt)
  1955. return ++pbl;
  1956. *idx = 0;
  1957. (*pinfo)++;
  1958. return (*pinfo)->addr;
  1959. }
  1960. /**
  1961. * irdma_copy_user_pgaddrs - copy user page address to pble's os locally
  1962. * @iwmr: iwmr for IB's user page addresses
  1963. * @pbl: ple pointer to save 1 level or 0 level pble
  1964. * @level: indicated level 0, 1 or 2
  1965. */
  1966. static void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl,
  1967. enum irdma_pble_level level)
  1968. {
  1969. struct ib_umem *region = iwmr->region;
  1970. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  1971. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  1972. struct irdma_pble_info *pinfo;
  1973. struct ib_block_iter biter;
  1974. u32 idx = 0;
  1975. u32 pbl_cnt = 0;
  1976. pinfo = (level == PBLE_LEVEL_1) ? NULL : palloc->level2.leaf;
  1977. if (iwmr->type == IRDMA_MEMREG_TYPE_QP)
  1978. iwpbl->qp_mr.sq_page = sg_page(region->sgt_append.sgt.sgl);
  1979. rdma_umem_for_each_dma_block(region, &biter, iwmr->page_size) {
  1980. *pbl = rdma_block_iter_dma_address(&biter);
  1981. if (++pbl_cnt == palloc->total_cnt)
  1982. break;
  1983. pbl = irdma_next_pbl_addr(pbl, &pinfo, &idx);
  1984. }
  1985. }
  1986. /**
  1987. * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous
  1988. * @arr: lvl1 pbl array
  1989. * @npages: page count
  1990. * @pg_size: page size
  1991. *
  1992. */
  1993. static bool irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
  1994. {
  1995. u32 pg_idx;
  1996. for (pg_idx = 0; pg_idx < npages; pg_idx++) {
  1997. if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
  1998. return false;
  1999. }
  2000. return true;
  2001. }
  2002. /**
  2003. * irdma_check_mr_contiguous - check if MR is physically contiguous
  2004. * @palloc: pbl allocation struct
  2005. * @pg_size: page size
  2006. */
  2007. static bool irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc,
  2008. u32 pg_size)
  2009. {
  2010. struct irdma_pble_level2 *lvl2 = &palloc->level2;
  2011. struct irdma_pble_info *leaf = lvl2->leaf;
  2012. u64 *arr = NULL;
  2013. u64 *start_addr = NULL;
  2014. int i;
  2015. bool ret;
  2016. if (palloc->level == PBLE_LEVEL_1) {
  2017. arr = palloc->level1.addr;
  2018. ret = irdma_check_mem_contiguous(arr, palloc->total_cnt,
  2019. pg_size);
  2020. return ret;
  2021. }
  2022. start_addr = leaf->addr;
  2023. for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
  2024. arr = leaf->addr;
  2025. if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
  2026. return false;
  2027. ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size);
  2028. if (!ret)
  2029. return false;
  2030. }
  2031. return true;
  2032. }
  2033. /**
  2034. * irdma_setup_pbles - copy user pg address to pble's
  2035. * @rf: RDMA PCI function
  2036. * @iwmr: mr pointer for this memory registration
  2037. * @use_pbles: flag if to use pble's
  2038. * @lvl_1_only: request only level 1 pble if true
  2039. */
  2040. static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr,
  2041. bool use_pbles, bool lvl_1_only)
  2042. {
  2043. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2044. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2045. struct irdma_pble_info *pinfo;
  2046. u64 *pbl;
  2047. int status;
  2048. enum irdma_pble_level level = PBLE_LEVEL_1;
  2049. if (use_pbles) {
  2050. status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,
  2051. lvl_1_only);
  2052. if (status)
  2053. return status;
  2054. iwpbl->pbl_allocated = true;
  2055. level = palloc->level;
  2056. pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 :
  2057. palloc->level2.leaf;
  2058. pbl = pinfo->addr;
  2059. } else {
  2060. pbl = iwmr->pgaddrmem;
  2061. }
  2062. irdma_copy_user_pgaddrs(iwmr, pbl, level);
  2063. if (use_pbles)
  2064. iwmr->pgaddrmem[0] = *pbl;
  2065. return 0;
  2066. }
  2067. /**
  2068. * irdma_handle_q_mem - handle memory for qp and cq
  2069. * @iwdev: irdma device
  2070. * @req: information for q memory management
  2071. * @iwpbl: pble struct
  2072. * @use_pbles: flag to use pble
  2073. */
  2074. static int irdma_handle_q_mem(struct irdma_device *iwdev,
  2075. struct irdma_mem_reg_req *req,
  2076. struct irdma_pbl *iwpbl, bool use_pbles)
  2077. {
  2078. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2079. struct irdma_mr *iwmr = iwpbl->iwmr;
  2080. struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
  2081. struct irdma_cq_mr *cqmr = &iwpbl->cq_mr;
  2082. struct irdma_hmc_pble *hmc_p;
  2083. u64 *arr = iwmr->pgaddrmem;
  2084. u32 pg_size, total;
  2085. int err = 0;
  2086. bool ret = true;
  2087. pg_size = iwmr->page_size;
  2088. err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles, true);
  2089. if (err)
  2090. return err;
  2091. if (use_pbles)
  2092. arr = palloc->level1.addr;
  2093. switch (iwmr->type) {
  2094. case IRDMA_MEMREG_TYPE_QP:
  2095. total = req->sq_pages + req->rq_pages;
  2096. hmc_p = &qpmr->sq_pbl;
  2097. qpmr->shadow = (dma_addr_t)arr[total];
  2098. if (use_pbles) {
  2099. ret = irdma_check_mem_contiguous(arr, req->sq_pages,
  2100. pg_size);
  2101. if (ret)
  2102. ret = irdma_check_mem_contiguous(&arr[req->sq_pages],
  2103. req->rq_pages,
  2104. pg_size);
  2105. }
  2106. if (!ret) {
  2107. hmc_p->idx = palloc->level1.idx;
  2108. hmc_p = &qpmr->rq_pbl;
  2109. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  2110. } else {
  2111. hmc_p->addr = arr[0];
  2112. hmc_p = &qpmr->rq_pbl;
  2113. hmc_p->addr = arr[req->sq_pages];
  2114. }
  2115. break;
  2116. case IRDMA_MEMREG_TYPE_CQ:
  2117. hmc_p = &cqmr->cq_pbl;
  2118. if (!cqmr->split)
  2119. cqmr->shadow = (dma_addr_t)arr[req->cq_pages];
  2120. if (use_pbles)
  2121. ret = irdma_check_mem_contiguous(arr, req->cq_pages,
  2122. pg_size);
  2123. if (!ret)
  2124. hmc_p->idx = palloc->level1.idx;
  2125. else
  2126. hmc_p->addr = arr[0];
  2127. break;
  2128. default:
  2129. ibdev_dbg(&iwdev->ibdev, "VERBS: MR type error\n");
  2130. err = -EINVAL;
  2131. }
  2132. if (use_pbles && ret) {
  2133. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2134. iwpbl->pbl_allocated = false;
  2135. }
  2136. return err;
  2137. }
  2138. /**
  2139. * irdma_hw_alloc_mw - create the hw memory window
  2140. * @iwdev: irdma device
  2141. * @iwmr: pointer to memory window info
  2142. */
  2143. static int irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr)
  2144. {
  2145. struct irdma_mw_alloc_info *info;
  2146. struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  2147. struct irdma_cqp_request *cqp_request;
  2148. struct cqp_cmds_info *cqp_info;
  2149. int status;
  2150. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2151. if (!cqp_request)
  2152. return -ENOMEM;
  2153. cqp_info = &cqp_request->info;
  2154. info = &cqp_info->in.u.mw_alloc.info;
  2155. memset(info, 0, sizeof(*info));
  2156. if (iwmr->ibmw.type == IB_MW_TYPE_1)
  2157. info->mw_wide = true;
  2158. info->page_size = PAGE_SIZE;
  2159. info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2160. info->pd_id = iwpd->sc_pd.pd_id;
  2161. info->remote_access = true;
  2162. cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC;
  2163. cqp_info->post_sq = 1;
  2164. cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev;
  2165. cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request;
  2166. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2167. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2168. return status;
  2169. }
  2170. /**
  2171. * irdma_alloc_mw - Allocate memory window
  2172. * @ibmw: Memory Window
  2173. * @udata: user data pointer
  2174. */
  2175. static int irdma_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
  2176. {
  2177. struct irdma_device *iwdev = to_iwdev(ibmw->device);
  2178. struct irdma_mr *iwmr = to_iwmw(ibmw);
  2179. int err_code;
  2180. u32 stag;
  2181. stag = irdma_create_stag(iwdev);
  2182. if (!stag)
  2183. return -ENOMEM;
  2184. iwmr->stag = stag;
  2185. ibmw->rkey = stag;
  2186. err_code = irdma_hw_alloc_mw(iwdev, iwmr);
  2187. if (err_code) {
  2188. irdma_free_stag(iwdev, stag);
  2189. return err_code;
  2190. }
  2191. return 0;
  2192. }
  2193. /**
  2194. * irdma_dealloc_mw - Dealloc memory window
  2195. * @ibmw: memory window structure.
  2196. */
  2197. static int irdma_dealloc_mw(struct ib_mw *ibmw)
  2198. {
  2199. struct ib_pd *ibpd = ibmw->pd;
  2200. struct irdma_pd *iwpd = to_iwpd(ibpd);
  2201. struct irdma_mr *iwmr = to_iwmr((struct ib_mr *)ibmw);
  2202. struct irdma_device *iwdev = to_iwdev(ibmw->device);
  2203. struct irdma_cqp_request *cqp_request;
  2204. struct cqp_cmds_info *cqp_info;
  2205. struct irdma_dealloc_stag_info *info;
  2206. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2207. if (!cqp_request)
  2208. return -ENOMEM;
  2209. cqp_info = &cqp_request->info;
  2210. info = &cqp_info->in.u.dealloc_stag.info;
  2211. memset(info, 0, sizeof(*info));
  2212. info->pd_id = iwpd->sc_pd.pd_id;
  2213. info->stag_idx = ibmw->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
  2214. info->mr = false;
  2215. cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
  2216. cqp_info->post_sq = 1;
  2217. cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
  2218. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  2219. irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2220. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2221. irdma_free_stag(iwdev, iwmr->stag);
  2222. return 0;
  2223. }
  2224. /**
  2225. * irdma_hw_alloc_stag - cqp command to allocate stag
  2226. * @iwdev: irdma device
  2227. * @iwmr: irdma mr pointer
  2228. */
  2229. static int irdma_hw_alloc_stag(struct irdma_device *iwdev,
  2230. struct irdma_mr *iwmr)
  2231. {
  2232. struct irdma_allocate_stag_info *info;
  2233. struct ib_pd *pd = iwmr->ibmr.pd;
  2234. struct irdma_pd *iwpd = to_iwpd(pd);
  2235. int status;
  2236. struct irdma_cqp_request *cqp_request;
  2237. struct cqp_cmds_info *cqp_info;
  2238. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2239. if (!cqp_request)
  2240. return -ENOMEM;
  2241. cqp_info = &cqp_request->info;
  2242. info = &cqp_info->in.u.alloc_stag.info;
  2243. memset(info, 0, sizeof(*info));
  2244. info->page_size = PAGE_SIZE;
  2245. info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2246. info->pd_id = iwpd->sc_pd.pd_id;
  2247. info->total_len = iwmr->len;
  2248. info->all_memory = pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY;
  2249. info->remote_access = true;
  2250. cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG;
  2251. cqp_info->post_sq = 1;
  2252. cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev;
  2253. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  2254. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2255. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2256. return status;
  2257. }
  2258. /**
  2259. * irdma_alloc_mr - register stag for fast memory registration
  2260. * @pd: ibpd pointer
  2261. * @mr_type: memory for stag registrion
  2262. * @max_num_sg: man number of pages
  2263. */
  2264. static struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
  2265. u32 max_num_sg)
  2266. {
  2267. struct irdma_device *iwdev = to_iwdev(pd->device);
  2268. struct irdma_pble_alloc *palloc;
  2269. struct irdma_pbl *iwpbl;
  2270. struct irdma_mr *iwmr;
  2271. u32 stag;
  2272. int err_code;
  2273. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2274. if (!iwmr)
  2275. return ERR_PTR(-ENOMEM);
  2276. stag = irdma_create_stag(iwdev);
  2277. if (!stag) {
  2278. err_code = -ENOMEM;
  2279. goto err;
  2280. }
  2281. iwmr->stag = stag;
  2282. iwmr->ibmr.rkey = stag;
  2283. iwmr->ibmr.lkey = stag;
  2284. iwmr->ibmr.pd = pd;
  2285. iwmr->ibmr.device = pd->device;
  2286. iwpbl = &iwmr->iwpbl;
  2287. iwpbl->iwmr = iwmr;
  2288. iwmr->type = IRDMA_MEMREG_TYPE_MEM;
  2289. palloc = &iwpbl->pble_alloc;
  2290. iwmr->page_cnt = max_num_sg;
  2291. /* Use system PAGE_SIZE as the sg page sizes are unknown at this point */
  2292. iwmr->len = max_num_sg * PAGE_SIZE;
  2293. err_code = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt,
  2294. false);
  2295. if (err_code)
  2296. goto err_get_pble;
  2297. err_code = irdma_hw_alloc_stag(iwdev, iwmr);
  2298. if (err_code)
  2299. goto err_alloc_stag;
  2300. iwpbl->pbl_allocated = true;
  2301. return &iwmr->ibmr;
  2302. err_alloc_stag:
  2303. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2304. err_get_pble:
  2305. irdma_free_stag(iwdev, stag);
  2306. err:
  2307. kfree(iwmr);
  2308. return ERR_PTR(err_code);
  2309. }
  2310. /**
  2311. * irdma_set_page - populate pbl list for fmr
  2312. * @ibmr: ib mem to access iwarp mr pointer
  2313. * @addr: page dma address fro pbl list
  2314. */
  2315. static int irdma_set_page(struct ib_mr *ibmr, u64 addr)
  2316. {
  2317. struct irdma_mr *iwmr = to_iwmr(ibmr);
  2318. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2319. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2320. u64 *pbl;
  2321. if (unlikely(iwmr->npages == iwmr->page_cnt))
  2322. return -ENOMEM;
  2323. if (palloc->level == PBLE_LEVEL_2) {
  2324. struct irdma_pble_info *palloc_info =
  2325. palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT);
  2326. palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr;
  2327. } else {
  2328. pbl = palloc->level1.addr;
  2329. pbl[iwmr->npages] = addr;
  2330. }
  2331. iwmr->npages++;
  2332. return 0;
  2333. }
  2334. /**
  2335. * irdma_map_mr_sg - map of sg list for fmr
  2336. * @ibmr: ib mem to access iwarp mr pointer
  2337. * @sg: scatter gather list
  2338. * @sg_nents: number of sg pages
  2339. * @sg_offset: scatter gather list for fmr
  2340. */
  2341. static int irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  2342. int sg_nents, unsigned int *sg_offset)
  2343. {
  2344. struct irdma_mr *iwmr = to_iwmr(ibmr);
  2345. iwmr->npages = 0;
  2346. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page);
  2347. }
  2348. /**
  2349. * irdma_hwreg_mr - send cqp command for memory registration
  2350. * @iwdev: irdma device
  2351. * @iwmr: irdma mr pointer
  2352. * @access: access for MR
  2353. */
  2354. static int irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr,
  2355. u16 access)
  2356. {
  2357. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2358. struct irdma_reg_ns_stag_info *stag_info;
  2359. struct ib_pd *pd = iwmr->ibmr.pd;
  2360. struct irdma_pd *iwpd = to_iwpd(pd);
  2361. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2362. struct irdma_cqp_request *cqp_request;
  2363. struct cqp_cmds_info *cqp_info;
  2364. int ret;
  2365. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2366. if (!cqp_request)
  2367. return -ENOMEM;
  2368. cqp_info = &cqp_request->info;
  2369. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  2370. memset(stag_info, 0, sizeof(*stag_info));
  2371. stag_info->va = iwpbl->user_base;
  2372. stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2373. stag_info->stag_key = (u8)iwmr->stag;
  2374. stag_info->total_len = iwmr->len;
  2375. stag_info->access_rights = irdma_get_mr_access(access);
  2376. stag_info->pd_id = iwpd->sc_pd.pd_id;
  2377. stag_info->all_memory = pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY;
  2378. if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED)
  2379. stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED;
  2380. else
  2381. stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED;
  2382. stag_info->page_size = iwmr->page_size;
  2383. if (iwpbl->pbl_allocated) {
  2384. if (palloc->level == PBLE_LEVEL_1) {
  2385. stag_info->first_pm_pbl_index = palloc->level1.idx;
  2386. stag_info->chunk_size = 1;
  2387. } else {
  2388. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  2389. stag_info->chunk_size = 3;
  2390. }
  2391. } else {
  2392. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  2393. }
  2394. cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED;
  2395. cqp_info->post_sq = 1;
  2396. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;
  2397. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  2398. ret = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2399. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2400. return ret;
  2401. }
  2402. /**
  2403. * irdma_reg_user_mr - Register a user memory region
  2404. * @pd: ptr of pd
  2405. * @start: virtual start address
  2406. * @len: length of mr
  2407. * @virt: virtual address
  2408. * @access: access of mr
  2409. * @udata: user data
  2410. */
  2411. static struct ib_mr *irdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,
  2412. u64 virt, int access,
  2413. struct ib_udata *udata)
  2414. {
  2415. #define IRDMA_MEM_REG_MIN_REQ_LEN offsetofend(struct irdma_mem_reg_req, sq_pages)
  2416. struct irdma_device *iwdev = to_iwdev(pd->device);
  2417. struct irdma_ucontext *ucontext;
  2418. struct irdma_pble_alloc *palloc;
  2419. struct irdma_pbl *iwpbl;
  2420. struct irdma_mr *iwmr;
  2421. struct ib_umem *region;
  2422. struct irdma_mem_reg_req req;
  2423. u32 total, stag = 0;
  2424. u8 shadow_pgcnt = 1;
  2425. bool use_pbles = false;
  2426. unsigned long flags;
  2427. int err = -EINVAL;
  2428. int ret;
  2429. if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
  2430. return ERR_PTR(-EINVAL);
  2431. if (udata->inlen < IRDMA_MEM_REG_MIN_REQ_LEN)
  2432. return ERR_PTR(-EINVAL);
  2433. region = ib_umem_get(pd->device, start, len, access);
  2434. if (IS_ERR(region)) {
  2435. ibdev_dbg(&iwdev->ibdev,
  2436. "VERBS: Failed to create ib_umem region\n");
  2437. return (struct ib_mr *)region;
  2438. }
  2439. if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen))) {
  2440. ib_umem_release(region);
  2441. return ERR_PTR(-EFAULT);
  2442. }
  2443. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2444. if (!iwmr) {
  2445. ib_umem_release(region);
  2446. return ERR_PTR(-ENOMEM);
  2447. }
  2448. iwpbl = &iwmr->iwpbl;
  2449. iwpbl->iwmr = iwmr;
  2450. iwmr->region = region;
  2451. iwmr->ibmr.pd = pd;
  2452. iwmr->ibmr.device = pd->device;
  2453. iwmr->ibmr.iova = virt;
  2454. iwmr->page_size = PAGE_SIZE;
  2455. if (req.reg_type == IRDMA_MEMREG_TYPE_MEM) {
  2456. iwmr->page_size = ib_umem_find_best_pgsz(region,
  2457. iwdev->rf->sc_dev.hw_attrs.page_size_cap,
  2458. virt);
  2459. if (unlikely(!iwmr->page_size)) {
  2460. kfree(iwmr);
  2461. ib_umem_release(region);
  2462. return ERR_PTR(-EOPNOTSUPP);
  2463. }
  2464. }
  2465. iwmr->len = region->length;
  2466. iwpbl->user_base = virt;
  2467. palloc = &iwpbl->pble_alloc;
  2468. iwmr->type = req.reg_type;
  2469. iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
  2470. switch (req.reg_type) {
  2471. case IRDMA_MEMREG_TYPE_QP:
  2472. total = req.sq_pages + req.rq_pages + shadow_pgcnt;
  2473. if (total > iwmr->page_cnt) {
  2474. err = -EINVAL;
  2475. goto error;
  2476. }
  2477. total = req.sq_pages + req.rq_pages;
  2478. use_pbles = (total > 2);
  2479. err = irdma_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  2480. if (err)
  2481. goto error;
  2482. ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  2483. ibucontext);
  2484. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  2485. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  2486. iwpbl->on_list = true;
  2487. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  2488. break;
  2489. case IRDMA_MEMREG_TYPE_CQ:
  2490. if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE)
  2491. shadow_pgcnt = 0;
  2492. total = req.cq_pages + shadow_pgcnt;
  2493. if (total > iwmr->page_cnt) {
  2494. err = -EINVAL;
  2495. goto error;
  2496. }
  2497. use_pbles = (req.cq_pages > 1);
  2498. err = irdma_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  2499. if (err)
  2500. goto error;
  2501. ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  2502. ibucontext);
  2503. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  2504. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  2505. iwpbl->on_list = true;
  2506. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  2507. break;
  2508. case IRDMA_MEMREG_TYPE_MEM:
  2509. use_pbles = (iwmr->page_cnt != 1);
  2510. err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles, false);
  2511. if (err)
  2512. goto error;
  2513. if (use_pbles) {
  2514. ret = irdma_check_mr_contiguous(palloc,
  2515. iwmr->page_size);
  2516. if (ret) {
  2517. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2518. iwpbl->pbl_allocated = false;
  2519. }
  2520. }
  2521. stag = irdma_create_stag(iwdev);
  2522. if (!stag) {
  2523. err = -ENOMEM;
  2524. goto error;
  2525. }
  2526. iwmr->stag = stag;
  2527. iwmr->ibmr.rkey = stag;
  2528. iwmr->ibmr.lkey = stag;
  2529. err = irdma_hwreg_mr(iwdev, iwmr, access);
  2530. if (err) {
  2531. irdma_free_stag(iwdev, stag);
  2532. goto error;
  2533. }
  2534. break;
  2535. default:
  2536. goto error;
  2537. }
  2538. iwmr->type = req.reg_type;
  2539. return &iwmr->ibmr;
  2540. error:
  2541. if (palloc->level != PBLE_LEVEL_0 && iwpbl->pbl_allocated)
  2542. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2543. ib_umem_release(region);
  2544. kfree(iwmr);
  2545. return ERR_PTR(err);
  2546. }
  2547. /**
  2548. * irdma_reg_phys_mr - register kernel physical memory
  2549. * @pd: ibpd pointer
  2550. * @addr: physical address of memory to register
  2551. * @size: size of memory to register
  2552. * @access: Access rights
  2553. * @iova_start: start of virtual address for physical buffers
  2554. */
  2555. struct ib_mr *irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access,
  2556. u64 *iova_start)
  2557. {
  2558. struct irdma_device *iwdev = to_iwdev(pd->device);
  2559. struct irdma_pbl *iwpbl;
  2560. struct irdma_mr *iwmr;
  2561. u32 stag;
  2562. int ret;
  2563. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2564. if (!iwmr)
  2565. return ERR_PTR(-ENOMEM);
  2566. iwmr->ibmr.pd = pd;
  2567. iwmr->ibmr.device = pd->device;
  2568. iwpbl = &iwmr->iwpbl;
  2569. iwpbl->iwmr = iwmr;
  2570. iwmr->type = IRDMA_MEMREG_TYPE_MEM;
  2571. iwpbl->user_base = *iova_start;
  2572. stag = irdma_create_stag(iwdev);
  2573. if (!stag) {
  2574. ret = -ENOMEM;
  2575. goto err;
  2576. }
  2577. iwmr->stag = stag;
  2578. iwmr->ibmr.iova = *iova_start;
  2579. iwmr->ibmr.rkey = stag;
  2580. iwmr->ibmr.lkey = stag;
  2581. iwmr->page_cnt = 1;
  2582. iwmr->pgaddrmem[0] = addr;
  2583. iwmr->len = size;
  2584. iwmr->page_size = SZ_4K;
  2585. ret = irdma_hwreg_mr(iwdev, iwmr, access);
  2586. if (ret) {
  2587. irdma_free_stag(iwdev, stag);
  2588. goto err;
  2589. }
  2590. return &iwmr->ibmr;
  2591. err:
  2592. kfree(iwmr);
  2593. return ERR_PTR(ret);
  2594. }
  2595. /**
  2596. * irdma_get_dma_mr - register physical mem
  2597. * @pd: ptr of pd
  2598. * @acc: access for memory
  2599. */
  2600. static struct ib_mr *irdma_get_dma_mr(struct ib_pd *pd, int acc)
  2601. {
  2602. u64 kva = 0;
  2603. return irdma_reg_phys_mr(pd, 0, 0, acc, &kva);
  2604. }
  2605. /**
  2606. * irdma_del_memlist - Deleting pbl list entries for CQ/QP
  2607. * @iwmr: iwmr for IB's user page addresses
  2608. * @ucontext: ptr to user context
  2609. */
  2610. static void irdma_del_memlist(struct irdma_mr *iwmr,
  2611. struct irdma_ucontext *ucontext)
  2612. {
  2613. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2614. unsigned long flags;
  2615. switch (iwmr->type) {
  2616. case IRDMA_MEMREG_TYPE_CQ:
  2617. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  2618. if (iwpbl->on_list) {
  2619. iwpbl->on_list = false;
  2620. list_del(&iwpbl->list);
  2621. }
  2622. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  2623. break;
  2624. case IRDMA_MEMREG_TYPE_QP:
  2625. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  2626. if (iwpbl->on_list) {
  2627. iwpbl->on_list = false;
  2628. list_del(&iwpbl->list);
  2629. }
  2630. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  2631. break;
  2632. default:
  2633. break;
  2634. }
  2635. }
  2636. /**
  2637. * irdma_dereg_mr - deregister mr
  2638. * @ib_mr: mr ptr for dereg
  2639. * @udata: user data
  2640. */
  2641. static int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
  2642. {
  2643. struct ib_pd *ibpd = ib_mr->pd;
  2644. struct irdma_pd *iwpd = to_iwpd(ibpd);
  2645. struct irdma_mr *iwmr = to_iwmr(ib_mr);
  2646. struct irdma_device *iwdev = to_iwdev(ib_mr->device);
  2647. struct irdma_dealloc_stag_info *info;
  2648. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2649. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2650. struct irdma_cqp_request *cqp_request;
  2651. struct cqp_cmds_info *cqp_info;
  2652. int status;
  2653. if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) {
  2654. if (iwmr->region) {
  2655. struct irdma_ucontext *ucontext;
  2656. ucontext = rdma_udata_to_drv_context(udata,
  2657. struct irdma_ucontext,
  2658. ibucontext);
  2659. irdma_del_memlist(iwmr, ucontext);
  2660. }
  2661. goto done;
  2662. }
  2663. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2664. if (!cqp_request)
  2665. return -ENOMEM;
  2666. cqp_info = &cqp_request->info;
  2667. info = &cqp_info->in.u.dealloc_stag.info;
  2668. memset(info, 0, sizeof(*info));
  2669. info->pd_id = iwpd->sc_pd.pd_id;
  2670. info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
  2671. info->mr = true;
  2672. if (iwpbl->pbl_allocated)
  2673. info->dealloc_pbl = true;
  2674. cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
  2675. cqp_info->post_sq = 1;
  2676. cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
  2677. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  2678. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2679. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2680. if (status)
  2681. return status;
  2682. irdma_free_stag(iwdev, iwmr->stag);
  2683. done:
  2684. if (iwpbl->pbl_allocated)
  2685. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2686. ib_umem_release(iwmr->region);
  2687. kfree(iwmr);
  2688. return 0;
  2689. }
  2690. /**
  2691. * irdma_post_send - kernel application wr
  2692. * @ibqp: qp ptr for wr
  2693. * @ib_wr: work request ptr
  2694. * @bad_wr: return of bad wr if err
  2695. */
  2696. static int irdma_post_send(struct ib_qp *ibqp,
  2697. const struct ib_send_wr *ib_wr,
  2698. const struct ib_send_wr **bad_wr)
  2699. {
  2700. struct irdma_qp *iwqp;
  2701. struct irdma_qp_uk *ukqp;
  2702. struct irdma_sc_dev *dev;
  2703. struct irdma_post_sq_info info;
  2704. int err = 0;
  2705. unsigned long flags;
  2706. bool inv_stag;
  2707. struct irdma_ah *ah;
  2708. iwqp = to_iwqp(ibqp);
  2709. ukqp = &iwqp->sc_qp.qp_uk;
  2710. dev = &iwqp->iwdev->rf->sc_dev;
  2711. spin_lock_irqsave(&iwqp->lock, flags);
  2712. while (ib_wr) {
  2713. memset(&info, 0, sizeof(info));
  2714. inv_stag = false;
  2715. info.wr_id = (ib_wr->wr_id);
  2716. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  2717. info.signaled = true;
  2718. if (ib_wr->send_flags & IB_SEND_FENCE)
  2719. info.read_fence = true;
  2720. switch (ib_wr->opcode) {
  2721. case IB_WR_SEND_WITH_IMM:
  2722. if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) {
  2723. info.imm_data_valid = true;
  2724. info.imm_data = ntohl(ib_wr->ex.imm_data);
  2725. } else {
  2726. err = -EINVAL;
  2727. break;
  2728. }
  2729. fallthrough;
  2730. case IB_WR_SEND:
  2731. case IB_WR_SEND_WITH_INV:
  2732. if (ib_wr->opcode == IB_WR_SEND ||
  2733. ib_wr->opcode == IB_WR_SEND_WITH_IMM) {
  2734. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  2735. info.op_type = IRDMA_OP_TYPE_SEND_SOL;
  2736. else
  2737. info.op_type = IRDMA_OP_TYPE_SEND;
  2738. } else {
  2739. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  2740. info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV;
  2741. else
  2742. info.op_type = IRDMA_OP_TYPE_SEND_INV;
  2743. info.stag_to_inv = ib_wr->ex.invalidate_rkey;
  2744. }
  2745. info.op.send.num_sges = ib_wr->num_sge;
  2746. info.op.send.sg_list = ib_wr->sg_list;
  2747. if (iwqp->ibqp.qp_type == IB_QPT_UD ||
  2748. iwqp->ibqp.qp_type == IB_QPT_GSI) {
  2749. ah = to_iwah(ud_wr(ib_wr)->ah);
  2750. info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx;
  2751. info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;
  2752. info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;
  2753. }
  2754. if (ib_wr->send_flags & IB_SEND_INLINE)
  2755. err = irdma_uk_inline_send(ukqp, &info, false);
  2756. else
  2757. err = irdma_uk_send(ukqp, &info, false);
  2758. break;
  2759. case IB_WR_RDMA_WRITE_WITH_IMM:
  2760. if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) {
  2761. info.imm_data_valid = true;
  2762. info.imm_data = ntohl(ib_wr->ex.imm_data);
  2763. } else {
  2764. err = -EINVAL;
  2765. break;
  2766. }
  2767. fallthrough;
  2768. case IB_WR_RDMA_WRITE:
  2769. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  2770. info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL;
  2771. else
  2772. info.op_type = IRDMA_OP_TYPE_RDMA_WRITE;
  2773. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  2774. info.op.rdma_write.lo_sg_list = ib_wr->sg_list;
  2775. info.op.rdma_write.rem_addr.addr =
  2776. rdma_wr(ib_wr)->remote_addr;
  2777. info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
  2778. if (ib_wr->send_flags & IB_SEND_INLINE)
  2779. err = irdma_uk_inline_rdma_write(ukqp, &info, false);
  2780. else
  2781. err = irdma_uk_rdma_write(ukqp, &info, false);
  2782. break;
  2783. case IB_WR_RDMA_READ_WITH_INV:
  2784. inv_stag = true;
  2785. fallthrough;
  2786. case IB_WR_RDMA_READ:
  2787. if (ib_wr->num_sge >
  2788. dev->hw_attrs.uk_attrs.max_hw_read_sges) {
  2789. err = -EINVAL;
  2790. break;
  2791. }
  2792. info.op_type = IRDMA_OP_TYPE_RDMA_READ;
  2793. info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
  2794. info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
  2795. info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;
  2796. info.op.rdma_read.num_lo_sges = ib_wr->num_sge;
  2797. err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
  2798. break;
  2799. case IB_WR_LOCAL_INV:
  2800. info.op_type = IRDMA_OP_TYPE_INV_STAG;
  2801. info.local_fence = info.read_fence;
  2802. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  2803. err = irdma_uk_stag_local_invalidate(ukqp, &info, true);
  2804. break;
  2805. case IB_WR_REG_MR: {
  2806. struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  2807. struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  2808. struct irdma_fast_reg_stag_info stag_info = {};
  2809. stag_info.signaled = info.signaled;
  2810. stag_info.read_fence = info.read_fence;
  2811. stag_info.access_rights = irdma_get_mr_access(reg_wr(ib_wr)->access);
  2812. stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
  2813. stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
  2814. stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
  2815. stag_info.wr_id = ib_wr->wr_id;
  2816. stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED;
  2817. stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  2818. stag_info.total_len = iwmr->ibmr.length;
  2819. stag_info.reg_addr_pa = *palloc->level1.addr;
  2820. stag_info.first_pm_pbl_index = palloc->level1.idx;
  2821. stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  2822. if (iwmr->npages > IRDMA_MIN_PAGES_PER_FMR)
  2823. stag_info.chunk_size = 1;
  2824. err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,
  2825. true);
  2826. break;
  2827. }
  2828. default:
  2829. err = -EINVAL;
  2830. ibdev_dbg(&iwqp->iwdev->ibdev,
  2831. "VERBS: upost_send bad opcode = 0x%x\n",
  2832. ib_wr->opcode);
  2833. break;
  2834. }
  2835. if (err)
  2836. break;
  2837. ib_wr = ib_wr->next;
  2838. }
  2839. if (!iwqp->flush_issued) {
  2840. if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS)
  2841. irdma_uk_qp_post_wr(ukqp);
  2842. spin_unlock_irqrestore(&iwqp->lock, flags);
  2843. } else {
  2844. spin_unlock_irqrestore(&iwqp->lock, flags);
  2845. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2846. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2847. }
  2848. if (err)
  2849. *bad_wr = ib_wr;
  2850. return err;
  2851. }
  2852. /**
  2853. * irdma_post_recv - post receive wr for kernel application
  2854. * @ibqp: ib qp pointer
  2855. * @ib_wr: work request for receive
  2856. * @bad_wr: bad wr caused an error
  2857. */
  2858. static int irdma_post_recv(struct ib_qp *ibqp,
  2859. const struct ib_recv_wr *ib_wr,
  2860. const struct ib_recv_wr **bad_wr)
  2861. {
  2862. struct irdma_qp *iwqp;
  2863. struct irdma_qp_uk *ukqp;
  2864. struct irdma_post_rq_info post_recv = {};
  2865. unsigned long flags;
  2866. int err = 0;
  2867. iwqp = to_iwqp(ibqp);
  2868. ukqp = &iwqp->sc_qp.qp_uk;
  2869. spin_lock_irqsave(&iwqp->lock, flags);
  2870. while (ib_wr) {
  2871. post_recv.num_sges = ib_wr->num_sge;
  2872. post_recv.wr_id = ib_wr->wr_id;
  2873. post_recv.sg_list = ib_wr->sg_list;
  2874. err = irdma_uk_post_receive(ukqp, &post_recv);
  2875. if (err) {
  2876. ibdev_dbg(&iwqp->iwdev->ibdev,
  2877. "VERBS: post_recv err %d\n", err);
  2878. goto out;
  2879. }
  2880. ib_wr = ib_wr->next;
  2881. }
  2882. out:
  2883. spin_unlock_irqrestore(&iwqp->lock, flags);
  2884. if (iwqp->flush_issued)
  2885. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2886. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2887. if (err)
  2888. *bad_wr = ib_wr;
  2889. return err;
  2890. }
  2891. /**
  2892. * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status
  2893. * @opcode: iwarp flush code
  2894. */
  2895. static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)
  2896. {
  2897. switch (opcode) {
  2898. case FLUSH_PROT_ERR:
  2899. return IB_WC_LOC_PROT_ERR;
  2900. case FLUSH_REM_ACCESS_ERR:
  2901. return IB_WC_REM_ACCESS_ERR;
  2902. case FLUSH_LOC_QP_OP_ERR:
  2903. return IB_WC_LOC_QP_OP_ERR;
  2904. case FLUSH_REM_OP_ERR:
  2905. return IB_WC_REM_OP_ERR;
  2906. case FLUSH_LOC_LEN_ERR:
  2907. return IB_WC_LOC_LEN_ERR;
  2908. case FLUSH_GENERAL_ERR:
  2909. return IB_WC_WR_FLUSH_ERR;
  2910. case FLUSH_RETRY_EXC_ERR:
  2911. return IB_WC_RETRY_EXC_ERR;
  2912. case FLUSH_MW_BIND_ERR:
  2913. return IB_WC_MW_BIND_ERR;
  2914. case FLUSH_REM_INV_REQ_ERR:
  2915. return IB_WC_REM_INV_REQ_ERR;
  2916. case FLUSH_FATAL_ERR:
  2917. default:
  2918. return IB_WC_FATAL_ERR;
  2919. }
  2920. }
  2921. /**
  2922. * irdma_process_cqe - process cqe info
  2923. * @entry: processed cqe
  2924. * @cq_poll_info: cqe info
  2925. */
  2926. static void irdma_process_cqe(struct ib_wc *entry,
  2927. struct irdma_cq_poll_info *cq_poll_info)
  2928. {
  2929. struct irdma_sc_qp *qp;
  2930. entry->wc_flags = 0;
  2931. entry->pkey_index = 0;
  2932. entry->wr_id = cq_poll_info->wr_id;
  2933. qp = cq_poll_info->qp_handle;
  2934. entry->qp = qp->qp_uk.back_qp;
  2935. if (cq_poll_info->error) {
  2936. entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ?
  2937. irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR;
  2938. entry->vendor_err = cq_poll_info->major_err << 16 |
  2939. cq_poll_info->minor_err;
  2940. } else {
  2941. entry->status = IB_WC_SUCCESS;
  2942. if (cq_poll_info->imm_valid) {
  2943. entry->ex.imm_data = htonl(cq_poll_info->imm_data);
  2944. entry->wc_flags |= IB_WC_WITH_IMM;
  2945. }
  2946. if (cq_poll_info->ud_smac_valid) {
  2947. ether_addr_copy(entry->smac, cq_poll_info->ud_smac);
  2948. entry->wc_flags |= IB_WC_WITH_SMAC;
  2949. }
  2950. if (cq_poll_info->ud_vlan_valid) {
  2951. u16 vlan = cq_poll_info->ud_vlan & VLAN_VID_MASK;
  2952. entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT;
  2953. if (vlan) {
  2954. entry->vlan_id = vlan;
  2955. entry->wc_flags |= IB_WC_WITH_VLAN;
  2956. }
  2957. } else {
  2958. entry->sl = 0;
  2959. }
  2960. }
  2961. if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) {
  2962. set_ib_wc_op_sq(cq_poll_info, entry);
  2963. } else {
  2964. set_ib_wc_op_rq(cq_poll_info, entry,
  2965. qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM ?
  2966. true : false);
  2967. if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD &&
  2968. cq_poll_info->stag_invalid_set) {
  2969. entry->ex.invalidate_rkey = cq_poll_info->inv_stag;
  2970. entry->wc_flags |= IB_WC_WITH_INVALIDATE;
  2971. }
  2972. }
  2973. if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) {
  2974. entry->src_qp = cq_poll_info->ud_src_qpn;
  2975. entry->slid = 0;
  2976. entry->wc_flags |=
  2977. (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE);
  2978. entry->network_hdr_type = cq_poll_info->ipv4 ?
  2979. RDMA_NETWORK_IPV4 :
  2980. RDMA_NETWORK_IPV6;
  2981. } else {
  2982. entry->src_qp = cq_poll_info->qp_id;
  2983. }
  2984. entry->byte_len = cq_poll_info->bytes_xfered;
  2985. }
  2986. /**
  2987. * irdma_poll_one - poll one entry of the CQ
  2988. * @ukcq: ukcq to poll
  2989. * @cur_cqe: current CQE info to be filled in
  2990. * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ
  2991. *
  2992. * Returns the internal irdma device error code or 0 on success
  2993. */
  2994. static inline int irdma_poll_one(struct irdma_cq_uk *ukcq,
  2995. struct irdma_cq_poll_info *cur_cqe,
  2996. struct ib_wc *entry)
  2997. {
  2998. int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe);
  2999. if (ret)
  3000. return ret;
  3001. irdma_process_cqe(entry, cur_cqe);
  3002. return 0;
  3003. }
  3004. /**
  3005. * __irdma_poll_cq - poll cq for completion (kernel apps)
  3006. * @iwcq: cq to poll
  3007. * @num_entries: number of entries to poll
  3008. * @entry: wr of a completed entry
  3009. */
  3010. static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry)
  3011. {
  3012. struct list_head *tmp_node, *list_node;
  3013. struct irdma_cq_buf *last_buf = NULL;
  3014. struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;
  3015. struct irdma_cq_buf *cq_buf;
  3016. int ret;
  3017. struct irdma_device *iwdev;
  3018. struct irdma_cq_uk *ukcq;
  3019. bool cq_new_cqe = false;
  3020. int resized_bufs = 0;
  3021. int npolled = 0;
  3022. iwdev = to_iwdev(iwcq->ibcq.device);
  3023. ukcq = &iwcq->sc_cq.cq_uk;
  3024. /* go through the list of previously resized CQ buffers */
  3025. list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
  3026. cq_buf = container_of(list_node, struct irdma_cq_buf, list);
  3027. while (npolled < num_entries) {
  3028. ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled);
  3029. if (!ret) {
  3030. ++npolled;
  3031. cq_new_cqe = true;
  3032. continue;
  3033. }
  3034. if (ret == -ENOENT)
  3035. break;
  3036. /* QP using the CQ is destroyed. Skip reporting this CQE */
  3037. if (ret == -EFAULT) {
  3038. cq_new_cqe = true;
  3039. continue;
  3040. }
  3041. goto error;
  3042. }
  3043. /* save the resized CQ buffer which received the last cqe */
  3044. if (cq_new_cqe)
  3045. last_buf = cq_buf;
  3046. cq_new_cqe = false;
  3047. }
  3048. /* check the current CQ for new cqes */
  3049. while (npolled < num_entries) {
  3050. ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled);
  3051. if (ret == -ENOENT) {
  3052. ret = irdma_generated_cmpls(iwcq, cur_cqe);
  3053. if (!ret)
  3054. irdma_process_cqe(entry + npolled, cur_cqe);
  3055. }
  3056. if (!ret) {
  3057. ++npolled;
  3058. cq_new_cqe = true;
  3059. continue;
  3060. }
  3061. if (ret == -ENOENT)
  3062. break;
  3063. /* QP using the CQ is destroyed. Skip reporting this CQE */
  3064. if (ret == -EFAULT) {
  3065. cq_new_cqe = true;
  3066. continue;
  3067. }
  3068. goto error;
  3069. }
  3070. if (cq_new_cqe)
  3071. /* all previous CQ resizes are complete */
  3072. resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL);
  3073. else if (last_buf)
  3074. /* only CQ resizes up to the last_buf are complete */
  3075. resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf);
  3076. if (resized_bufs)
  3077. /* report to the HW the number of complete CQ resizes */
  3078. irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs);
  3079. return npolled;
  3080. error:
  3081. ibdev_dbg(&iwdev->ibdev, "%s: Error polling CQ, irdma_err: %d\n",
  3082. __func__, ret);
  3083. return ret;
  3084. }
  3085. /**
  3086. * irdma_poll_cq - poll cq for completion (kernel apps)
  3087. * @ibcq: cq to poll
  3088. * @num_entries: number of entries to poll
  3089. * @entry: wr of a completed entry
  3090. */
  3091. static int irdma_poll_cq(struct ib_cq *ibcq, int num_entries,
  3092. struct ib_wc *entry)
  3093. {
  3094. struct irdma_cq *iwcq;
  3095. unsigned long flags;
  3096. int ret;
  3097. iwcq = to_iwcq(ibcq);
  3098. spin_lock_irqsave(&iwcq->lock, flags);
  3099. ret = __irdma_poll_cq(iwcq, num_entries, entry);
  3100. spin_unlock_irqrestore(&iwcq->lock, flags);
  3101. return ret;
  3102. }
  3103. /**
  3104. * irdma_req_notify_cq - arm cq kernel application
  3105. * @ibcq: cq to arm
  3106. * @notify_flags: notofication flags
  3107. */
  3108. static int irdma_req_notify_cq(struct ib_cq *ibcq,
  3109. enum ib_cq_notify_flags notify_flags)
  3110. {
  3111. struct irdma_cq *iwcq;
  3112. struct irdma_cq_uk *ukcq;
  3113. unsigned long flags;
  3114. enum irdma_cmpl_notify cq_notify;
  3115. bool promo_event = false;
  3116. int ret = 0;
  3117. cq_notify = notify_flags == IB_CQ_SOLICITED ?
  3118. IRDMA_CQ_COMPL_SOLICITED : IRDMA_CQ_COMPL_EVENT;
  3119. iwcq = to_iwcq(ibcq);
  3120. ukcq = &iwcq->sc_cq.cq_uk;
  3121. spin_lock_irqsave(&iwcq->lock, flags);
  3122. /* Only promote to arm the CQ for any event if the last arm event was solicited. */
  3123. if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED && notify_flags != IB_CQ_SOLICITED)
  3124. promo_event = true;
  3125. if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) {
  3126. iwcq->last_notify = cq_notify;
  3127. irdma_uk_cq_request_notification(ukcq, cq_notify);
  3128. }
  3129. if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
  3130. (!irdma_cq_empty(iwcq) || !list_empty(&iwcq->cmpl_generated)))
  3131. ret = 1;
  3132. spin_unlock_irqrestore(&iwcq->lock, flags);
  3133. return ret;
  3134. }
  3135. static int irdma_roce_port_immutable(struct ib_device *ibdev, u32 port_num,
  3136. struct ib_port_immutable *immutable)
  3137. {
  3138. struct ib_port_attr attr;
  3139. int err;
  3140. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  3141. err = ib_query_port(ibdev, port_num, &attr);
  3142. if (err)
  3143. return err;
  3144. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  3145. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  3146. immutable->gid_tbl_len = attr.gid_tbl_len;
  3147. return 0;
  3148. }
  3149. static int irdma_iw_port_immutable(struct ib_device *ibdev, u32 port_num,
  3150. struct ib_port_immutable *immutable)
  3151. {
  3152. struct ib_port_attr attr;
  3153. int err;
  3154. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  3155. err = ib_query_port(ibdev, port_num, &attr);
  3156. if (err)
  3157. return err;
  3158. immutable->gid_tbl_len = attr.gid_tbl_len;
  3159. return 0;
  3160. }
  3161. static const struct rdma_stat_desc irdma_hw_stat_descs[] = {
  3162. /* 32bit names */
  3163. [IRDMA_HW_STAT_INDEX_RXVLANERR].name = "rxVlanErrors",
  3164. [IRDMA_HW_STAT_INDEX_IP4RXDISCARD].name = "ip4InDiscards",
  3165. [IRDMA_HW_STAT_INDEX_IP4RXTRUNC].name = "ip4InTruncatedPkts",
  3166. [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE].name = "ip4OutNoRoutes",
  3167. [IRDMA_HW_STAT_INDEX_IP6RXDISCARD].name = "ip6InDiscards",
  3168. [IRDMA_HW_STAT_INDEX_IP6RXTRUNC].name = "ip6InTruncatedPkts",
  3169. [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE].name = "ip6OutNoRoutes",
  3170. [IRDMA_HW_STAT_INDEX_TCPRTXSEG].name = "tcpRetransSegs",
  3171. [IRDMA_HW_STAT_INDEX_TCPRXOPTERR].name = "tcpInOptErrors",
  3172. [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR].name = "tcpInProtoErrors",
  3173. [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED].name = "cnpHandled",
  3174. [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED].name = "cnpIgnored",
  3175. [IRDMA_HW_STAT_INDEX_TXNPCNPSENT].name = "cnpSent",
  3176. /* 64bit names */
  3177. [IRDMA_HW_STAT_INDEX_IP4RXOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3178. "ip4InOctets",
  3179. [IRDMA_HW_STAT_INDEX_IP4RXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3180. "ip4InPkts",
  3181. [IRDMA_HW_STAT_INDEX_IP4RXFRAGS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3182. "ip4InReasmRqd",
  3183. [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3184. "ip4InMcastOctets",
  3185. [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3186. "ip4InMcastPkts",
  3187. [IRDMA_HW_STAT_INDEX_IP4TXOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3188. "ip4OutOctets",
  3189. [IRDMA_HW_STAT_INDEX_IP4TXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3190. "ip4OutPkts",
  3191. [IRDMA_HW_STAT_INDEX_IP4TXFRAGS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3192. "ip4OutSegRqd",
  3193. [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3194. "ip4OutMcastOctets",
  3195. [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3196. "ip4OutMcastPkts",
  3197. [IRDMA_HW_STAT_INDEX_IP6RXOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3198. "ip6InOctets",
  3199. [IRDMA_HW_STAT_INDEX_IP6RXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3200. "ip6InPkts",
  3201. [IRDMA_HW_STAT_INDEX_IP6RXFRAGS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3202. "ip6InReasmRqd",
  3203. [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3204. "ip6InMcastOctets",
  3205. [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3206. "ip6InMcastPkts",
  3207. [IRDMA_HW_STAT_INDEX_IP6TXOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3208. "ip6OutOctets",
  3209. [IRDMA_HW_STAT_INDEX_IP6TXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3210. "ip6OutPkts",
  3211. [IRDMA_HW_STAT_INDEX_IP6TXFRAGS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3212. "ip6OutSegRqd",
  3213. [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3214. "ip6OutMcastOctets",
  3215. [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3216. "ip6OutMcastPkts",
  3217. [IRDMA_HW_STAT_INDEX_TCPRXSEGS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3218. "tcpInSegs",
  3219. [IRDMA_HW_STAT_INDEX_TCPTXSEG + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3220. "tcpOutSegs",
  3221. [IRDMA_HW_STAT_INDEX_RDMARXRDS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3222. "iwInRdmaReads",
  3223. [IRDMA_HW_STAT_INDEX_RDMARXSNDS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3224. "iwInRdmaSends",
  3225. [IRDMA_HW_STAT_INDEX_RDMARXWRS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3226. "iwInRdmaWrites",
  3227. [IRDMA_HW_STAT_INDEX_RDMATXRDS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3228. "iwOutRdmaReads",
  3229. [IRDMA_HW_STAT_INDEX_RDMATXSNDS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3230. "iwOutRdmaSends",
  3231. [IRDMA_HW_STAT_INDEX_RDMATXWRS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3232. "iwOutRdmaWrites",
  3233. [IRDMA_HW_STAT_INDEX_RDMAVBND + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3234. "iwRdmaBnd",
  3235. [IRDMA_HW_STAT_INDEX_RDMAVINV + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3236. "iwRdmaInv",
  3237. [IRDMA_HW_STAT_INDEX_UDPRXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3238. "RxUDP",
  3239. [IRDMA_HW_STAT_INDEX_UDPTXPKTS + IRDMA_HW_STAT_INDEX_MAX_32].name =
  3240. "TxUDP",
  3241. [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS + IRDMA_HW_STAT_INDEX_MAX_32]
  3242. .name = "RxECNMrkd",
  3243. };
  3244. static void irdma_get_dev_fw_str(struct ib_device *dev, char *str)
  3245. {
  3246. struct irdma_device *iwdev = to_iwdev(dev);
  3247. snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u",
  3248. irdma_fw_major_ver(&iwdev->rf->sc_dev),
  3249. irdma_fw_minor_ver(&iwdev->rf->sc_dev));
  3250. }
  3251. /**
  3252. * irdma_alloc_hw_port_stats - Allocate a hw stats structure
  3253. * @ibdev: device pointer from stack
  3254. * @port_num: port number
  3255. */
  3256. static struct rdma_hw_stats *irdma_alloc_hw_port_stats(struct ib_device *ibdev,
  3257. u32 port_num)
  3258. {
  3259. int num_counters = IRDMA_HW_STAT_INDEX_MAX_32 +
  3260. IRDMA_HW_STAT_INDEX_MAX_64;
  3261. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  3262. BUILD_BUG_ON(ARRAY_SIZE(irdma_hw_stat_descs) !=
  3263. (IRDMA_HW_STAT_INDEX_MAX_32 + IRDMA_HW_STAT_INDEX_MAX_64));
  3264. return rdma_alloc_hw_stats_struct(irdma_hw_stat_descs, num_counters,
  3265. lifespan);
  3266. }
  3267. /**
  3268. * irdma_get_hw_stats - Populates the rdma_hw_stats structure
  3269. * @ibdev: device pointer from stack
  3270. * @stats: stats pointer from stack
  3271. * @port_num: port number
  3272. * @index: which hw counter the stack is requesting we update
  3273. */
  3274. static int irdma_get_hw_stats(struct ib_device *ibdev,
  3275. struct rdma_hw_stats *stats, u32 port_num,
  3276. int index)
  3277. {
  3278. struct irdma_device *iwdev = to_iwdev(ibdev);
  3279. struct irdma_dev_hw_stats *hw_stats = &iwdev->vsi.pestat->hw_stats;
  3280. if (iwdev->rf->rdma_ver >= IRDMA_GEN_2)
  3281. irdma_cqp_gather_stats_cmd(&iwdev->rf->sc_dev, iwdev->vsi.pestat, true);
  3282. else
  3283. irdma_cqp_gather_stats_gen1(&iwdev->rf->sc_dev, iwdev->vsi.pestat);
  3284. memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
  3285. return stats->num_counters;
  3286. }
  3287. /**
  3288. * irdma_query_gid - Query port GID
  3289. * @ibdev: device pointer from stack
  3290. * @port: port number
  3291. * @index: Entry index
  3292. * @gid: Global ID
  3293. */
  3294. static int irdma_query_gid(struct ib_device *ibdev, u32 port, int index,
  3295. union ib_gid *gid)
  3296. {
  3297. struct irdma_device *iwdev = to_iwdev(ibdev);
  3298. memset(gid->raw, 0, sizeof(gid->raw));
  3299. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  3300. return 0;
  3301. }
  3302. /**
  3303. * mcast_list_add - Add a new mcast item to list
  3304. * @rf: RDMA PCI function
  3305. * @new_elem: pointer to element to add
  3306. */
  3307. static void mcast_list_add(struct irdma_pci_f *rf,
  3308. struct mc_table_list *new_elem)
  3309. {
  3310. list_add(&new_elem->list, &rf->mc_qht_list.list);
  3311. }
  3312. /**
  3313. * mcast_list_del - Remove an mcast item from list
  3314. * @mc_qht_elem: pointer to mcast table list element
  3315. */
  3316. static void mcast_list_del(struct mc_table_list *mc_qht_elem)
  3317. {
  3318. if (mc_qht_elem)
  3319. list_del(&mc_qht_elem->list);
  3320. }
  3321. /**
  3322. * mcast_list_lookup_ip - Search mcast list for address
  3323. * @rf: RDMA PCI function
  3324. * @ip_mcast: pointer to mcast IP address
  3325. */
  3326. static struct mc_table_list *mcast_list_lookup_ip(struct irdma_pci_f *rf,
  3327. u32 *ip_mcast)
  3328. {
  3329. struct mc_table_list *mc_qht_el;
  3330. struct list_head *pos, *q;
  3331. list_for_each_safe (pos, q, &rf->mc_qht_list.list) {
  3332. mc_qht_el = list_entry(pos, struct mc_table_list, list);
  3333. if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast,
  3334. sizeof(mc_qht_el->mc_info.dest_ip)))
  3335. return mc_qht_el;
  3336. }
  3337. return NULL;
  3338. }
  3339. /**
  3340. * irdma_mcast_cqp_op - perform a mcast cqp operation
  3341. * @iwdev: irdma device
  3342. * @mc_grp_ctx: mcast group info
  3343. * @op: operation
  3344. *
  3345. * returns error status
  3346. */
  3347. static int irdma_mcast_cqp_op(struct irdma_device *iwdev,
  3348. struct irdma_mcast_grp_info *mc_grp_ctx, u8 op)
  3349. {
  3350. struct cqp_cmds_info *cqp_info;
  3351. struct irdma_cqp_request *cqp_request;
  3352. int status;
  3353. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  3354. if (!cqp_request)
  3355. return -ENOMEM;
  3356. cqp_request->info.in.u.mc_create.info = *mc_grp_ctx;
  3357. cqp_info = &cqp_request->info;
  3358. cqp_info->cqp_cmd = op;
  3359. cqp_info->post_sq = 1;
  3360. cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request;
  3361. cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;
  3362. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  3363. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  3364. return status;
  3365. }
  3366. /**
  3367. * irdma_mcast_mac - Get the multicast MAC for an IP address
  3368. * @ip_addr: IPv4 or IPv6 address
  3369. * @mac: pointer to result MAC address
  3370. * @ipv4: flag indicating IPv4 or IPv6
  3371. *
  3372. */
  3373. void irdma_mcast_mac(u32 *ip_addr, u8 *mac, bool ipv4)
  3374. {
  3375. u8 *ip = (u8 *)ip_addr;
  3376. if (ipv4) {
  3377. unsigned char mac4[ETH_ALEN] = {0x01, 0x00, 0x5E, 0x00,
  3378. 0x00, 0x00};
  3379. mac4[3] = ip[2] & 0x7F;
  3380. mac4[4] = ip[1];
  3381. mac4[5] = ip[0];
  3382. ether_addr_copy(mac, mac4);
  3383. } else {
  3384. unsigned char mac6[ETH_ALEN] = {0x33, 0x33, 0x00, 0x00,
  3385. 0x00, 0x00};
  3386. mac6[2] = ip[3];
  3387. mac6[3] = ip[2];
  3388. mac6[4] = ip[1];
  3389. mac6[5] = ip[0];
  3390. ether_addr_copy(mac, mac6);
  3391. }
  3392. }
  3393. /**
  3394. * irdma_attach_mcast - attach a qp to a multicast group
  3395. * @ibqp: ptr to qp
  3396. * @ibgid: pointer to global ID
  3397. * @lid: local ID
  3398. *
  3399. * returns error status
  3400. */
  3401. static int irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
  3402. {
  3403. struct irdma_qp *iwqp = to_iwqp(ibqp);
  3404. struct irdma_device *iwdev = iwqp->iwdev;
  3405. struct irdma_pci_f *rf = iwdev->rf;
  3406. struct mc_table_list *mc_qht_elem;
  3407. struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
  3408. unsigned long flags;
  3409. u32 ip_addr[4] = {};
  3410. u32 mgn;
  3411. u32 no_mgs;
  3412. int ret = 0;
  3413. bool ipv4;
  3414. u16 vlan_id;
  3415. union irdma_sockaddr sgid_addr;
  3416. unsigned char dmac[ETH_ALEN];
  3417. rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
  3418. if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) {
  3419. irdma_copy_ip_ntohl(ip_addr,
  3420. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3421. irdma_netdev_vlan_ipv6(ip_addr, &vlan_id, NULL);
  3422. ipv4 = false;
  3423. ibdev_dbg(&iwdev->ibdev,
  3424. "VERBS: qp_id=%d, IP6address=%pI6\n", ibqp->qp_num,
  3425. ip_addr);
  3426. irdma_mcast_mac(ip_addr, dmac, false);
  3427. } else {
  3428. ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3429. ipv4 = true;
  3430. vlan_id = irdma_get_vlan_ipv4(ip_addr);
  3431. irdma_mcast_mac(ip_addr, dmac, true);
  3432. ibdev_dbg(&iwdev->ibdev,
  3433. "VERBS: qp_id=%d, IP4address=%pI4, MAC=%pM\n",
  3434. ibqp->qp_num, ip_addr, dmac);
  3435. }
  3436. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3437. mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
  3438. if (!mc_qht_elem) {
  3439. struct irdma_dma_mem *dma_mem_mc;
  3440. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3441. mc_qht_elem = kzalloc(sizeof(*mc_qht_elem), GFP_KERNEL);
  3442. if (!mc_qht_elem)
  3443. return -ENOMEM;
  3444. mc_qht_elem->mc_info.ipv4_valid = ipv4;
  3445. memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr,
  3446. sizeof(mc_qht_elem->mc_info.dest_ip));
  3447. ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg,
  3448. &mgn, &rf->next_mcg);
  3449. if (ret) {
  3450. kfree(mc_qht_elem);
  3451. return -ENOMEM;
  3452. }
  3453. mc_qht_elem->mc_info.mgn = mgn;
  3454. dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc;
  3455. dma_mem_mc->size = ALIGN(sizeof(u64) * IRDMA_MAX_MGS_PER_CTX,
  3456. IRDMA_HW_PAGE_SIZE);
  3457. dma_mem_mc->va = dma_alloc_coherent(rf->hw.device,
  3458. dma_mem_mc->size,
  3459. &dma_mem_mc->pa,
  3460. GFP_KERNEL);
  3461. if (!dma_mem_mc->va) {
  3462. irdma_free_rsrc(rf, rf->allocated_mcgs, mgn);
  3463. kfree(mc_qht_elem);
  3464. return -ENOMEM;
  3465. }
  3466. mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn;
  3467. memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr,
  3468. sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr));
  3469. mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4;
  3470. mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id;
  3471. if (vlan_id < VLAN_N_VID)
  3472. mc_qht_elem->mc_grp_ctx.vlan_valid = true;
  3473. mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->vsi.fcn_id;
  3474. mc_qht_elem->mc_grp_ctx.qs_handle =
  3475. iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle;
  3476. ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac);
  3477. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3478. mcast_list_add(rf, mc_qht_elem);
  3479. } else {
  3480. if (mc_qht_elem->mc_grp_ctx.no_of_mgs ==
  3481. IRDMA_MAX_MGS_PER_CTX) {
  3482. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3483. return -ENOMEM;
  3484. }
  3485. }
  3486. mcg_info.qp_id = iwqp->ibqp.qp_num;
  3487. no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs;
  3488. irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3489. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3490. /* Only if there is a change do we need to modify or create */
  3491. if (!no_mgs) {
  3492. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3493. IRDMA_OP_MC_CREATE);
  3494. } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3495. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3496. IRDMA_OP_MC_MODIFY);
  3497. } else {
  3498. return 0;
  3499. }
  3500. if (ret)
  3501. goto error;
  3502. return 0;
  3503. error:
  3504. irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3505. if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3506. mcast_list_del(mc_qht_elem);
  3507. dma_free_coherent(rf->hw.device,
  3508. mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
  3509. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
  3510. mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
  3511. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
  3512. irdma_free_rsrc(rf, rf->allocated_mcgs,
  3513. mc_qht_elem->mc_grp_ctx.mg_id);
  3514. kfree(mc_qht_elem);
  3515. }
  3516. return ret;
  3517. }
  3518. /**
  3519. * irdma_detach_mcast - detach a qp from a multicast group
  3520. * @ibqp: ptr to qp
  3521. * @ibgid: pointer to global ID
  3522. * @lid: local ID
  3523. *
  3524. * returns error status
  3525. */
  3526. static int irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
  3527. {
  3528. struct irdma_qp *iwqp = to_iwqp(ibqp);
  3529. struct irdma_device *iwdev = iwqp->iwdev;
  3530. struct irdma_pci_f *rf = iwdev->rf;
  3531. u32 ip_addr[4] = {};
  3532. struct mc_table_list *mc_qht_elem;
  3533. struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
  3534. int ret;
  3535. unsigned long flags;
  3536. union irdma_sockaddr sgid_addr;
  3537. rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
  3538. if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
  3539. irdma_copy_ip_ntohl(ip_addr,
  3540. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3541. else
  3542. ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3543. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3544. mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
  3545. if (!mc_qht_elem) {
  3546. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3547. ibdev_dbg(&iwdev->ibdev,
  3548. "VERBS: address not found MCG\n");
  3549. return 0;
  3550. }
  3551. mcg_info.qp_id = iwqp->ibqp.qp_num;
  3552. irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3553. if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3554. mcast_list_del(mc_qht_elem);
  3555. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3556. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3557. IRDMA_OP_MC_DESTROY);
  3558. if (ret) {
  3559. ibdev_dbg(&iwdev->ibdev,
  3560. "VERBS: failed MC_DESTROY MCG\n");
  3561. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3562. mcast_list_add(rf, mc_qht_elem);
  3563. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3564. return -EAGAIN;
  3565. }
  3566. dma_free_coherent(rf->hw.device,
  3567. mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
  3568. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
  3569. mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
  3570. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
  3571. irdma_free_rsrc(rf, rf->allocated_mcgs,
  3572. mc_qht_elem->mc_grp_ctx.mg_id);
  3573. kfree(mc_qht_elem);
  3574. } else {
  3575. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3576. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3577. IRDMA_OP_MC_MODIFY);
  3578. if (ret) {
  3579. ibdev_dbg(&iwdev->ibdev,
  3580. "VERBS: failed Modify MCG\n");
  3581. return ret;
  3582. }
  3583. }
  3584. return 0;
  3585. }
  3586. static int irdma_create_hw_ah(struct irdma_device *iwdev, struct irdma_ah *ah, bool sleep)
  3587. {
  3588. struct irdma_pci_f *rf = iwdev->rf;
  3589. int err;
  3590. err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, &ah->sc_ah.ah_info.ah_idx,
  3591. &rf->next_ah);
  3592. if (err)
  3593. return err;
  3594. err = irdma_ah_cqp_op(rf, &ah->sc_ah, IRDMA_OP_AH_CREATE, sleep,
  3595. irdma_gsi_ud_qp_ah_cb, &ah->sc_ah);
  3596. if (err) {
  3597. ibdev_dbg(&iwdev->ibdev, "VERBS: CQP-OP Create AH fail");
  3598. goto err_ah_create;
  3599. }
  3600. if (!sleep) {
  3601. int cnt = CQP_COMPL_WAIT_TIME_MS * CQP_TIMEOUT_THRESHOLD;
  3602. do {
  3603. irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
  3604. mdelay(1);
  3605. } while (!ah->sc_ah.ah_info.ah_valid && --cnt);
  3606. if (!cnt) {
  3607. ibdev_dbg(&iwdev->ibdev, "VERBS: CQP create AH timed out");
  3608. err = -ETIMEDOUT;
  3609. goto err_ah_create;
  3610. }
  3611. }
  3612. return 0;
  3613. err_ah_create:
  3614. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah->sc_ah.ah_info.ah_idx);
  3615. return err;
  3616. }
  3617. static int irdma_setup_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr)
  3618. {
  3619. struct irdma_pd *pd = to_iwpd(ibah->pd);
  3620. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  3621. struct rdma_ah_attr *ah_attr = attr->ah_attr;
  3622. const struct ib_gid_attr *sgid_attr;
  3623. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  3624. struct irdma_pci_f *rf = iwdev->rf;
  3625. struct irdma_sc_ah *sc_ah;
  3626. struct irdma_ah_info *ah_info;
  3627. union irdma_sockaddr sgid_addr, dgid_addr;
  3628. int err;
  3629. u8 dmac[ETH_ALEN];
  3630. ah->pd = pd;
  3631. sc_ah = &ah->sc_ah;
  3632. sc_ah->ah_info.vsi = &iwdev->vsi;
  3633. irdma_sc_init_ah(&rf->sc_dev, sc_ah);
  3634. ah->sgid_index = ah_attr->grh.sgid_index;
  3635. sgid_attr = ah_attr->grh.sgid_attr;
  3636. memcpy(&ah->dgid, &ah_attr->grh.dgid, sizeof(ah->dgid));
  3637. rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid);
  3638. rdma_gid2ip((struct sockaddr *)&dgid_addr, &ah_attr->grh.dgid);
  3639. ah->av.attrs = *ah_attr;
  3640. ah->av.net_type = rdma_gid_attr_network_type(sgid_attr);
  3641. ah_info = &sc_ah->ah_info;
  3642. ah_info->pd_idx = pd->sc_pd.pd_id;
  3643. if (ah_attr->ah_flags & IB_AH_GRH) {
  3644. ah_info->flow_label = ah_attr->grh.flow_label;
  3645. ah_info->hop_ttl = ah_attr->grh.hop_limit;
  3646. ah_info->tc_tos = ah_attr->grh.traffic_class;
  3647. }
  3648. ether_addr_copy(dmac, ah_attr->roce.dmac);
  3649. if (ah->av.net_type == RDMA_NETWORK_IPV4) {
  3650. ah_info->ipv4_valid = true;
  3651. ah_info->dest_ip_addr[0] =
  3652. ntohl(dgid_addr.saddr_in.sin_addr.s_addr);
  3653. ah_info->src_ip_addr[0] =
  3654. ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3655. ah_info->do_lpbk = irdma_ipv4_is_lpb(ah_info->src_ip_addr[0],
  3656. ah_info->dest_ip_addr[0]);
  3657. if (ipv4_is_multicast(dgid_addr.saddr_in.sin_addr.s_addr)) {
  3658. ah_info->do_lpbk = true;
  3659. irdma_mcast_mac(ah_info->dest_ip_addr, dmac, true);
  3660. }
  3661. } else {
  3662. irdma_copy_ip_ntohl(ah_info->dest_ip_addr,
  3663. dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3664. irdma_copy_ip_ntohl(ah_info->src_ip_addr,
  3665. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3666. ah_info->do_lpbk = irdma_ipv6_is_lpb(ah_info->src_ip_addr,
  3667. ah_info->dest_ip_addr);
  3668. if (rdma_is_multicast_addr(&dgid_addr.saddr_in6.sin6_addr)) {
  3669. ah_info->do_lpbk = true;
  3670. irdma_mcast_mac(ah_info->dest_ip_addr, dmac, false);
  3671. }
  3672. }
  3673. err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag,
  3674. ah_info->mac_addr);
  3675. if (err)
  3676. return err;
  3677. ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, ah_info->dest_ip_addr,
  3678. ah_info->ipv4_valid, dmac);
  3679. if (ah_info->dst_arpindex == -1)
  3680. return -EINVAL;
  3681. if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb_vlan_mode)
  3682. ah_info->vlan_tag = 0;
  3683. if (ah_info->vlan_tag < VLAN_N_VID) {
  3684. ah_info->insert_vlan_tag = true;
  3685. ah_info->vlan_tag |=
  3686. rt_tos2priority(ah_info->tc_tos) << VLAN_PRIO_SHIFT;
  3687. }
  3688. return 0;
  3689. }
  3690. /**
  3691. * irdma_ah_exists - Check for existing identical AH
  3692. * @iwdev: irdma device
  3693. * @new_ah: AH to check for
  3694. *
  3695. * returns true if AH is found, false if not found.
  3696. */
  3697. static bool irdma_ah_exists(struct irdma_device *iwdev,
  3698. struct irdma_ah *new_ah)
  3699. {
  3700. struct irdma_ah *ah;
  3701. u32 key = new_ah->sc_ah.ah_info.dest_ip_addr[0] ^
  3702. new_ah->sc_ah.ah_info.dest_ip_addr[1] ^
  3703. new_ah->sc_ah.ah_info.dest_ip_addr[2] ^
  3704. new_ah->sc_ah.ah_info.dest_ip_addr[3];
  3705. hash_for_each_possible(iwdev->ah_hash_tbl, ah, list, key) {
  3706. /* Set ah_valid and ah_id the same so memcmp can work */
  3707. new_ah->sc_ah.ah_info.ah_idx = ah->sc_ah.ah_info.ah_idx;
  3708. new_ah->sc_ah.ah_info.ah_valid = ah->sc_ah.ah_info.ah_valid;
  3709. if (!memcmp(&ah->sc_ah.ah_info, &new_ah->sc_ah.ah_info,
  3710. sizeof(ah->sc_ah.ah_info))) {
  3711. refcount_inc(&ah->refcnt);
  3712. new_ah->parent_ah = ah;
  3713. return true;
  3714. }
  3715. }
  3716. return false;
  3717. }
  3718. /**
  3719. * irdma_destroy_ah - Destroy address handle
  3720. * @ibah: pointer to address handle
  3721. * @ah_flags: flags for sleepable
  3722. */
  3723. static int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags)
  3724. {
  3725. struct irdma_device *iwdev = to_iwdev(ibah->device);
  3726. struct irdma_ah *ah = to_iwah(ibah);
  3727. if ((ah_flags & RDMA_DESTROY_AH_SLEEPABLE) && ah->parent_ah) {
  3728. mutex_lock(&iwdev->ah_tbl_lock);
  3729. if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) {
  3730. mutex_unlock(&iwdev->ah_tbl_lock);
  3731. return 0;
  3732. }
  3733. hash_del(&ah->parent_ah->list);
  3734. kfree(ah->parent_ah);
  3735. mutex_unlock(&iwdev->ah_tbl_lock);
  3736. }
  3737. irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,
  3738. false, NULL, ah);
  3739. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs,
  3740. ah->sc_ah.ah_info.ah_idx);
  3741. return 0;
  3742. }
  3743. /**
  3744. * irdma_create_user_ah - create user address handle
  3745. * @ibah: address handle
  3746. * @attr: address handle attributes
  3747. * @udata: User data
  3748. *
  3749. * returns 0 on success, error otherwise
  3750. */
  3751. static int irdma_create_user_ah(struct ib_ah *ibah,
  3752. struct rdma_ah_init_attr *attr,
  3753. struct ib_udata *udata)
  3754. {
  3755. #define IRDMA_CREATE_AH_MIN_RESP_LEN offsetofend(struct irdma_create_ah_resp, rsvd)
  3756. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  3757. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  3758. struct irdma_create_ah_resp uresp;
  3759. struct irdma_ah *parent_ah;
  3760. int err;
  3761. if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN)
  3762. return -EINVAL;
  3763. err = irdma_setup_ah(ibah, attr);
  3764. if (err)
  3765. return err;
  3766. mutex_lock(&iwdev->ah_tbl_lock);
  3767. if (!irdma_ah_exists(iwdev, ah)) {
  3768. err = irdma_create_hw_ah(iwdev, ah, true);
  3769. if (err) {
  3770. mutex_unlock(&iwdev->ah_tbl_lock);
  3771. return err;
  3772. }
  3773. /* Add new AH to list */
  3774. parent_ah = kmemdup(ah, sizeof(*ah), GFP_KERNEL);
  3775. if (parent_ah) {
  3776. u32 key = parent_ah->sc_ah.ah_info.dest_ip_addr[0] ^
  3777. parent_ah->sc_ah.ah_info.dest_ip_addr[1] ^
  3778. parent_ah->sc_ah.ah_info.dest_ip_addr[2] ^
  3779. parent_ah->sc_ah.ah_info.dest_ip_addr[3];
  3780. ah->parent_ah = parent_ah;
  3781. hash_add(iwdev->ah_hash_tbl, &parent_ah->list, key);
  3782. refcount_set(&parent_ah->refcnt, 1);
  3783. }
  3784. }
  3785. mutex_unlock(&iwdev->ah_tbl_lock);
  3786. uresp.ah_id = ah->sc_ah.ah_info.ah_idx;
  3787. err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen));
  3788. if (err)
  3789. irdma_destroy_ah(ibah, attr->flags);
  3790. return err;
  3791. }
  3792. /**
  3793. * irdma_create_ah - create address handle
  3794. * @ibah: address handle
  3795. * @attr: address handle attributes
  3796. * @udata: NULL
  3797. *
  3798. * returns 0 on success, error otherwise
  3799. */
  3800. static int irdma_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr,
  3801. struct ib_udata *udata)
  3802. {
  3803. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  3804. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  3805. int err;
  3806. err = irdma_setup_ah(ibah, attr);
  3807. if (err)
  3808. return err;
  3809. err = irdma_create_hw_ah(iwdev, ah, attr->flags & RDMA_CREATE_AH_SLEEPABLE);
  3810. return err;
  3811. }
  3812. /**
  3813. * irdma_query_ah - Query address handle
  3814. * @ibah: pointer to address handle
  3815. * @ah_attr: address handle attributes
  3816. */
  3817. static int irdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)
  3818. {
  3819. struct irdma_ah *ah = to_iwah(ibah);
  3820. memset(ah_attr, 0, sizeof(*ah_attr));
  3821. if (ah->av.attrs.ah_flags & IB_AH_GRH) {
  3822. ah_attr->ah_flags = IB_AH_GRH;
  3823. ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label;
  3824. ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos;
  3825. ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl;
  3826. ah_attr->grh.sgid_index = ah->sgid_index;
  3827. memcpy(&ah_attr->grh.dgid, &ah->dgid,
  3828. sizeof(ah_attr->grh.dgid));
  3829. }
  3830. return 0;
  3831. }
  3832. static enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev,
  3833. u32 port_num)
  3834. {
  3835. return IB_LINK_LAYER_ETHERNET;
  3836. }
  3837. static const struct ib_device_ops irdma_roce_dev_ops = {
  3838. .attach_mcast = irdma_attach_mcast,
  3839. .create_ah = irdma_create_ah,
  3840. .create_user_ah = irdma_create_user_ah,
  3841. .destroy_ah = irdma_destroy_ah,
  3842. .detach_mcast = irdma_detach_mcast,
  3843. .get_link_layer = irdma_get_link_layer,
  3844. .get_port_immutable = irdma_roce_port_immutable,
  3845. .modify_qp = irdma_modify_qp_roce,
  3846. .query_ah = irdma_query_ah,
  3847. .query_pkey = irdma_query_pkey,
  3848. };
  3849. static const struct ib_device_ops irdma_iw_dev_ops = {
  3850. .modify_qp = irdma_modify_qp,
  3851. .get_port_immutable = irdma_iw_port_immutable,
  3852. .query_gid = irdma_query_gid,
  3853. };
  3854. static const struct ib_device_ops irdma_dev_ops = {
  3855. .owner = THIS_MODULE,
  3856. .driver_id = RDMA_DRIVER_IRDMA,
  3857. .uverbs_abi_ver = IRDMA_ABI_VER,
  3858. .alloc_hw_port_stats = irdma_alloc_hw_port_stats,
  3859. .alloc_mr = irdma_alloc_mr,
  3860. .alloc_mw = irdma_alloc_mw,
  3861. .alloc_pd = irdma_alloc_pd,
  3862. .alloc_ucontext = irdma_alloc_ucontext,
  3863. .create_cq = irdma_create_cq,
  3864. .create_qp = irdma_create_qp,
  3865. .dealloc_driver = irdma_ib_dealloc_device,
  3866. .dealloc_mw = irdma_dealloc_mw,
  3867. .dealloc_pd = irdma_dealloc_pd,
  3868. .dealloc_ucontext = irdma_dealloc_ucontext,
  3869. .dereg_mr = irdma_dereg_mr,
  3870. .destroy_cq = irdma_destroy_cq,
  3871. .destroy_qp = irdma_destroy_qp,
  3872. .disassociate_ucontext = irdma_disassociate_ucontext,
  3873. .get_dev_fw_str = irdma_get_dev_fw_str,
  3874. .get_dma_mr = irdma_get_dma_mr,
  3875. .get_hw_stats = irdma_get_hw_stats,
  3876. .map_mr_sg = irdma_map_mr_sg,
  3877. .mmap = irdma_mmap,
  3878. .mmap_free = irdma_mmap_free,
  3879. .poll_cq = irdma_poll_cq,
  3880. .post_recv = irdma_post_recv,
  3881. .post_send = irdma_post_send,
  3882. .query_device = irdma_query_device,
  3883. .query_port = irdma_query_port,
  3884. .query_qp = irdma_query_qp,
  3885. .reg_user_mr = irdma_reg_user_mr,
  3886. .req_notify_cq = irdma_req_notify_cq,
  3887. .resize_cq = irdma_resize_cq,
  3888. INIT_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd),
  3889. INIT_RDMA_OBJ_SIZE(ib_ucontext, irdma_ucontext, ibucontext),
  3890. INIT_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah),
  3891. INIT_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq),
  3892. INIT_RDMA_OBJ_SIZE(ib_mw, irdma_mr, ibmw),
  3893. INIT_RDMA_OBJ_SIZE(ib_qp, irdma_qp, ibqp),
  3894. };
  3895. /**
  3896. * irdma_init_roce_device - initialization of roce rdma device
  3897. * @iwdev: irdma device
  3898. */
  3899. static void irdma_init_roce_device(struct irdma_device *iwdev)
  3900. {
  3901. iwdev->ibdev.node_type = RDMA_NODE_IB_CA;
  3902. addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
  3903. iwdev->netdev->dev_addr);
  3904. ib_set_device_ops(&iwdev->ibdev, &irdma_roce_dev_ops);
  3905. }
  3906. /**
  3907. * irdma_init_iw_device - initialization of iwarp rdma device
  3908. * @iwdev: irdma device
  3909. */
  3910. static int irdma_init_iw_device(struct irdma_device *iwdev)
  3911. {
  3912. struct net_device *netdev = iwdev->netdev;
  3913. iwdev->ibdev.node_type = RDMA_NODE_RNIC;
  3914. addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
  3915. netdev->dev_addr);
  3916. iwdev->ibdev.ops.iw_add_ref = irdma_qp_add_ref;
  3917. iwdev->ibdev.ops.iw_rem_ref = irdma_qp_rem_ref;
  3918. iwdev->ibdev.ops.iw_get_qp = irdma_get_qp;
  3919. iwdev->ibdev.ops.iw_connect = irdma_connect;
  3920. iwdev->ibdev.ops.iw_accept = irdma_accept;
  3921. iwdev->ibdev.ops.iw_reject = irdma_reject;
  3922. iwdev->ibdev.ops.iw_create_listen = irdma_create_listen;
  3923. iwdev->ibdev.ops.iw_destroy_listen = irdma_destroy_listen;
  3924. memcpy(iwdev->ibdev.iw_ifname, netdev->name,
  3925. sizeof(iwdev->ibdev.iw_ifname));
  3926. ib_set_device_ops(&iwdev->ibdev, &irdma_iw_dev_ops);
  3927. return 0;
  3928. }
  3929. /**
  3930. * irdma_init_rdma_device - initialization of rdma device
  3931. * @iwdev: irdma device
  3932. */
  3933. static int irdma_init_rdma_device(struct irdma_device *iwdev)
  3934. {
  3935. struct pci_dev *pcidev = iwdev->rf->pcidev;
  3936. int ret;
  3937. if (iwdev->roce_mode) {
  3938. irdma_init_roce_device(iwdev);
  3939. } else {
  3940. ret = irdma_init_iw_device(iwdev);
  3941. if (ret)
  3942. return ret;
  3943. }
  3944. iwdev->ibdev.phys_port_cnt = 1;
  3945. iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count;
  3946. iwdev->ibdev.dev.parent = &pcidev->dev;
  3947. ib_set_device_ops(&iwdev->ibdev, &irdma_dev_ops);
  3948. return 0;
  3949. }
  3950. /**
  3951. * irdma_port_ibevent - indicate port event
  3952. * @iwdev: irdma device
  3953. */
  3954. void irdma_port_ibevent(struct irdma_device *iwdev)
  3955. {
  3956. struct ib_event event;
  3957. event.device = &iwdev->ibdev;
  3958. event.element.port_num = 1;
  3959. event.event =
  3960. iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  3961. ib_dispatch_event(&event);
  3962. }
  3963. /**
  3964. * irdma_ib_unregister_device - unregister rdma device from IB
  3965. * core
  3966. * @iwdev: irdma device
  3967. */
  3968. void irdma_ib_unregister_device(struct irdma_device *iwdev)
  3969. {
  3970. iwdev->iw_status = 0;
  3971. irdma_port_ibevent(iwdev);
  3972. ib_unregister_device(&iwdev->ibdev);
  3973. }
  3974. /**
  3975. * irdma_ib_register_device - register irdma device to IB core
  3976. * @iwdev: irdma device
  3977. */
  3978. int irdma_ib_register_device(struct irdma_device *iwdev)
  3979. {
  3980. int ret;
  3981. ret = irdma_init_rdma_device(iwdev);
  3982. if (ret)
  3983. return ret;
  3984. ret = ib_device_set_netdev(&iwdev->ibdev, iwdev->netdev, 1);
  3985. if (ret)
  3986. goto error;
  3987. dma_set_max_seg_size(iwdev->rf->hw.device, UINT_MAX);
  3988. ret = ib_register_device(&iwdev->ibdev, "irdma%d", iwdev->rf->hw.device);
  3989. if (ret)
  3990. goto error;
  3991. iwdev->iw_status = 1;
  3992. irdma_port_ibevent(iwdev);
  3993. return 0;
  3994. error:
  3995. if (ret)
  3996. ibdev_dbg(&iwdev->ibdev, "VERBS: Register RDMA device fail\n");
  3997. return ret;
  3998. }
  3999. /**
  4000. * irdma_ib_dealloc_device
  4001. * @ibdev: ib device
  4002. *
  4003. * callback from ibdev dealloc_driver to deallocate resources
  4004. * unber irdma device
  4005. */
  4006. void irdma_ib_dealloc_device(struct ib_device *ibdev)
  4007. {
  4008. struct irdma_device *iwdev = to_iwdev(ibdev);
  4009. irdma_rt_deinit_hw(iwdev);
  4010. irdma_ctrl_deinit_hw(iwdev->rf);
  4011. kfree(iwdev->rf);
  4012. }