utils.c 70 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656
  1. // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
  2. /* Copyright (c) 2015 - 2021 Intel Corporation */
  3. #include "main.h"
  4. /**
  5. * irdma_arp_table -manage arp table
  6. * @rf: RDMA PCI function
  7. * @ip_addr: ip address for device
  8. * @ipv4: IPv4 flag
  9. * @mac_addr: mac address ptr
  10. * @action: modify, delete or add
  11. */
  12. int irdma_arp_table(struct irdma_pci_f *rf, u32 *ip_addr, bool ipv4,
  13. const u8 *mac_addr, u32 action)
  14. {
  15. unsigned long flags;
  16. int arp_index;
  17. u32 ip[4] = {};
  18. if (ipv4)
  19. ip[0] = *ip_addr;
  20. else
  21. memcpy(ip, ip_addr, sizeof(ip));
  22. spin_lock_irqsave(&rf->arp_lock, flags);
  23. for (arp_index = 0; (u32)arp_index < rf->arp_table_size; arp_index++) {
  24. if (!memcmp(rf->arp_table[arp_index].ip_addr, ip, sizeof(ip)))
  25. break;
  26. }
  27. switch (action) {
  28. case IRDMA_ARP_ADD:
  29. if (arp_index != rf->arp_table_size) {
  30. arp_index = -1;
  31. break;
  32. }
  33. arp_index = 0;
  34. if (irdma_alloc_rsrc(rf, rf->allocated_arps, rf->arp_table_size,
  35. (u32 *)&arp_index, &rf->next_arp_index)) {
  36. arp_index = -1;
  37. break;
  38. }
  39. memcpy(rf->arp_table[arp_index].ip_addr, ip,
  40. sizeof(rf->arp_table[arp_index].ip_addr));
  41. ether_addr_copy(rf->arp_table[arp_index].mac_addr, mac_addr);
  42. break;
  43. case IRDMA_ARP_RESOLVE:
  44. if (arp_index == rf->arp_table_size)
  45. arp_index = -1;
  46. break;
  47. case IRDMA_ARP_DELETE:
  48. if (arp_index == rf->arp_table_size) {
  49. arp_index = -1;
  50. break;
  51. }
  52. memset(rf->arp_table[arp_index].ip_addr, 0,
  53. sizeof(rf->arp_table[arp_index].ip_addr));
  54. eth_zero_addr(rf->arp_table[arp_index].mac_addr);
  55. irdma_free_rsrc(rf, rf->allocated_arps, arp_index);
  56. break;
  57. default:
  58. arp_index = -1;
  59. break;
  60. }
  61. spin_unlock_irqrestore(&rf->arp_lock, flags);
  62. return arp_index;
  63. }
  64. /**
  65. * irdma_add_arp - add a new arp entry if needed
  66. * @rf: RDMA function
  67. * @ip: IP address
  68. * @ipv4: IPv4 flag
  69. * @mac: MAC address
  70. */
  71. int irdma_add_arp(struct irdma_pci_f *rf, u32 *ip, bool ipv4, const u8 *mac)
  72. {
  73. int arpidx;
  74. arpidx = irdma_arp_table(rf, &ip[0], ipv4, NULL, IRDMA_ARP_RESOLVE);
  75. if (arpidx >= 0) {
  76. if (ether_addr_equal(rf->arp_table[arpidx].mac_addr, mac))
  77. return arpidx;
  78. irdma_manage_arp_cache(rf, rf->arp_table[arpidx].mac_addr, ip,
  79. ipv4, IRDMA_ARP_DELETE);
  80. }
  81. irdma_manage_arp_cache(rf, mac, ip, ipv4, IRDMA_ARP_ADD);
  82. return irdma_arp_table(rf, ip, ipv4, NULL, IRDMA_ARP_RESOLVE);
  83. }
  84. /**
  85. * wr32 - write 32 bits to hw register
  86. * @hw: hardware information including registers
  87. * @reg: register offset
  88. * @val: value to write to register
  89. */
  90. inline void wr32(struct irdma_hw *hw, u32 reg, u32 val)
  91. {
  92. writel(val, hw->hw_addr + reg);
  93. }
  94. /**
  95. * rd32 - read a 32 bit hw register
  96. * @hw: hardware information including registers
  97. * @reg: register offset
  98. *
  99. * Return value of register content
  100. */
  101. inline u32 rd32(struct irdma_hw *hw, u32 reg)
  102. {
  103. return readl(hw->hw_addr + reg);
  104. }
  105. /**
  106. * rd64 - read a 64 bit hw register
  107. * @hw: hardware information including registers
  108. * @reg: register offset
  109. *
  110. * Return value of register content
  111. */
  112. inline u64 rd64(struct irdma_hw *hw, u32 reg)
  113. {
  114. return readq(hw->hw_addr + reg);
  115. }
  116. static void irdma_gid_change_event(struct ib_device *ibdev)
  117. {
  118. struct ib_event ib_event;
  119. ib_event.event = IB_EVENT_GID_CHANGE;
  120. ib_event.device = ibdev;
  121. ib_event.element.port_num = 1;
  122. ib_dispatch_event(&ib_event);
  123. }
  124. /**
  125. * irdma_inetaddr_event - system notifier for ipv4 addr events
  126. * @notifier: not used
  127. * @event: event for notifier
  128. * @ptr: if address
  129. */
  130. int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event,
  131. void *ptr)
  132. {
  133. struct in_ifaddr *ifa = ptr;
  134. struct net_device *real_dev, *netdev = ifa->ifa_dev->dev;
  135. struct irdma_device *iwdev;
  136. struct ib_device *ibdev;
  137. u32 local_ipaddr;
  138. real_dev = rdma_vlan_dev_real_dev(netdev);
  139. if (!real_dev)
  140. real_dev = netdev;
  141. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  142. if (!ibdev)
  143. return NOTIFY_DONE;
  144. iwdev = to_iwdev(ibdev);
  145. local_ipaddr = ntohl(ifa->ifa_address);
  146. ibdev_dbg(&iwdev->ibdev,
  147. "DEV: netdev %p event %lu local_ip=%pI4 MAC=%pM\n", real_dev,
  148. event, &local_ipaddr, real_dev->dev_addr);
  149. switch (event) {
  150. case NETDEV_DOWN:
  151. irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
  152. &local_ipaddr, true, IRDMA_ARP_DELETE);
  153. irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, false);
  154. irdma_gid_change_event(&iwdev->ibdev);
  155. break;
  156. case NETDEV_UP:
  157. case NETDEV_CHANGEADDR:
  158. irdma_add_arp(iwdev->rf, &local_ipaddr, true, real_dev->dev_addr);
  159. irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, true);
  160. irdma_gid_change_event(&iwdev->ibdev);
  161. break;
  162. default:
  163. break;
  164. }
  165. ib_device_put(ibdev);
  166. return NOTIFY_DONE;
  167. }
  168. /**
  169. * irdma_inet6addr_event - system notifier for ipv6 addr events
  170. * @notifier: not used
  171. * @event: event for notifier
  172. * @ptr: if address
  173. */
  174. int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event,
  175. void *ptr)
  176. {
  177. struct inet6_ifaddr *ifa = ptr;
  178. struct net_device *real_dev, *netdev = ifa->idev->dev;
  179. struct irdma_device *iwdev;
  180. struct ib_device *ibdev;
  181. u32 local_ipaddr6[4];
  182. real_dev = rdma_vlan_dev_real_dev(netdev);
  183. if (!real_dev)
  184. real_dev = netdev;
  185. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  186. if (!ibdev)
  187. return NOTIFY_DONE;
  188. iwdev = to_iwdev(ibdev);
  189. irdma_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);
  190. ibdev_dbg(&iwdev->ibdev,
  191. "DEV: netdev %p event %lu local_ip=%pI6 MAC=%pM\n", real_dev,
  192. event, local_ipaddr6, real_dev->dev_addr);
  193. switch (event) {
  194. case NETDEV_DOWN:
  195. irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
  196. local_ipaddr6, false, IRDMA_ARP_DELETE);
  197. irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, false);
  198. irdma_gid_change_event(&iwdev->ibdev);
  199. break;
  200. case NETDEV_UP:
  201. case NETDEV_CHANGEADDR:
  202. irdma_add_arp(iwdev->rf, local_ipaddr6, false,
  203. real_dev->dev_addr);
  204. irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, true);
  205. irdma_gid_change_event(&iwdev->ibdev);
  206. break;
  207. default:
  208. break;
  209. }
  210. ib_device_put(ibdev);
  211. return NOTIFY_DONE;
  212. }
  213. /**
  214. * irdma_net_event - system notifier for net events
  215. * @notifier: not used
  216. * @event: event for notifier
  217. * @ptr: neighbor
  218. */
  219. int irdma_net_event(struct notifier_block *notifier, unsigned long event,
  220. void *ptr)
  221. {
  222. struct neighbour *neigh = ptr;
  223. struct net_device *real_dev, *netdev = (struct net_device *)neigh->dev;
  224. struct irdma_device *iwdev;
  225. struct ib_device *ibdev;
  226. __be32 *p;
  227. u32 local_ipaddr[4] = {};
  228. bool ipv4 = true;
  229. switch (event) {
  230. case NETEVENT_NEIGH_UPDATE:
  231. real_dev = rdma_vlan_dev_real_dev(netdev);
  232. if (!real_dev)
  233. real_dev = netdev;
  234. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  235. if (!ibdev)
  236. return NOTIFY_DONE;
  237. iwdev = to_iwdev(ibdev);
  238. p = (__be32 *)neigh->primary_key;
  239. if (neigh->tbl->family == AF_INET6) {
  240. ipv4 = false;
  241. irdma_copy_ip_ntohl(local_ipaddr, p);
  242. } else {
  243. local_ipaddr[0] = ntohl(*p);
  244. }
  245. ibdev_dbg(&iwdev->ibdev,
  246. "DEV: netdev %p state %d local_ip=%pI4 MAC=%pM\n",
  247. iwdev->netdev, neigh->nud_state, local_ipaddr,
  248. neigh->ha);
  249. if (neigh->nud_state & NUD_VALID)
  250. irdma_add_arp(iwdev->rf, local_ipaddr, ipv4, neigh->ha);
  251. else
  252. irdma_manage_arp_cache(iwdev->rf, neigh->ha,
  253. local_ipaddr, ipv4,
  254. IRDMA_ARP_DELETE);
  255. ib_device_put(ibdev);
  256. break;
  257. default:
  258. break;
  259. }
  260. return NOTIFY_DONE;
  261. }
  262. /**
  263. * irdma_netdevice_event - system notifier for netdev events
  264. * @notifier: not used
  265. * @event: event for notifier
  266. * @ptr: netdev
  267. */
  268. int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event,
  269. void *ptr)
  270. {
  271. struct irdma_device *iwdev;
  272. struct ib_device *ibdev;
  273. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  274. ibdev = ib_device_get_by_netdev(netdev, RDMA_DRIVER_IRDMA);
  275. if (!ibdev)
  276. return NOTIFY_DONE;
  277. iwdev = to_iwdev(ibdev);
  278. iwdev->iw_status = 1;
  279. switch (event) {
  280. case NETDEV_DOWN:
  281. iwdev->iw_status = 0;
  282. fallthrough;
  283. case NETDEV_UP:
  284. irdma_port_ibevent(iwdev);
  285. break;
  286. default:
  287. break;
  288. }
  289. ib_device_put(ibdev);
  290. return NOTIFY_DONE;
  291. }
  292. /**
  293. * irdma_add_ipv6_addr - add ipv6 address to the hw arp table
  294. * @iwdev: irdma device
  295. */
  296. static void irdma_add_ipv6_addr(struct irdma_device *iwdev)
  297. {
  298. struct net_device *ip_dev;
  299. struct inet6_dev *idev;
  300. struct inet6_ifaddr *ifp, *tmp;
  301. u32 local_ipaddr6[4];
  302. rcu_read_lock();
  303. for_each_netdev_rcu (&init_net, ip_dev) {
  304. if (((rdma_vlan_dev_vlan_id(ip_dev) < 0xFFFF &&
  305. rdma_vlan_dev_real_dev(ip_dev) == iwdev->netdev) ||
  306. ip_dev == iwdev->netdev) &&
  307. (READ_ONCE(ip_dev->flags) & IFF_UP)) {
  308. idev = __in6_dev_get(ip_dev);
  309. if (!idev) {
  310. ibdev_err(&iwdev->ibdev, "ipv6 inet device not found\n");
  311. break;
  312. }
  313. list_for_each_entry_safe (ifp, tmp, &idev->addr_list,
  314. if_list) {
  315. ibdev_dbg(&iwdev->ibdev,
  316. "INIT: IP=%pI6, vlan_id=%d, MAC=%pM\n",
  317. &ifp->addr,
  318. rdma_vlan_dev_vlan_id(ip_dev),
  319. ip_dev->dev_addr);
  320. irdma_copy_ip_ntohl(local_ipaddr6,
  321. ifp->addr.in6_u.u6_addr32);
  322. irdma_manage_arp_cache(iwdev->rf,
  323. ip_dev->dev_addr,
  324. local_ipaddr6, false,
  325. IRDMA_ARP_ADD);
  326. }
  327. }
  328. }
  329. rcu_read_unlock();
  330. }
  331. /**
  332. * irdma_add_ipv4_addr - add ipv4 address to the hw arp table
  333. * @iwdev: irdma device
  334. */
  335. static void irdma_add_ipv4_addr(struct irdma_device *iwdev)
  336. {
  337. struct net_device *dev;
  338. struct in_device *idev;
  339. u32 ip_addr;
  340. rcu_read_lock();
  341. for_each_netdev_rcu (&init_net, dev) {
  342. if (((rdma_vlan_dev_vlan_id(dev) < 0xFFFF &&
  343. rdma_vlan_dev_real_dev(dev) == iwdev->netdev) ||
  344. dev == iwdev->netdev) && (READ_ONCE(dev->flags) & IFF_UP)) {
  345. const struct in_ifaddr *ifa;
  346. idev = __in_dev_get_rcu(dev);
  347. if (!idev)
  348. continue;
  349. in_dev_for_each_ifa_rcu(ifa, idev) {
  350. ibdev_dbg(&iwdev->ibdev, "CM: IP=%pI4, vlan_id=%d, MAC=%pM\n",
  351. &ifa->ifa_address, rdma_vlan_dev_vlan_id(dev),
  352. dev->dev_addr);
  353. ip_addr = ntohl(ifa->ifa_address);
  354. irdma_manage_arp_cache(iwdev->rf, dev->dev_addr,
  355. &ip_addr, true,
  356. IRDMA_ARP_ADD);
  357. }
  358. }
  359. }
  360. rcu_read_unlock();
  361. }
  362. /**
  363. * irdma_add_ip - add ip addresses
  364. * @iwdev: irdma device
  365. *
  366. * Add ipv4/ipv6 addresses to the arp cache
  367. */
  368. void irdma_add_ip(struct irdma_device *iwdev)
  369. {
  370. irdma_add_ipv4_addr(iwdev);
  371. irdma_add_ipv6_addr(iwdev);
  372. }
  373. /**
  374. * irdma_alloc_and_get_cqp_request - get cqp struct
  375. * @cqp: device cqp ptr
  376. * @wait: cqp to be used in wait mode
  377. */
  378. struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp,
  379. bool wait)
  380. {
  381. struct irdma_cqp_request *cqp_request = NULL;
  382. unsigned long flags;
  383. spin_lock_irqsave(&cqp->req_lock, flags);
  384. if (!list_empty(&cqp->cqp_avail_reqs)) {
  385. cqp_request = list_first_entry(&cqp->cqp_avail_reqs,
  386. struct irdma_cqp_request, list);
  387. list_del_init(&cqp_request->list);
  388. }
  389. spin_unlock_irqrestore(&cqp->req_lock, flags);
  390. if (!cqp_request) {
  391. cqp_request = kzalloc(sizeof(*cqp_request), GFP_ATOMIC);
  392. if (cqp_request) {
  393. cqp_request->dynamic = true;
  394. if (wait)
  395. init_waitqueue_head(&cqp_request->waitq);
  396. }
  397. }
  398. if (!cqp_request) {
  399. ibdev_dbg(to_ibdev(cqp->sc_cqp.dev), "ERR: CQP Request Fail: No Memory");
  400. return NULL;
  401. }
  402. cqp_request->waiting = wait;
  403. refcount_set(&cqp_request->refcnt, 1);
  404. memset(&cqp_request->compl_info, 0, sizeof(cqp_request->compl_info));
  405. return cqp_request;
  406. }
  407. /**
  408. * irdma_get_cqp_request - increase refcount for cqp_request
  409. * @cqp_request: pointer to cqp_request instance
  410. */
  411. static inline void irdma_get_cqp_request(struct irdma_cqp_request *cqp_request)
  412. {
  413. refcount_inc(&cqp_request->refcnt);
  414. }
  415. /**
  416. * irdma_free_cqp_request - free cqp request
  417. * @cqp: cqp ptr
  418. * @cqp_request: to be put back in cqp list
  419. */
  420. void irdma_free_cqp_request(struct irdma_cqp *cqp,
  421. struct irdma_cqp_request *cqp_request)
  422. {
  423. unsigned long flags;
  424. if (cqp_request->dynamic) {
  425. kfree(cqp_request);
  426. } else {
  427. WRITE_ONCE(cqp_request->request_done, false);
  428. cqp_request->callback_fcn = NULL;
  429. cqp_request->waiting = false;
  430. spin_lock_irqsave(&cqp->req_lock, flags);
  431. list_add_tail(&cqp_request->list, &cqp->cqp_avail_reqs);
  432. spin_unlock_irqrestore(&cqp->req_lock, flags);
  433. }
  434. wake_up(&cqp->remove_wq);
  435. }
  436. /**
  437. * irdma_put_cqp_request - dec ref count and free if 0
  438. * @cqp: cqp ptr
  439. * @cqp_request: to be put back in cqp list
  440. */
  441. void irdma_put_cqp_request(struct irdma_cqp *cqp,
  442. struct irdma_cqp_request *cqp_request)
  443. {
  444. if (refcount_dec_and_test(&cqp_request->refcnt))
  445. irdma_free_cqp_request(cqp, cqp_request);
  446. }
  447. /**
  448. * irdma_free_pending_cqp_request -free pending cqp request objs
  449. * @cqp: cqp ptr
  450. * @cqp_request: to be put back in cqp list
  451. */
  452. static void
  453. irdma_free_pending_cqp_request(struct irdma_cqp *cqp,
  454. struct irdma_cqp_request *cqp_request)
  455. {
  456. if (cqp_request->waiting) {
  457. cqp_request->compl_info.error = true;
  458. WRITE_ONCE(cqp_request->request_done, true);
  459. wake_up(&cqp_request->waitq);
  460. }
  461. wait_event_timeout(cqp->remove_wq,
  462. refcount_read(&cqp_request->refcnt) == 1, 1000);
  463. irdma_put_cqp_request(cqp, cqp_request);
  464. }
  465. /**
  466. * irdma_cleanup_pending_cqp_op - clean-up cqp with no
  467. * completions
  468. * @rf: RDMA PCI function
  469. */
  470. void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf)
  471. {
  472. struct irdma_sc_dev *dev = &rf->sc_dev;
  473. struct irdma_cqp *cqp = &rf->cqp;
  474. struct irdma_cqp_request *cqp_request = NULL;
  475. struct cqp_cmds_info *pcmdinfo = NULL;
  476. u32 i, pending_work, wqe_idx;
  477. pending_work = IRDMA_RING_USED_QUANTA(cqp->sc_cqp.sq_ring);
  478. wqe_idx = IRDMA_RING_CURRENT_TAIL(cqp->sc_cqp.sq_ring);
  479. for (i = 0; i < pending_work; i++) {
  480. cqp_request = (struct irdma_cqp_request *)(unsigned long)
  481. cqp->scratch_array[wqe_idx];
  482. if (cqp_request)
  483. irdma_free_pending_cqp_request(cqp, cqp_request);
  484. wqe_idx = (wqe_idx + 1) % IRDMA_RING_SIZE(cqp->sc_cqp.sq_ring);
  485. }
  486. while (!list_empty(&dev->cqp_cmd_head)) {
  487. pcmdinfo = irdma_remove_cqp_head(dev);
  488. cqp_request =
  489. container_of(pcmdinfo, struct irdma_cqp_request, info);
  490. if (cqp_request)
  491. irdma_free_pending_cqp_request(cqp, cqp_request);
  492. }
  493. }
  494. /**
  495. * irdma_wait_event - wait for completion
  496. * @rf: RDMA PCI function
  497. * @cqp_request: cqp request to wait
  498. */
  499. static int irdma_wait_event(struct irdma_pci_f *rf,
  500. struct irdma_cqp_request *cqp_request)
  501. {
  502. struct irdma_cqp_timeout cqp_timeout = {};
  503. bool cqp_error = false;
  504. int err_code = 0;
  505. cqp_timeout.compl_cqp_cmds = atomic64_read(&rf->sc_dev.cqp->completed_ops);
  506. do {
  507. irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
  508. if (wait_event_timeout(cqp_request->waitq,
  509. READ_ONCE(cqp_request->request_done),
  510. msecs_to_jiffies(CQP_COMPL_WAIT_TIME_MS)))
  511. break;
  512. irdma_check_cqp_progress(&cqp_timeout, &rf->sc_dev);
  513. if (cqp_timeout.count < CQP_TIMEOUT_THRESHOLD)
  514. continue;
  515. if (!rf->reset) {
  516. rf->reset = true;
  517. rf->gen_ops.request_reset(rf);
  518. }
  519. return -ETIMEDOUT;
  520. } while (1);
  521. cqp_error = cqp_request->compl_info.error;
  522. if (cqp_error) {
  523. err_code = -EIO;
  524. if (cqp_request->compl_info.maj_err_code == 0xFFFF) {
  525. if (cqp_request->compl_info.min_err_code == 0x8002)
  526. err_code = -EBUSY;
  527. else if (cqp_request->compl_info.min_err_code == 0x8029) {
  528. if (!rf->reset) {
  529. rf->reset = true;
  530. rf->gen_ops.request_reset(rf);
  531. }
  532. }
  533. }
  534. }
  535. return err_code;
  536. }
  537. static const char *const irdma_cqp_cmd_names[IRDMA_MAX_CQP_OPS] = {
  538. [IRDMA_OP_CEQ_DESTROY] = "Destroy CEQ Cmd",
  539. [IRDMA_OP_AEQ_DESTROY] = "Destroy AEQ Cmd",
  540. [IRDMA_OP_DELETE_ARP_CACHE_ENTRY] = "Delete ARP Cache Cmd",
  541. [IRDMA_OP_MANAGE_APBVT_ENTRY] = "Manage APBV Table Entry Cmd",
  542. [IRDMA_OP_CEQ_CREATE] = "CEQ Create Cmd",
  543. [IRDMA_OP_AEQ_CREATE] = "AEQ Destroy Cmd",
  544. [IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY] = "Manage Quad Hash Table Entry Cmd",
  545. [IRDMA_OP_QP_MODIFY] = "Modify QP Cmd",
  546. [IRDMA_OP_QP_UPLOAD_CONTEXT] = "Upload Context Cmd",
  547. [IRDMA_OP_CQ_CREATE] = "Create CQ Cmd",
  548. [IRDMA_OP_CQ_DESTROY] = "Destroy CQ Cmd",
  549. [IRDMA_OP_QP_CREATE] = "Create QP Cmd",
  550. [IRDMA_OP_QP_DESTROY] = "Destroy QP Cmd",
  551. [IRDMA_OP_ALLOC_STAG] = "Allocate STag Cmd",
  552. [IRDMA_OP_MR_REG_NON_SHARED] = "Register Non-Shared MR Cmd",
  553. [IRDMA_OP_DEALLOC_STAG] = "Deallocate STag Cmd",
  554. [IRDMA_OP_MW_ALLOC] = "Allocate Memory Window Cmd",
  555. [IRDMA_OP_QP_FLUSH_WQES] = "Flush QP Cmd",
  556. [IRDMA_OP_ADD_ARP_CACHE_ENTRY] = "Add ARP Cache Cmd",
  557. [IRDMA_OP_MANAGE_PUSH_PAGE] = "Manage Push Page Cmd",
  558. [IRDMA_OP_UPDATE_PE_SDS] = "Update PE SDs Cmd",
  559. [IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE] = "Manage HMC PM Function Table Cmd",
  560. [IRDMA_OP_SUSPEND] = "Suspend QP Cmd",
  561. [IRDMA_OP_RESUME] = "Resume QP Cmd",
  562. [IRDMA_OP_MANAGE_VF_PBLE_BP] = "Manage VF PBLE Backing Pages Cmd",
  563. [IRDMA_OP_QUERY_FPM_VAL] = "Query FPM Values Cmd",
  564. [IRDMA_OP_COMMIT_FPM_VAL] = "Commit FPM Values Cmd",
  565. [IRDMA_OP_AH_CREATE] = "Create Address Handle Cmd",
  566. [IRDMA_OP_AH_MODIFY] = "Modify Address Handle Cmd",
  567. [IRDMA_OP_AH_DESTROY] = "Destroy Address Handle Cmd",
  568. [IRDMA_OP_MC_CREATE] = "Create Multicast Group Cmd",
  569. [IRDMA_OP_MC_DESTROY] = "Destroy Multicast Group Cmd",
  570. [IRDMA_OP_MC_MODIFY] = "Modify Multicast Group Cmd",
  571. [IRDMA_OP_STATS_ALLOCATE] = "Add Statistics Instance Cmd",
  572. [IRDMA_OP_STATS_FREE] = "Free Statistics Instance Cmd",
  573. [IRDMA_OP_STATS_GATHER] = "Gather Statistics Cmd",
  574. [IRDMA_OP_WS_ADD_NODE] = "Add Work Scheduler Node Cmd",
  575. [IRDMA_OP_WS_MODIFY_NODE] = "Modify Work Scheduler Node Cmd",
  576. [IRDMA_OP_WS_DELETE_NODE] = "Delete Work Scheduler Node Cmd",
  577. [IRDMA_OP_SET_UP_MAP] = "Set UP-UP Mapping Cmd",
  578. [IRDMA_OP_GEN_AE] = "Generate AE Cmd",
  579. [IRDMA_OP_QUERY_RDMA_FEATURES] = "RDMA Get Features Cmd",
  580. [IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY] = "Allocate Local MAC Entry Cmd",
  581. [IRDMA_OP_ADD_LOCAL_MAC_ENTRY] = "Add Local MAC Entry Cmd",
  582. [IRDMA_OP_DELETE_LOCAL_MAC_ENTRY] = "Delete Local MAC Entry Cmd",
  583. [IRDMA_OP_CQ_MODIFY] = "CQ Modify Cmd",
  584. };
  585. static const struct irdma_cqp_err_info irdma_noncrit_err_list[] = {
  586. {0xffff, 0x8002, "Invalid State"},
  587. {0xffff, 0x8006, "Flush No Wqe Pending"},
  588. {0xffff, 0x8007, "Modify QP Bad Close"},
  589. {0xffff, 0x8009, "LLP Closed"},
  590. {0xffff, 0x800a, "Reset Not Sent"}
  591. };
  592. /**
  593. * irdma_cqp_crit_err - check if CQP error is critical
  594. * @dev: pointer to dev structure
  595. * @cqp_cmd: code for last CQP operation
  596. * @maj_err_code: major error code
  597. * @min_err_code: minot error code
  598. */
  599. bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd,
  600. u16 maj_err_code, u16 min_err_code)
  601. {
  602. int i;
  603. for (i = 0; i < ARRAY_SIZE(irdma_noncrit_err_list); ++i) {
  604. if (maj_err_code == irdma_noncrit_err_list[i].maj &&
  605. min_err_code == irdma_noncrit_err_list[i].min) {
  606. ibdev_dbg(to_ibdev(dev),
  607. "CQP: [%s Error][%s] maj=0x%x min=0x%x\n",
  608. irdma_noncrit_err_list[i].desc,
  609. irdma_cqp_cmd_names[cqp_cmd], maj_err_code,
  610. min_err_code);
  611. return false;
  612. }
  613. }
  614. return true;
  615. }
  616. /**
  617. * irdma_handle_cqp_op - process cqp command
  618. * @rf: RDMA PCI function
  619. * @cqp_request: cqp request to process
  620. */
  621. int irdma_handle_cqp_op(struct irdma_pci_f *rf,
  622. struct irdma_cqp_request *cqp_request)
  623. {
  624. struct irdma_sc_dev *dev = &rf->sc_dev;
  625. struct cqp_cmds_info *info = &cqp_request->info;
  626. int status;
  627. bool put_cqp_request = true;
  628. if (rf->reset)
  629. return -EBUSY;
  630. irdma_get_cqp_request(cqp_request);
  631. status = irdma_process_cqp_cmd(dev, info);
  632. if (status)
  633. goto err;
  634. if (cqp_request->waiting) {
  635. put_cqp_request = false;
  636. status = irdma_wait_event(rf, cqp_request);
  637. if (status)
  638. goto err;
  639. }
  640. return 0;
  641. err:
  642. if (irdma_cqp_crit_err(dev, info->cqp_cmd,
  643. cqp_request->compl_info.maj_err_code,
  644. cqp_request->compl_info.min_err_code))
  645. ibdev_err(&rf->iwdev->ibdev,
  646. "[%s Error][op_code=%d] status=%d waiting=%d completion_err=%d maj=0x%x min=0x%x\n",
  647. irdma_cqp_cmd_names[info->cqp_cmd], info->cqp_cmd, status, cqp_request->waiting,
  648. cqp_request->compl_info.error, cqp_request->compl_info.maj_err_code,
  649. cqp_request->compl_info.min_err_code);
  650. if (put_cqp_request)
  651. irdma_put_cqp_request(&rf->cqp, cqp_request);
  652. return status;
  653. }
  654. void irdma_qp_add_ref(struct ib_qp *ibqp)
  655. {
  656. struct irdma_qp *iwqp = (struct irdma_qp *)ibqp;
  657. refcount_inc(&iwqp->refcnt);
  658. }
  659. void irdma_qp_rem_ref(struct ib_qp *ibqp)
  660. {
  661. struct irdma_qp *iwqp = to_iwqp(ibqp);
  662. struct irdma_device *iwdev = iwqp->iwdev;
  663. u32 qp_num;
  664. unsigned long flags;
  665. spin_lock_irqsave(&iwdev->rf->qptable_lock, flags);
  666. if (!refcount_dec_and_test(&iwqp->refcnt)) {
  667. spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);
  668. return;
  669. }
  670. qp_num = iwqp->ibqp.qp_num;
  671. iwdev->rf->qp_table[qp_num] = NULL;
  672. spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);
  673. complete(&iwqp->free_qp);
  674. }
  675. struct ib_device *to_ibdev(struct irdma_sc_dev *dev)
  676. {
  677. return &(container_of(dev, struct irdma_pci_f, sc_dev))->iwdev->ibdev;
  678. }
  679. /**
  680. * irdma_get_qp - get qp address
  681. * @device: iwarp device
  682. * @qpn: qp number
  683. */
  684. struct ib_qp *irdma_get_qp(struct ib_device *device, int qpn)
  685. {
  686. struct irdma_device *iwdev = to_iwdev(device);
  687. if (qpn < IW_FIRST_QPN || qpn >= iwdev->rf->max_qp)
  688. return NULL;
  689. return &iwdev->rf->qp_table[qpn]->ibqp;
  690. }
  691. /**
  692. * irdma_remove_cqp_head - return head entry and remove
  693. * @dev: device
  694. */
  695. void *irdma_remove_cqp_head(struct irdma_sc_dev *dev)
  696. {
  697. struct list_head *entry;
  698. struct list_head *list = &dev->cqp_cmd_head;
  699. if (list_empty(list))
  700. return NULL;
  701. entry = list->next;
  702. list_del(entry);
  703. return entry;
  704. }
  705. /**
  706. * irdma_cqp_sds_cmd - create cqp command for sd
  707. * @dev: hardware control device structure
  708. * @sdinfo: information for sd cqp
  709. *
  710. */
  711. int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
  712. struct irdma_update_sds_info *sdinfo)
  713. {
  714. struct irdma_cqp_request *cqp_request;
  715. struct cqp_cmds_info *cqp_info;
  716. struct irdma_pci_f *rf = dev_to_rf(dev);
  717. int status;
  718. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  719. if (!cqp_request)
  720. return -ENOMEM;
  721. cqp_info = &cqp_request->info;
  722. memcpy(&cqp_info->in.u.update_pe_sds.info, sdinfo,
  723. sizeof(cqp_info->in.u.update_pe_sds.info));
  724. cqp_info->cqp_cmd = IRDMA_OP_UPDATE_PE_SDS;
  725. cqp_info->post_sq = 1;
  726. cqp_info->in.u.update_pe_sds.dev = dev;
  727. cqp_info->in.u.update_pe_sds.scratch = (uintptr_t)cqp_request;
  728. status = irdma_handle_cqp_op(rf, cqp_request);
  729. irdma_put_cqp_request(&rf->cqp, cqp_request);
  730. return status;
  731. }
  732. /**
  733. * irdma_cqp_qp_suspend_resume - cqp command for suspend/resume
  734. * @qp: hardware control qp
  735. * @op: suspend or resume
  736. */
  737. int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 op)
  738. {
  739. struct irdma_sc_dev *dev = qp->dev;
  740. struct irdma_cqp_request *cqp_request;
  741. struct irdma_sc_cqp *cqp = dev->cqp;
  742. struct cqp_cmds_info *cqp_info;
  743. struct irdma_pci_f *rf = dev_to_rf(dev);
  744. int status;
  745. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
  746. if (!cqp_request)
  747. return -ENOMEM;
  748. cqp_info = &cqp_request->info;
  749. cqp_info->cqp_cmd = op;
  750. cqp_info->in.u.suspend_resume.cqp = cqp;
  751. cqp_info->in.u.suspend_resume.qp = qp;
  752. cqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request;
  753. status = irdma_handle_cqp_op(rf, cqp_request);
  754. irdma_put_cqp_request(&rf->cqp, cqp_request);
  755. return status;
  756. }
  757. /**
  758. * irdma_term_modify_qp - modify qp for term message
  759. * @qp: hardware control qp
  760. * @next_state: qp's next state
  761. * @term: terminate code
  762. * @term_len: length
  763. */
  764. void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,
  765. u8 term_len)
  766. {
  767. struct irdma_qp *iwqp;
  768. iwqp = qp->qp_uk.back_qp;
  769. irdma_next_iw_state(iwqp, next_state, 0, term, term_len);
  770. };
  771. /**
  772. * irdma_terminate_done - after terminate is completed
  773. * @qp: hardware control qp
  774. * @timeout_occurred: indicates if terminate timer expired
  775. */
  776. void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred)
  777. {
  778. struct irdma_qp *iwqp;
  779. u8 hte = 0;
  780. bool first_time;
  781. unsigned long flags;
  782. iwqp = qp->qp_uk.back_qp;
  783. spin_lock_irqsave(&iwqp->lock, flags);
  784. if (iwqp->hte_added) {
  785. iwqp->hte_added = 0;
  786. hte = 1;
  787. }
  788. first_time = !(qp->term_flags & IRDMA_TERM_DONE);
  789. qp->term_flags |= IRDMA_TERM_DONE;
  790. spin_unlock_irqrestore(&iwqp->lock, flags);
  791. if (first_time) {
  792. if (!timeout_occurred)
  793. irdma_terminate_del_timer(qp);
  794. irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, hte, 0, 0);
  795. irdma_cm_disconn(iwqp);
  796. }
  797. }
  798. static void irdma_terminate_timeout(struct timer_list *t)
  799. {
  800. struct irdma_qp *iwqp = from_timer(iwqp, t, terminate_timer);
  801. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  802. irdma_terminate_done(qp, 1);
  803. irdma_qp_rem_ref(&iwqp->ibqp);
  804. }
  805. /**
  806. * irdma_terminate_start_timer - start terminate timeout
  807. * @qp: hardware control qp
  808. */
  809. void irdma_terminate_start_timer(struct irdma_sc_qp *qp)
  810. {
  811. struct irdma_qp *iwqp;
  812. iwqp = qp->qp_uk.back_qp;
  813. irdma_qp_add_ref(&iwqp->ibqp);
  814. timer_setup(&iwqp->terminate_timer, irdma_terminate_timeout, 0);
  815. iwqp->terminate_timer.expires = jiffies + HZ;
  816. add_timer(&iwqp->terminate_timer);
  817. }
  818. /**
  819. * irdma_terminate_del_timer - delete terminate timeout
  820. * @qp: hardware control qp
  821. */
  822. void irdma_terminate_del_timer(struct irdma_sc_qp *qp)
  823. {
  824. struct irdma_qp *iwqp;
  825. int ret;
  826. iwqp = qp->qp_uk.back_qp;
  827. ret = del_timer(&iwqp->terminate_timer);
  828. if (ret)
  829. irdma_qp_rem_ref(&iwqp->ibqp);
  830. }
  831. /**
  832. * irdma_cqp_query_fpm_val_cmd - send cqp command for fpm
  833. * @dev: function device struct
  834. * @val_mem: buffer for fpm
  835. * @hmc_fn_id: function id for fpm
  836. */
  837. int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
  838. struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
  839. {
  840. struct irdma_cqp_request *cqp_request;
  841. struct cqp_cmds_info *cqp_info;
  842. struct irdma_pci_f *rf = dev_to_rf(dev);
  843. int status;
  844. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  845. if (!cqp_request)
  846. return -ENOMEM;
  847. cqp_info = &cqp_request->info;
  848. cqp_request->param = NULL;
  849. cqp_info->in.u.query_fpm_val.cqp = dev->cqp;
  850. cqp_info->in.u.query_fpm_val.fpm_val_pa = val_mem->pa;
  851. cqp_info->in.u.query_fpm_val.fpm_val_va = val_mem->va;
  852. cqp_info->in.u.query_fpm_val.hmc_fn_id = hmc_fn_id;
  853. cqp_info->cqp_cmd = IRDMA_OP_QUERY_FPM_VAL;
  854. cqp_info->post_sq = 1;
  855. cqp_info->in.u.query_fpm_val.scratch = (uintptr_t)cqp_request;
  856. status = irdma_handle_cqp_op(rf, cqp_request);
  857. irdma_put_cqp_request(&rf->cqp, cqp_request);
  858. return status;
  859. }
  860. /**
  861. * irdma_cqp_commit_fpm_val_cmd - commit fpm values in hw
  862. * @dev: hardware control device structure
  863. * @val_mem: buffer with fpm values
  864. * @hmc_fn_id: function id for fpm
  865. */
  866. int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
  867. struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
  868. {
  869. struct irdma_cqp_request *cqp_request;
  870. struct cqp_cmds_info *cqp_info;
  871. struct irdma_pci_f *rf = dev_to_rf(dev);
  872. int status;
  873. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  874. if (!cqp_request)
  875. return -ENOMEM;
  876. cqp_info = &cqp_request->info;
  877. cqp_request->param = NULL;
  878. cqp_info->in.u.commit_fpm_val.cqp = dev->cqp;
  879. cqp_info->in.u.commit_fpm_val.fpm_val_pa = val_mem->pa;
  880. cqp_info->in.u.commit_fpm_val.fpm_val_va = val_mem->va;
  881. cqp_info->in.u.commit_fpm_val.hmc_fn_id = hmc_fn_id;
  882. cqp_info->cqp_cmd = IRDMA_OP_COMMIT_FPM_VAL;
  883. cqp_info->post_sq = 1;
  884. cqp_info->in.u.commit_fpm_val.scratch = (uintptr_t)cqp_request;
  885. status = irdma_handle_cqp_op(rf, cqp_request);
  886. irdma_put_cqp_request(&rf->cqp, cqp_request);
  887. return status;
  888. }
  889. /**
  890. * irdma_cqp_cq_create_cmd - create a cq for the cqp
  891. * @dev: device pointer
  892. * @cq: pointer to created cq
  893. */
  894. int irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
  895. {
  896. struct irdma_pci_f *rf = dev_to_rf(dev);
  897. struct irdma_cqp *iwcqp = &rf->cqp;
  898. struct irdma_cqp_request *cqp_request;
  899. struct cqp_cmds_info *cqp_info;
  900. int status;
  901. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  902. if (!cqp_request)
  903. return -ENOMEM;
  904. cqp_info = &cqp_request->info;
  905. cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
  906. cqp_info->post_sq = 1;
  907. cqp_info->in.u.cq_create.cq = cq;
  908. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  909. status = irdma_handle_cqp_op(rf, cqp_request);
  910. irdma_put_cqp_request(iwcqp, cqp_request);
  911. return status;
  912. }
  913. /**
  914. * irdma_cqp_qp_create_cmd - create a qp for the cqp
  915. * @dev: device pointer
  916. * @qp: pointer to created qp
  917. */
  918. int irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  919. {
  920. struct irdma_pci_f *rf = dev_to_rf(dev);
  921. struct irdma_cqp *iwcqp = &rf->cqp;
  922. struct irdma_cqp_request *cqp_request;
  923. struct cqp_cmds_info *cqp_info;
  924. struct irdma_create_qp_info *qp_info;
  925. int status;
  926. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  927. if (!cqp_request)
  928. return -ENOMEM;
  929. cqp_info = &cqp_request->info;
  930. qp_info = &cqp_request->info.in.u.qp_create.info;
  931. memset(qp_info, 0, sizeof(*qp_info));
  932. qp_info->cq_num_valid = true;
  933. qp_info->next_iwarp_state = IRDMA_QP_STATE_RTS;
  934. cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
  935. cqp_info->post_sq = 1;
  936. cqp_info->in.u.qp_create.qp = qp;
  937. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  938. status = irdma_handle_cqp_op(rf, cqp_request);
  939. irdma_put_cqp_request(iwcqp, cqp_request);
  940. return status;
  941. }
  942. /**
  943. * irdma_dealloc_push_page - free a push page for qp
  944. * @rf: RDMA PCI function
  945. * @qp: hardware control qp
  946. */
  947. static void irdma_dealloc_push_page(struct irdma_pci_f *rf,
  948. struct irdma_sc_qp *qp)
  949. {
  950. struct irdma_cqp_request *cqp_request;
  951. struct cqp_cmds_info *cqp_info;
  952. int status;
  953. if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX)
  954. return;
  955. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
  956. if (!cqp_request)
  957. return;
  958. cqp_info = &cqp_request->info;
  959. cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
  960. cqp_info->post_sq = 1;
  961. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  962. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  963. cqp_info->in.u.manage_push_page.info.free_page = 1;
  964. cqp_info->in.u.manage_push_page.info.push_page_type = 0;
  965. cqp_info->in.u.manage_push_page.cqp = &rf->cqp.sc_cqp;
  966. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  967. status = irdma_handle_cqp_op(rf, cqp_request);
  968. if (!status)
  969. qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;
  970. irdma_put_cqp_request(&rf->cqp, cqp_request);
  971. }
  972. /**
  973. * irdma_free_qp_rsrc - free up memory resources for qp
  974. * @iwqp: qp ptr (user or kernel)
  975. */
  976. void irdma_free_qp_rsrc(struct irdma_qp *iwqp)
  977. {
  978. struct irdma_device *iwdev = iwqp->iwdev;
  979. struct irdma_pci_f *rf = iwdev->rf;
  980. u32 qp_num = iwqp->ibqp.qp_num;
  981. irdma_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
  982. irdma_dealloc_push_page(rf, &iwqp->sc_qp);
  983. if (iwqp->sc_qp.vsi) {
  984. irdma_qp_rem_qos(&iwqp->sc_qp);
  985. iwqp->sc_qp.dev->ws_remove(iwqp->sc_qp.vsi,
  986. iwqp->sc_qp.user_pri);
  987. }
  988. if (qp_num > 2)
  989. irdma_free_rsrc(rf, rf->allocated_qps, qp_num);
  990. dma_free_coherent(rf->sc_dev.hw->device, iwqp->q2_ctx_mem.size,
  991. iwqp->q2_ctx_mem.va, iwqp->q2_ctx_mem.pa);
  992. iwqp->q2_ctx_mem.va = NULL;
  993. dma_free_coherent(rf->sc_dev.hw->device, iwqp->kqp.dma_mem.size,
  994. iwqp->kqp.dma_mem.va, iwqp->kqp.dma_mem.pa);
  995. iwqp->kqp.dma_mem.va = NULL;
  996. kfree(iwqp->kqp.sq_wrid_mem);
  997. kfree(iwqp->kqp.rq_wrid_mem);
  998. }
  999. /**
  1000. * irdma_cq_wq_destroy - send cq destroy cqp
  1001. * @rf: RDMA PCI function
  1002. * @cq: hardware control cq
  1003. */
  1004. void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
  1005. {
  1006. struct irdma_cqp_request *cqp_request;
  1007. struct cqp_cmds_info *cqp_info;
  1008. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1009. if (!cqp_request)
  1010. return;
  1011. cqp_info = &cqp_request->info;
  1012. cqp_info->cqp_cmd = IRDMA_OP_CQ_DESTROY;
  1013. cqp_info->post_sq = 1;
  1014. cqp_info->in.u.cq_destroy.cq = cq;
  1015. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  1016. irdma_handle_cqp_op(rf, cqp_request);
  1017. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1018. }
  1019. /**
  1020. * irdma_hw_modify_qp_callback - handle state for modifyQPs that don't wait
  1021. * @cqp_request: modify QP completion
  1022. */
  1023. static void irdma_hw_modify_qp_callback(struct irdma_cqp_request *cqp_request)
  1024. {
  1025. struct cqp_cmds_info *cqp_info;
  1026. struct irdma_qp *iwqp;
  1027. cqp_info = &cqp_request->info;
  1028. iwqp = cqp_info->in.u.qp_modify.qp->qp_uk.back_qp;
  1029. atomic_dec(&iwqp->hw_mod_qp_pend);
  1030. wake_up(&iwqp->mod_qp_waitq);
  1031. }
  1032. /**
  1033. * irdma_hw_modify_qp - setup cqp for modify qp
  1034. * @iwdev: RDMA device
  1035. * @iwqp: qp ptr (user or kernel)
  1036. * @info: info for modify qp
  1037. * @wait: flag to wait or not for modify qp completion
  1038. */
  1039. int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,
  1040. struct irdma_modify_qp_info *info, bool wait)
  1041. {
  1042. int status;
  1043. struct irdma_pci_f *rf = iwdev->rf;
  1044. struct irdma_cqp_request *cqp_request;
  1045. struct cqp_cmds_info *cqp_info;
  1046. struct irdma_modify_qp_info *m_info;
  1047. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
  1048. if (!cqp_request)
  1049. return -ENOMEM;
  1050. if (!wait) {
  1051. cqp_request->callback_fcn = irdma_hw_modify_qp_callback;
  1052. atomic_inc(&iwqp->hw_mod_qp_pend);
  1053. }
  1054. cqp_info = &cqp_request->info;
  1055. m_info = &cqp_info->in.u.qp_modify.info;
  1056. memcpy(m_info, info, sizeof(*m_info));
  1057. cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;
  1058. cqp_info->post_sq = 1;
  1059. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  1060. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  1061. status = irdma_handle_cqp_op(rf, cqp_request);
  1062. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1063. if (status) {
  1064. if (rdma_protocol_roce(&iwdev->ibdev, 1))
  1065. return status;
  1066. switch (m_info->next_iwarp_state) {
  1067. struct irdma_gen_ae_info ae_info;
  1068. case IRDMA_QP_STATE_RTS:
  1069. case IRDMA_QP_STATE_IDLE:
  1070. case IRDMA_QP_STATE_TERMINATE:
  1071. case IRDMA_QP_STATE_CLOSING:
  1072. if (info->curr_iwarp_state == IRDMA_QP_STATE_IDLE)
  1073. irdma_send_reset(iwqp->cm_node);
  1074. else
  1075. iwqp->sc_qp.term_flags = IRDMA_TERM_DONE;
  1076. if (!wait) {
  1077. ae_info.ae_code = IRDMA_AE_BAD_CLOSE;
  1078. ae_info.ae_src = 0;
  1079. irdma_gen_ae(rf, &iwqp->sc_qp, &ae_info, false);
  1080. } else {
  1081. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp,
  1082. wait);
  1083. if (!cqp_request)
  1084. return -ENOMEM;
  1085. cqp_info = &cqp_request->info;
  1086. m_info = &cqp_info->in.u.qp_modify.info;
  1087. memcpy(m_info, info, sizeof(*m_info));
  1088. cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;
  1089. cqp_info->post_sq = 1;
  1090. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  1091. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  1092. m_info->next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1093. m_info->reset_tcp_conn = true;
  1094. irdma_handle_cqp_op(rf, cqp_request);
  1095. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1096. }
  1097. break;
  1098. case IRDMA_QP_STATE_ERROR:
  1099. default:
  1100. break;
  1101. }
  1102. }
  1103. return status;
  1104. }
  1105. /**
  1106. * irdma_cqp_cq_destroy_cmd - destroy the cqp cq
  1107. * @dev: device pointer
  1108. * @cq: pointer to cq
  1109. */
  1110. void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
  1111. {
  1112. struct irdma_pci_f *rf = dev_to_rf(dev);
  1113. irdma_cq_wq_destroy(rf, cq);
  1114. }
  1115. /**
  1116. * irdma_cqp_qp_destroy_cmd - destroy the cqp
  1117. * @dev: device pointer
  1118. * @qp: pointer to qp
  1119. */
  1120. int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  1121. {
  1122. struct irdma_pci_f *rf = dev_to_rf(dev);
  1123. struct irdma_cqp *iwcqp = &rf->cqp;
  1124. struct irdma_cqp_request *cqp_request;
  1125. struct cqp_cmds_info *cqp_info;
  1126. int status;
  1127. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  1128. if (!cqp_request)
  1129. return -ENOMEM;
  1130. cqp_info = &cqp_request->info;
  1131. memset(cqp_info, 0, sizeof(*cqp_info));
  1132. cqp_info->cqp_cmd = IRDMA_OP_QP_DESTROY;
  1133. cqp_info->post_sq = 1;
  1134. cqp_info->in.u.qp_destroy.qp = qp;
  1135. cqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;
  1136. cqp_info->in.u.qp_destroy.remove_hash_idx = true;
  1137. status = irdma_handle_cqp_op(rf, cqp_request);
  1138. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1139. return status;
  1140. }
  1141. /**
  1142. * irdma_ieq_mpa_crc_ae - generate AE for crc error
  1143. * @dev: hardware control device structure
  1144. * @qp: hardware control qp
  1145. */
  1146. void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  1147. {
  1148. struct irdma_gen_ae_info info = {};
  1149. struct irdma_pci_f *rf = dev_to_rf(dev);
  1150. ibdev_dbg(&rf->iwdev->ibdev, "AEQ: Generate MPA CRC AE\n");
  1151. info.ae_code = IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR;
  1152. info.ae_src = IRDMA_AE_SOURCE_RQ;
  1153. irdma_gen_ae(rf, qp, &info, false);
  1154. }
  1155. /**
  1156. * irdma_init_hash_desc - initialize hash for crc calculation
  1157. * @desc: cryption type
  1158. */
  1159. int irdma_init_hash_desc(struct shash_desc **desc)
  1160. {
  1161. struct crypto_shash *tfm;
  1162. struct shash_desc *tdesc;
  1163. tfm = crypto_alloc_shash("crc32c", 0, 0);
  1164. if (IS_ERR(tfm))
  1165. return -EINVAL;
  1166. tdesc = kzalloc(sizeof(*tdesc) + crypto_shash_descsize(tfm),
  1167. GFP_KERNEL);
  1168. if (!tdesc) {
  1169. crypto_free_shash(tfm);
  1170. return -EINVAL;
  1171. }
  1172. tdesc->tfm = tfm;
  1173. *desc = tdesc;
  1174. return 0;
  1175. }
  1176. /**
  1177. * irdma_free_hash_desc - free hash desc
  1178. * @desc: to be freed
  1179. */
  1180. void irdma_free_hash_desc(struct shash_desc *desc)
  1181. {
  1182. if (desc) {
  1183. crypto_free_shash(desc->tfm);
  1184. kfree(desc);
  1185. }
  1186. }
  1187. /**
  1188. * irdma_ieq_check_mpacrc - check if mpa crc is OK
  1189. * @desc: desc for hash
  1190. * @addr: address of buffer for crc
  1191. * @len: length of buffer
  1192. * @val: value to be compared
  1193. */
  1194. int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len,
  1195. u32 val)
  1196. {
  1197. u32 crc = 0;
  1198. int ret;
  1199. int ret_code = 0;
  1200. crypto_shash_init(desc);
  1201. ret = crypto_shash_update(desc, addr, len);
  1202. if (!ret)
  1203. crypto_shash_final(desc, (u8 *)&crc);
  1204. if (crc != val)
  1205. ret_code = -EINVAL;
  1206. return ret_code;
  1207. }
  1208. /**
  1209. * irdma_ieq_get_qp - get qp based on quad in puda buffer
  1210. * @dev: hardware control device structure
  1211. * @buf: receive puda buffer on exception q
  1212. */
  1213. struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev,
  1214. struct irdma_puda_buf *buf)
  1215. {
  1216. struct irdma_qp *iwqp;
  1217. struct irdma_cm_node *cm_node;
  1218. struct irdma_device *iwdev = buf->vsi->back_vsi;
  1219. u32 loc_addr[4] = {};
  1220. u32 rem_addr[4] = {};
  1221. u16 loc_port, rem_port;
  1222. struct ipv6hdr *ip6h;
  1223. struct iphdr *iph = (struct iphdr *)buf->iph;
  1224. struct tcphdr *tcph = (struct tcphdr *)buf->tcph;
  1225. if (iph->version == 4) {
  1226. loc_addr[0] = ntohl(iph->daddr);
  1227. rem_addr[0] = ntohl(iph->saddr);
  1228. } else {
  1229. ip6h = (struct ipv6hdr *)buf->iph;
  1230. irdma_copy_ip_ntohl(loc_addr, ip6h->daddr.in6_u.u6_addr32);
  1231. irdma_copy_ip_ntohl(rem_addr, ip6h->saddr.in6_u.u6_addr32);
  1232. }
  1233. loc_port = ntohs(tcph->dest);
  1234. rem_port = ntohs(tcph->source);
  1235. cm_node = irdma_find_node(&iwdev->cm_core, rem_port, rem_addr, loc_port,
  1236. loc_addr, buf->vlan_valid ? buf->vlan_id : 0xFFFF);
  1237. if (!cm_node)
  1238. return NULL;
  1239. iwqp = cm_node->iwqp;
  1240. irdma_rem_ref_cm_node(cm_node);
  1241. return &iwqp->sc_qp;
  1242. }
  1243. /**
  1244. * irdma_send_ieq_ack - ACKs for duplicate or OOO partials FPDUs
  1245. * @qp: qp ptr
  1246. */
  1247. void irdma_send_ieq_ack(struct irdma_sc_qp *qp)
  1248. {
  1249. struct irdma_cm_node *cm_node = ((struct irdma_qp *)qp->qp_uk.back_qp)->cm_node;
  1250. struct irdma_puda_buf *buf = qp->pfpdu.lastrcv_buf;
  1251. struct tcphdr *tcph = (struct tcphdr *)buf->tcph;
  1252. cm_node->tcp_cntxt.rcv_nxt = qp->pfpdu.nextseqnum;
  1253. cm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq);
  1254. irdma_send_ack(cm_node);
  1255. }
  1256. /**
  1257. * irdma_puda_ieq_get_ah_info - get AH info from IEQ buffer
  1258. * @qp: qp pointer
  1259. * @ah_info: AH info pointer
  1260. */
  1261. void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp,
  1262. struct irdma_ah_info *ah_info)
  1263. {
  1264. struct irdma_puda_buf *buf = qp->pfpdu.ah_buf;
  1265. struct iphdr *iph;
  1266. struct ipv6hdr *ip6h;
  1267. memset(ah_info, 0, sizeof(*ah_info));
  1268. ah_info->do_lpbk = true;
  1269. ah_info->vlan_tag = buf->vlan_id;
  1270. ah_info->insert_vlan_tag = buf->vlan_valid;
  1271. ah_info->ipv4_valid = buf->ipv4;
  1272. ah_info->vsi = qp->vsi;
  1273. if (buf->smac_valid)
  1274. ether_addr_copy(ah_info->mac_addr, buf->smac);
  1275. if (buf->ipv4) {
  1276. ah_info->ipv4_valid = true;
  1277. iph = (struct iphdr *)buf->iph;
  1278. ah_info->hop_ttl = iph->ttl;
  1279. ah_info->tc_tos = iph->tos;
  1280. ah_info->dest_ip_addr[0] = ntohl(iph->daddr);
  1281. ah_info->src_ip_addr[0] = ntohl(iph->saddr);
  1282. } else {
  1283. ip6h = (struct ipv6hdr *)buf->iph;
  1284. ah_info->hop_ttl = ip6h->hop_limit;
  1285. ah_info->tc_tos = ip6h->priority;
  1286. irdma_copy_ip_ntohl(ah_info->dest_ip_addr,
  1287. ip6h->daddr.in6_u.u6_addr32);
  1288. irdma_copy_ip_ntohl(ah_info->src_ip_addr,
  1289. ip6h->saddr.in6_u.u6_addr32);
  1290. }
  1291. ah_info->dst_arpindex = irdma_arp_table(dev_to_rf(qp->dev),
  1292. ah_info->dest_ip_addr,
  1293. ah_info->ipv4_valid,
  1294. NULL, IRDMA_ARP_RESOLVE);
  1295. }
  1296. /**
  1297. * irdma_gen1_ieq_update_tcpip_info - update tcpip in the buffer
  1298. * @buf: puda to update
  1299. * @len: length of buffer
  1300. * @seqnum: seq number for tcp
  1301. */
  1302. static void irdma_gen1_ieq_update_tcpip_info(struct irdma_puda_buf *buf,
  1303. u16 len, u32 seqnum)
  1304. {
  1305. struct tcphdr *tcph;
  1306. struct iphdr *iph;
  1307. u16 iphlen;
  1308. u16 pktsize;
  1309. u8 *addr = buf->mem.va;
  1310. iphlen = (buf->ipv4) ? 20 : 40;
  1311. iph = (struct iphdr *)(addr + buf->maclen);
  1312. tcph = (struct tcphdr *)(addr + buf->maclen + iphlen);
  1313. pktsize = len + buf->tcphlen + iphlen;
  1314. iph->tot_len = htons(pktsize);
  1315. tcph->seq = htonl(seqnum);
  1316. }
  1317. /**
  1318. * irdma_ieq_update_tcpip_info - update tcpip in the buffer
  1319. * @buf: puda to update
  1320. * @len: length of buffer
  1321. * @seqnum: seq number for tcp
  1322. */
  1323. void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,
  1324. u32 seqnum)
  1325. {
  1326. struct tcphdr *tcph;
  1327. u8 *addr;
  1328. if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
  1329. return irdma_gen1_ieq_update_tcpip_info(buf, len, seqnum);
  1330. addr = buf->mem.va;
  1331. tcph = (struct tcphdr *)addr;
  1332. tcph->seq = htonl(seqnum);
  1333. }
  1334. /**
  1335. * irdma_gen1_puda_get_tcpip_info - get tcpip info from puda
  1336. * buffer
  1337. * @info: to get information
  1338. * @buf: puda buffer
  1339. */
  1340. static int irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
  1341. struct irdma_puda_buf *buf)
  1342. {
  1343. struct iphdr *iph;
  1344. struct ipv6hdr *ip6h;
  1345. struct tcphdr *tcph;
  1346. u16 iphlen;
  1347. u16 pkt_len;
  1348. u8 *mem = buf->mem.va;
  1349. struct ethhdr *ethh = buf->mem.va;
  1350. if (ethh->h_proto == htons(0x8100)) {
  1351. info->vlan_valid = true;
  1352. buf->vlan_id = ntohs(((struct vlan_ethhdr *)ethh)->h_vlan_TCI) &
  1353. VLAN_VID_MASK;
  1354. }
  1355. buf->maclen = (info->vlan_valid) ? 18 : 14;
  1356. iphlen = (info->l3proto) ? 40 : 20;
  1357. buf->ipv4 = (info->l3proto) ? false : true;
  1358. buf->iph = mem + buf->maclen;
  1359. iph = (struct iphdr *)buf->iph;
  1360. buf->tcph = buf->iph + iphlen;
  1361. tcph = (struct tcphdr *)buf->tcph;
  1362. if (buf->ipv4) {
  1363. pkt_len = ntohs(iph->tot_len);
  1364. } else {
  1365. ip6h = (struct ipv6hdr *)buf->iph;
  1366. pkt_len = ntohs(ip6h->payload_len) + iphlen;
  1367. }
  1368. buf->totallen = pkt_len + buf->maclen;
  1369. if (info->payload_len < buf->totallen) {
  1370. ibdev_dbg(to_ibdev(buf->vsi->dev),
  1371. "ERR: payload_len = 0x%x totallen expected0x%x\n",
  1372. info->payload_len, buf->totallen);
  1373. return -EINVAL;
  1374. }
  1375. buf->tcphlen = tcph->doff << 2;
  1376. buf->datalen = pkt_len - iphlen - buf->tcphlen;
  1377. buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;
  1378. buf->hdrlen = buf->maclen + iphlen + buf->tcphlen;
  1379. buf->seqnum = ntohl(tcph->seq);
  1380. return 0;
  1381. }
  1382. /**
  1383. * irdma_puda_get_tcpip_info - get tcpip info from puda buffer
  1384. * @info: to get information
  1385. * @buf: puda buffer
  1386. */
  1387. int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
  1388. struct irdma_puda_buf *buf)
  1389. {
  1390. struct tcphdr *tcph;
  1391. u32 pkt_len;
  1392. u8 *mem;
  1393. if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
  1394. return irdma_gen1_puda_get_tcpip_info(info, buf);
  1395. mem = buf->mem.va;
  1396. buf->vlan_valid = info->vlan_valid;
  1397. if (info->vlan_valid)
  1398. buf->vlan_id = info->vlan;
  1399. buf->ipv4 = info->ipv4;
  1400. if (buf->ipv4)
  1401. buf->iph = mem + IRDMA_IPV4_PAD;
  1402. else
  1403. buf->iph = mem;
  1404. buf->tcph = mem + IRDMA_TCP_OFFSET;
  1405. tcph = (struct tcphdr *)buf->tcph;
  1406. pkt_len = info->payload_len;
  1407. buf->totallen = pkt_len;
  1408. buf->tcphlen = tcph->doff << 2;
  1409. buf->datalen = pkt_len - IRDMA_TCP_OFFSET - buf->tcphlen;
  1410. buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;
  1411. buf->hdrlen = IRDMA_TCP_OFFSET + buf->tcphlen;
  1412. buf->seqnum = ntohl(tcph->seq);
  1413. if (info->smac_valid) {
  1414. ether_addr_copy(buf->smac, info->smac);
  1415. buf->smac_valid = true;
  1416. }
  1417. return 0;
  1418. }
  1419. /**
  1420. * irdma_hw_stats_timeout - Stats timer-handler which updates all HW stats
  1421. * @t: timer_list pointer
  1422. */
  1423. static void irdma_hw_stats_timeout(struct timer_list *t)
  1424. {
  1425. struct irdma_vsi_pestat *pf_devstat =
  1426. from_timer(pf_devstat, t, stats_timer);
  1427. struct irdma_sc_vsi *sc_vsi = pf_devstat->vsi;
  1428. if (sc_vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
  1429. irdma_cqp_gather_stats_gen1(sc_vsi->dev, sc_vsi->pestat);
  1430. else
  1431. irdma_cqp_gather_stats_cmd(sc_vsi->dev, sc_vsi->pestat, false);
  1432. mod_timer(&pf_devstat->stats_timer,
  1433. jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
  1434. }
  1435. /**
  1436. * irdma_hw_stats_start_timer - Start periodic stats timer
  1437. * @vsi: vsi structure pointer
  1438. */
  1439. void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi)
  1440. {
  1441. struct irdma_vsi_pestat *devstat = vsi->pestat;
  1442. timer_setup(&devstat->stats_timer, irdma_hw_stats_timeout, 0);
  1443. mod_timer(&devstat->stats_timer,
  1444. jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
  1445. }
  1446. /**
  1447. * irdma_hw_stats_stop_timer - Delete periodic stats timer
  1448. * @vsi: pointer to vsi structure
  1449. */
  1450. void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi)
  1451. {
  1452. struct irdma_vsi_pestat *devstat = vsi->pestat;
  1453. del_timer_sync(&devstat->stats_timer);
  1454. }
  1455. /**
  1456. * irdma_process_stats - Checking for wrap and update stats
  1457. * @pestat: stats structure pointer
  1458. */
  1459. static inline void irdma_process_stats(struct irdma_vsi_pestat *pestat)
  1460. {
  1461. sc_vsi_update_stats(pestat->vsi);
  1462. }
  1463. /**
  1464. * irdma_cqp_gather_stats_gen1 - Gather stats
  1465. * @dev: pointer to device structure
  1466. * @pestat: statistics structure
  1467. */
  1468. void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev,
  1469. struct irdma_vsi_pestat *pestat)
  1470. {
  1471. struct irdma_gather_stats *gather_stats =
  1472. pestat->gather_info.gather_stats_va;
  1473. u32 stats_inst_offset_32;
  1474. u32 stats_inst_offset_64;
  1475. stats_inst_offset_32 = (pestat->gather_info.use_stats_inst) ?
  1476. pestat->gather_info.stats_inst_index :
  1477. pestat->hw->hmc.hmc_fn_id;
  1478. stats_inst_offset_32 *= 4;
  1479. stats_inst_offset_64 = stats_inst_offset_32 * 2;
  1480. gather_stats->rxvlanerr =
  1481. rd32(dev->hw,
  1482. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_RXVLANERR]
  1483. + stats_inst_offset_32);
  1484. gather_stats->ip4rxdiscard =
  1485. rd32(dev->hw,
  1486. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4RXDISCARD]
  1487. + stats_inst_offset_32);
  1488. gather_stats->ip4rxtrunc =
  1489. rd32(dev->hw,
  1490. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4RXTRUNC]
  1491. + stats_inst_offset_32);
  1492. gather_stats->ip4txnoroute =
  1493. rd32(dev->hw,
  1494. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE]
  1495. + stats_inst_offset_32);
  1496. gather_stats->ip6rxdiscard =
  1497. rd32(dev->hw,
  1498. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6RXDISCARD]
  1499. + stats_inst_offset_32);
  1500. gather_stats->ip6rxtrunc =
  1501. rd32(dev->hw,
  1502. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6RXTRUNC]
  1503. + stats_inst_offset_32);
  1504. gather_stats->ip6txnoroute =
  1505. rd32(dev->hw,
  1506. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE]
  1507. + stats_inst_offset_32);
  1508. gather_stats->tcprtxseg =
  1509. rd32(dev->hw,
  1510. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_TCPRTXSEG]
  1511. + stats_inst_offset_32);
  1512. gather_stats->tcprxopterr =
  1513. rd32(dev->hw,
  1514. dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_TCPRXOPTERR]
  1515. + stats_inst_offset_32);
  1516. gather_stats->ip4rxocts =
  1517. rd64(dev->hw,
  1518. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXOCTS]
  1519. + stats_inst_offset_64);
  1520. gather_stats->ip4rxpkts =
  1521. rd64(dev->hw,
  1522. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXPKTS]
  1523. + stats_inst_offset_64);
  1524. gather_stats->ip4txfrag =
  1525. rd64(dev->hw,
  1526. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXFRAGS]
  1527. + stats_inst_offset_64);
  1528. gather_stats->ip4rxmcpkts =
  1529. rd64(dev->hw,
  1530. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS]
  1531. + stats_inst_offset_64);
  1532. gather_stats->ip4txocts =
  1533. rd64(dev->hw,
  1534. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXOCTS]
  1535. + stats_inst_offset_64);
  1536. gather_stats->ip4txpkts =
  1537. rd64(dev->hw,
  1538. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXPKTS]
  1539. + stats_inst_offset_64);
  1540. gather_stats->ip4txfrag =
  1541. rd64(dev->hw,
  1542. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXFRAGS]
  1543. + stats_inst_offset_64);
  1544. gather_stats->ip4txmcpkts =
  1545. rd64(dev->hw,
  1546. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS]
  1547. + stats_inst_offset_64);
  1548. gather_stats->ip6rxocts =
  1549. rd64(dev->hw,
  1550. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXOCTS]
  1551. + stats_inst_offset_64);
  1552. gather_stats->ip6rxpkts =
  1553. rd64(dev->hw,
  1554. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXPKTS]
  1555. + stats_inst_offset_64);
  1556. gather_stats->ip6txfrags =
  1557. rd64(dev->hw,
  1558. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXFRAGS]
  1559. + stats_inst_offset_64);
  1560. gather_stats->ip6rxmcpkts =
  1561. rd64(dev->hw,
  1562. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS]
  1563. + stats_inst_offset_64);
  1564. gather_stats->ip6txocts =
  1565. rd64(dev->hw,
  1566. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXOCTS]
  1567. + stats_inst_offset_64);
  1568. gather_stats->ip6txpkts =
  1569. rd64(dev->hw,
  1570. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXPKTS]
  1571. + stats_inst_offset_64);
  1572. gather_stats->ip6txfrags =
  1573. rd64(dev->hw,
  1574. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXFRAGS]
  1575. + stats_inst_offset_64);
  1576. gather_stats->ip6txmcpkts =
  1577. rd64(dev->hw,
  1578. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS]
  1579. + stats_inst_offset_64);
  1580. gather_stats->tcprxsegs =
  1581. rd64(dev->hw,
  1582. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_TCPRXSEGS]
  1583. + stats_inst_offset_64);
  1584. gather_stats->tcptxsegs =
  1585. rd64(dev->hw,
  1586. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_TCPTXSEG]
  1587. + stats_inst_offset_64);
  1588. gather_stats->rdmarxrds =
  1589. rd64(dev->hw,
  1590. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXRDS]
  1591. + stats_inst_offset_64);
  1592. gather_stats->rdmarxsnds =
  1593. rd64(dev->hw,
  1594. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXSNDS]
  1595. + stats_inst_offset_64);
  1596. gather_stats->rdmarxwrs =
  1597. rd64(dev->hw,
  1598. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXWRS]
  1599. + stats_inst_offset_64);
  1600. gather_stats->rdmatxrds =
  1601. rd64(dev->hw,
  1602. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXRDS]
  1603. + stats_inst_offset_64);
  1604. gather_stats->rdmatxsnds =
  1605. rd64(dev->hw,
  1606. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXSNDS]
  1607. + stats_inst_offset_64);
  1608. gather_stats->rdmatxwrs =
  1609. rd64(dev->hw,
  1610. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXWRS]
  1611. + stats_inst_offset_64);
  1612. gather_stats->rdmavbn =
  1613. rd64(dev->hw,
  1614. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMAVBND]
  1615. + stats_inst_offset_64);
  1616. gather_stats->rdmavinv =
  1617. rd64(dev->hw,
  1618. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMAVINV]
  1619. + stats_inst_offset_64);
  1620. gather_stats->udprxpkts =
  1621. rd64(dev->hw,
  1622. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_UDPRXPKTS]
  1623. + stats_inst_offset_64);
  1624. gather_stats->udptxpkts =
  1625. rd64(dev->hw,
  1626. dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_UDPTXPKTS]
  1627. + stats_inst_offset_64);
  1628. irdma_process_stats(pestat);
  1629. }
  1630. /**
  1631. * irdma_process_cqp_stats - Checking for wrap and update stats
  1632. * @cqp_request: cqp_request structure pointer
  1633. */
  1634. static void irdma_process_cqp_stats(struct irdma_cqp_request *cqp_request)
  1635. {
  1636. struct irdma_vsi_pestat *pestat = cqp_request->param;
  1637. irdma_process_stats(pestat);
  1638. }
  1639. /**
  1640. * irdma_cqp_gather_stats_cmd - Gather stats
  1641. * @dev: pointer to device structure
  1642. * @pestat: pointer to stats info
  1643. * @wait: flag to wait or not wait for stats
  1644. */
  1645. int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,
  1646. struct irdma_vsi_pestat *pestat, bool wait)
  1647. {
  1648. struct irdma_pci_f *rf = dev_to_rf(dev);
  1649. struct irdma_cqp *iwcqp = &rf->cqp;
  1650. struct irdma_cqp_request *cqp_request;
  1651. struct cqp_cmds_info *cqp_info;
  1652. int status;
  1653. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
  1654. if (!cqp_request)
  1655. return -ENOMEM;
  1656. cqp_info = &cqp_request->info;
  1657. memset(cqp_info, 0, sizeof(*cqp_info));
  1658. cqp_info->cqp_cmd = IRDMA_OP_STATS_GATHER;
  1659. cqp_info->post_sq = 1;
  1660. cqp_info->in.u.stats_gather.info = pestat->gather_info;
  1661. cqp_info->in.u.stats_gather.scratch = (uintptr_t)cqp_request;
  1662. cqp_info->in.u.stats_gather.cqp = &rf->cqp.sc_cqp;
  1663. cqp_request->param = pestat;
  1664. if (!wait)
  1665. cqp_request->callback_fcn = irdma_process_cqp_stats;
  1666. status = irdma_handle_cqp_op(rf, cqp_request);
  1667. if (wait)
  1668. irdma_process_stats(pestat);
  1669. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1670. return status;
  1671. }
  1672. /**
  1673. * irdma_cqp_stats_inst_cmd - Allocate/free stats instance
  1674. * @vsi: pointer to vsi structure
  1675. * @cmd: command to allocate or free
  1676. * @stats_info: pointer to allocate stats info
  1677. */
  1678. int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
  1679. struct irdma_stats_inst_info *stats_info)
  1680. {
  1681. struct irdma_pci_f *rf = dev_to_rf(vsi->dev);
  1682. struct irdma_cqp *iwcqp = &rf->cqp;
  1683. struct irdma_cqp_request *cqp_request;
  1684. struct cqp_cmds_info *cqp_info;
  1685. int status;
  1686. bool wait = false;
  1687. if (cmd == IRDMA_OP_STATS_ALLOCATE)
  1688. wait = true;
  1689. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
  1690. if (!cqp_request)
  1691. return -ENOMEM;
  1692. cqp_info = &cqp_request->info;
  1693. memset(cqp_info, 0, sizeof(*cqp_info));
  1694. cqp_info->cqp_cmd = cmd;
  1695. cqp_info->post_sq = 1;
  1696. cqp_info->in.u.stats_manage.info = *stats_info;
  1697. cqp_info->in.u.stats_manage.scratch = (uintptr_t)cqp_request;
  1698. cqp_info->in.u.stats_manage.cqp = &rf->cqp.sc_cqp;
  1699. status = irdma_handle_cqp_op(rf, cqp_request);
  1700. if (wait)
  1701. stats_info->stats_idx = cqp_request->compl_info.op_ret_val;
  1702. irdma_put_cqp_request(iwcqp, cqp_request);
  1703. return status;
  1704. }
  1705. /**
  1706. * irdma_cqp_ceq_cmd - Create/Destroy CEQ's after CEQ 0
  1707. * @dev: pointer to device info
  1708. * @sc_ceq: pointer to ceq structure
  1709. * @op: Create or Destroy
  1710. */
  1711. int irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_ceq *sc_ceq,
  1712. u8 op)
  1713. {
  1714. struct irdma_cqp_request *cqp_request;
  1715. struct cqp_cmds_info *cqp_info;
  1716. struct irdma_pci_f *rf = dev_to_rf(dev);
  1717. int status;
  1718. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1719. if (!cqp_request)
  1720. return -ENOMEM;
  1721. cqp_info = &cqp_request->info;
  1722. cqp_info->post_sq = 1;
  1723. cqp_info->cqp_cmd = op;
  1724. cqp_info->in.u.ceq_create.ceq = sc_ceq;
  1725. cqp_info->in.u.ceq_create.scratch = (uintptr_t)cqp_request;
  1726. status = irdma_handle_cqp_op(rf, cqp_request);
  1727. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1728. return status;
  1729. }
  1730. /**
  1731. * irdma_cqp_aeq_cmd - Create/Destroy AEQ
  1732. * @dev: pointer to device info
  1733. * @sc_aeq: pointer to aeq structure
  1734. * @op: Create or Destroy
  1735. */
  1736. int irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_aeq *sc_aeq,
  1737. u8 op)
  1738. {
  1739. struct irdma_cqp_request *cqp_request;
  1740. struct cqp_cmds_info *cqp_info;
  1741. struct irdma_pci_f *rf = dev_to_rf(dev);
  1742. int status;
  1743. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1744. if (!cqp_request)
  1745. return -ENOMEM;
  1746. cqp_info = &cqp_request->info;
  1747. cqp_info->post_sq = 1;
  1748. cqp_info->cqp_cmd = op;
  1749. cqp_info->in.u.aeq_create.aeq = sc_aeq;
  1750. cqp_info->in.u.aeq_create.scratch = (uintptr_t)cqp_request;
  1751. status = irdma_handle_cqp_op(rf, cqp_request);
  1752. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1753. return status;
  1754. }
  1755. /**
  1756. * irdma_cqp_ws_node_cmd - Add/modify/delete ws node
  1757. * @dev: pointer to device structure
  1758. * @cmd: Add, modify or delete
  1759. * @node_info: pointer to ws node info
  1760. */
  1761. int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,
  1762. struct irdma_ws_node_info *node_info)
  1763. {
  1764. struct irdma_pci_f *rf = dev_to_rf(dev);
  1765. struct irdma_cqp *iwcqp = &rf->cqp;
  1766. struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp;
  1767. struct irdma_cqp_request *cqp_request;
  1768. struct cqp_cmds_info *cqp_info;
  1769. int status;
  1770. bool poll;
  1771. if (!rf->sc_dev.ceq_valid)
  1772. poll = true;
  1773. else
  1774. poll = false;
  1775. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, !poll);
  1776. if (!cqp_request)
  1777. return -ENOMEM;
  1778. cqp_info = &cqp_request->info;
  1779. memset(cqp_info, 0, sizeof(*cqp_info));
  1780. cqp_info->cqp_cmd = cmd;
  1781. cqp_info->post_sq = 1;
  1782. cqp_info->in.u.ws_node.info = *node_info;
  1783. cqp_info->in.u.ws_node.cqp = cqp;
  1784. cqp_info->in.u.ws_node.scratch = (uintptr_t)cqp_request;
  1785. status = irdma_handle_cqp_op(rf, cqp_request);
  1786. if (status)
  1787. goto exit;
  1788. if (poll) {
  1789. struct irdma_ccq_cqe_info compl_info;
  1790. status = irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_WORK_SCHED_NODE,
  1791. &compl_info);
  1792. node_info->qs_handle = compl_info.op_ret_val;
  1793. ibdev_dbg(&rf->iwdev->ibdev, "DCB: opcode=%d, compl_info.retval=%d\n",
  1794. compl_info.op_code, compl_info.op_ret_val);
  1795. } else {
  1796. node_info->qs_handle = cqp_request->compl_info.op_ret_val;
  1797. }
  1798. exit:
  1799. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1800. return status;
  1801. }
  1802. /**
  1803. * irdma_ah_cqp_op - perform an AH cqp operation
  1804. * @rf: RDMA PCI function
  1805. * @sc_ah: address handle
  1806. * @cmd: AH operation
  1807. * @wait: wait if true
  1808. * @callback_fcn: Callback function on CQP op completion
  1809. * @cb_param: parameter for callback function
  1810. *
  1811. * returns errno
  1812. */
  1813. int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd,
  1814. bool wait,
  1815. void (*callback_fcn)(struct irdma_cqp_request *),
  1816. void *cb_param)
  1817. {
  1818. struct irdma_cqp_request *cqp_request;
  1819. struct cqp_cmds_info *cqp_info;
  1820. int status;
  1821. if (cmd != IRDMA_OP_AH_CREATE && cmd != IRDMA_OP_AH_DESTROY)
  1822. return -EINVAL;
  1823. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
  1824. if (!cqp_request)
  1825. return -ENOMEM;
  1826. cqp_info = &cqp_request->info;
  1827. cqp_info->cqp_cmd = cmd;
  1828. cqp_info->post_sq = 1;
  1829. if (cmd == IRDMA_OP_AH_CREATE) {
  1830. cqp_info->in.u.ah_create.info = sc_ah->ah_info;
  1831. cqp_info->in.u.ah_create.scratch = (uintptr_t)cqp_request;
  1832. cqp_info->in.u.ah_create.cqp = &rf->cqp.sc_cqp;
  1833. } else if (cmd == IRDMA_OP_AH_DESTROY) {
  1834. cqp_info->in.u.ah_destroy.info = sc_ah->ah_info;
  1835. cqp_info->in.u.ah_destroy.scratch = (uintptr_t)cqp_request;
  1836. cqp_info->in.u.ah_destroy.cqp = &rf->cqp.sc_cqp;
  1837. }
  1838. if (!wait) {
  1839. cqp_request->callback_fcn = callback_fcn;
  1840. cqp_request->param = cb_param;
  1841. }
  1842. status = irdma_handle_cqp_op(rf, cqp_request);
  1843. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1844. if (status)
  1845. return -ENOMEM;
  1846. if (wait)
  1847. sc_ah->ah_info.ah_valid = (cmd == IRDMA_OP_AH_CREATE);
  1848. return 0;
  1849. }
  1850. /**
  1851. * irdma_ieq_ah_cb - callback after creation of AH for IEQ
  1852. * @cqp_request: pointer to cqp_request of create AH
  1853. */
  1854. static void irdma_ieq_ah_cb(struct irdma_cqp_request *cqp_request)
  1855. {
  1856. struct irdma_sc_qp *qp = cqp_request->param;
  1857. struct irdma_sc_ah *sc_ah = qp->pfpdu.ah;
  1858. unsigned long flags;
  1859. spin_lock_irqsave(&qp->pfpdu.lock, flags);
  1860. if (!cqp_request->compl_info.op_ret_val) {
  1861. sc_ah->ah_info.ah_valid = true;
  1862. irdma_ieq_process_fpdus(qp, qp->vsi->ieq);
  1863. } else {
  1864. sc_ah->ah_info.ah_valid = false;
  1865. irdma_ieq_cleanup_qp(qp->vsi->ieq, qp);
  1866. }
  1867. spin_unlock_irqrestore(&qp->pfpdu.lock, flags);
  1868. }
  1869. /**
  1870. * irdma_ilq_ah_cb - callback after creation of AH for ILQ
  1871. * @cqp_request: pointer to cqp_request of create AH
  1872. */
  1873. static void irdma_ilq_ah_cb(struct irdma_cqp_request *cqp_request)
  1874. {
  1875. struct irdma_cm_node *cm_node = cqp_request->param;
  1876. struct irdma_sc_ah *sc_ah = cm_node->ah;
  1877. sc_ah->ah_info.ah_valid = !cqp_request->compl_info.op_ret_val;
  1878. irdma_add_conn_est_qh(cm_node);
  1879. }
  1880. /**
  1881. * irdma_puda_create_ah - create AH for ILQ/IEQ qp's
  1882. * @dev: device pointer
  1883. * @ah_info: Address handle info
  1884. * @wait: When true will wait for operation to complete
  1885. * @type: ILQ/IEQ
  1886. * @cb_param: Callback param when not waiting
  1887. * @ah_ret: Returned pointer to address handle if created
  1888. *
  1889. */
  1890. int irdma_puda_create_ah(struct irdma_sc_dev *dev,
  1891. struct irdma_ah_info *ah_info, bool wait,
  1892. enum puda_rsrc_type type, void *cb_param,
  1893. struct irdma_sc_ah **ah_ret)
  1894. {
  1895. struct irdma_sc_ah *ah;
  1896. struct irdma_pci_f *rf = dev_to_rf(dev);
  1897. int err;
  1898. ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
  1899. *ah_ret = ah;
  1900. if (!ah)
  1901. return -ENOMEM;
  1902. err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah,
  1903. &ah_info->ah_idx, &rf->next_ah);
  1904. if (err)
  1905. goto err_free;
  1906. ah->dev = dev;
  1907. ah->ah_info = *ah_info;
  1908. if (type == IRDMA_PUDA_RSRC_TYPE_ILQ)
  1909. err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,
  1910. irdma_ilq_ah_cb, cb_param);
  1911. else
  1912. err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,
  1913. irdma_ieq_ah_cb, cb_param);
  1914. if (err)
  1915. goto error;
  1916. return 0;
  1917. error:
  1918. irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);
  1919. err_free:
  1920. kfree(ah);
  1921. *ah_ret = NULL;
  1922. return -ENOMEM;
  1923. }
  1924. /**
  1925. * irdma_puda_free_ah - free a puda address handle
  1926. * @dev: device pointer
  1927. * @ah: The address handle to free
  1928. */
  1929. void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)
  1930. {
  1931. struct irdma_pci_f *rf = dev_to_rf(dev);
  1932. if (!ah)
  1933. return;
  1934. if (ah->ah_info.ah_valid) {
  1935. irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_DESTROY, false, NULL, NULL);
  1936. irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);
  1937. }
  1938. kfree(ah);
  1939. }
  1940. /**
  1941. * irdma_gsi_ud_qp_ah_cb - callback after creation of AH for GSI/ID QP
  1942. * @cqp_request: pointer to cqp_request of create AH
  1943. */
  1944. void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request)
  1945. {
  1946. struct irdma_sc_ah *sc_ah = cqp_request->param;
  1947. if (!cqp_request->compl_info.op_ret_val)
  1948. sc_ah->ah_info.ah_valid = true;
  1949. else
  1950. sc_ah->ah_info.ah_valid = false;
  1951. }
  1952. /**
  1953. * irdma_prm_add_pble_mem - add moemory to pble resources
  1954. * @pprm: pble resource manager
  1955. * @pchunk: chunk of memory to add
  1956. */
  1957. int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,
  1958. struct irdma_chunk *pchunk)
  1959. {
  1960. u64 sizeofbitmap;
  1961. if (pchunk->size & 0xfff)
  1962. return -EINVAL;
  1963. sizeofbitmap = (u64)pchunk->size >> pprm->pble_shift;
  1964. pchunk->bitmapbuf = bitmap_zalloc(sizeofbitmap, GFP_KERNEL);
  1965. if (!pchunk->bitmapbuf)
  1966. return -ENOMEM;
  1967. pchunk->sizeofbitmap = sizeofbitmap;
  1968. /* each pble is 8 bytes hence shift by 3 */
  1969. pprm->total_pble_alloc += pchunk->size >> 3;
  1970. pprm->free_pble_cnt += pchunk->size >> 3;
  1971. return 0;
  1972. }
  1973. /**
  1974. * irdma_prm_get_pbles - get pble's from prm
  1975. * @pprm: pble resource manager
  1976. * @chunkinfo: nformation about chunk where pble's were acquired
  1977. * @mem_size: size of pble memory needed
  1978. * @vaddr: returns virtual address of pble memory
  1979. * @fpm_addr: returns fpm address of pble memory
  1980. */
  1981. int irdma_prm_get_pbles(struct irdma_pble_prm *pprm,
  1982. struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,
  1983. u64 **vaddr, u64 *fpm_addr)
  1984. {
  1985. u64 bits_needed;
  1986. u64 bit_idx = PBLE_INVALID_IDX;
  1987. struct irdma_chunk *pchunk = NULL;
  1988. struct list_head *chunk_entry = pprm->clist.next;
  1989. u32 offset;
  1990. unsigned long flags;
  1991. *vaddr = NULL;
  1992. *fpm_addr = 0;
  1993. bits_needed = DIV_ROUND_UP_ULL(mem_size, BIT_ULL(pprm->pble_shift));
  1994. spin_lock_irqsave(&pprm->prm_lock, flags);
  1995. while (chunk_entry != &pprm->clist) {
  1996. pchunk = (struct irdma_chunk *)chunk_entry;
  1997. bit_idx = bitmap_find_next_zero_area(pchunk->bitmapbuf,
  1998. pchunk->sizeofbitmap, 0,
  1999. bits_needed, 0);
  2000. if (bit_idx < pchunk->sizeofbitmap)
  2001. break;
  2002. /* list.next used macro */
  2003. chunk_entry = pchunk->list.next;
  2004. }
  2005. if (!pchunk || bit_idx >= pchunk->sizeofbitmap) {
  2006. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  2007. return -ENOMEM;
  2008. }
  2009. bitmap_set(pchunk->bitmapbuf, bit_idx, bits_needed);
  2010. offset = bit_idx << pprm->pble_shift;
  2011. *vaddr = pchunk->vaddr + offset;
  2012. *fpm_addr = pchunk->fpm_addr + offset;
  2013. chunkinfo->pchunk = pchunk;
  2014. chunkinfo->bit_idx = bit_idx;
  2015. chunkinfo->bits_used = bits_needed;
  2016. /* 3 is sizeof pble divide */
  2017. pprm->free_pble_cnt -= chunkinfo->bits_used << (pprm->pble_shift - 3);
  2018. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  2019. return 0;
  2020. }
  2021. /**
  2022. * irdma_prm_return_pbles - return pbles back to prm
  2023. * @pprm: pble resource manager
  2024. * @chunkinfo: chunk where pble's were acquired and to be freed
  2025. */
  2026. void irdma_prm_return_pbles(struct irdma_pble_prm *pprm,
  2027. struct irdma_pble_chunkinfo *chunkinfo)
  2028. {
  2029. unsigned long flags;
  2030. spin_lock_irqsave(&pprm->prm_lock, flags);
  2031. pprm->free_pble_cnt += chunkinfo->bits_used << (pprm->pble_shift - 3);
  2032. bitmap_clear(chunkinfo->pchunk->bitmapbuf, chunkinfo->bit_idx,
  2033. chunkinfo->bits_used);
  2034. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  2035. }
  2036. int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t *pg_dma,
  2037. u32 pg_cnt)
  2038. {
  2039. struct page *vm_page;
  2040. int i;
  2041. u8 *addr;
  2042. addr = (u8 *)(uintptr_t)va;
  2043. for (i = 0; i < pg_cnt; i++) {
  2044. vm_page = vmalloc_to_page(addr);
  2045. if (!vm_page)
  2046. goto err;
  2047. pg_dma[i] = dma_map_page(hw->device, vm_page, 0, PAGE_SIZE,
  2048. DMA_BIDIRECTIONAL);
  2049. if (dma_mapping_error(hw->device, pg_dma[i]))
  2050. goto err;
  2051. addr += PAGE_SIZE;
  2052. }
  2053. return 0;
  2054. err:
  2055. irdma_unmap_vm_page_list(hw, pg_dma, i);
  2056. return -ENOMEM;
  2057. }
  2058. void irdma_unmap_vm_page_list(struct irdma_hw *hw, dma_addr_t *pg_dma, u32 pg_cnt)
  2059. {
  2060. int i;
  2061. for (i = 0; i < pg_cnt; i++)
  2062. dma_unmap_page(hw->device, pg_dma[i], PAGE_SIZE, DMA_BIDIRECTIONAL);
  2063. }
  2064. /**
  2065. * irdma_pble_free_paged_mem - free virtual paged memory
  2066. * @chunk: chunk to free with paged memory
  2067. */
  2068. void irdma_pble_free_paged_mem(struct irdma_chunk *chunk)
  2069. {
  2070. if (!chunk->pg_cnt)
  2071. goto done;
  2072. irdma_unmap_vm_page_list(chunk->dev->hw, chunk->dmainfo.dmaaddrs,
  2073. chunk->pg_cnt);
  2074. done:
  2075. kfree(chunk->dmainfo.dmaaddrs);
  2076. chunk->dmainfo.dmaaddrs = NULL;
  2077. vfree(chunk->vaddr);
  2078. chunk->vaddr = NULL;
  2079. chunk->type = 0;
  2080. }
  2081. /**
  2082. * irdma_pble_get_paged_mem -allocate paged memory for pbles
  2083. * @chunk: chunk to add for paged memory
  2084. * @pg_cnt: number of pages needed
  2085. */
  2086. int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt)
  2087. {
  2088. u32 size;
  2089. void *va;
  2090. chunk->dmainfo.dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL);
  2091. if (!chunk->dmainfo.dmaaddrs)
  2092. return -ENOMEM;
  2093. size = PAGE_SIZE * pg_cnt;
  2094. va = vmalloc(size);
  2095. if (!va)
  2096. goto err;
  2097. if (irdma_map_vm_page_list(chunk->dev->hw, va, chunk->dmainfo.dmaaddrs,
  2098. pg_cnt)) {
  2099. vfree(va);
  2100. goto err;
  2101. }
  2102. chunk->vaddr = va;
  2103. chunk->size = size;
  2104. chunk->pg_cnt = pg_cnt;
  2105. chunk->type = PBLE_SD_PAGED;
  2106. return 0;
  2107. err:
  2108. kfree(chunk->dmainfo.dmaaddrs);
  2109. chunk->dmainfo.dmaaddrs = NULL;
  2110. return -ENOMEM;
  2111. }
  2112. /**
  2113. * irdma_alloc_ws_node_id - Allocate a tx scheduler node ID
  2114. * @dev: device pointer
  2115. */
  2116. u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev)
  2117. {
  2118. struct irdma_pci_f *rf = dev_to_rf(dev);
  2119. u32 next = 1;
  2120. u32 node_id;
  2121. if (irdma_alloc_rsrc(rf, rf->allocated_ws_nodes, rf->max_ws_node_id,
  2122. &node_id, &next))
  2123. return IRDMA_WS_NODE_INVALID;
  2124. return (u16)node_id;
  2125. }
  2126. /**
  2127. * irdma_free_ws_node_id - Free a tx scheduler node ID
  2128. * @dev: device pointer
  2129. * @node_id: Work scheduler node ID
  2130. */
  2131. void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id)
  2132. {
  2133. struct irdma_pci_f *rf = dev_to_rf(dev);
  2134. irdma_free_rsrc(rf, rf->allocated_ws_nodes, (u32)node_id);
  2135. }
  2136. /**
  2137. * irdma_modify_qp_to_err - Modify a QP to error
  2138. * @sc_qp: qp structure
  2139. */
  2140. void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp)
  2141. {
  2142. struct irdma_qp *qp = sc_qp->qp_uk.back_qp;
  2143. struct ib_qp_attr attr;
  2144. if (qp->iwdev->rf->reset)
  2145. return;
  2146. attr.qp_state = IB_QPS_ERR;
  2147. if (rdma_protocol_roce(qp->ibqp.device, 1))
  2148. irdma_modify_qp_roce(&qp->ibqp, &attr, IB_QP_STATE, NULL);
  2149. else
  2150. irdma_modify_qp(&qp->ibqp, &attr, IB_QP_STATE, NULL);
  2151. }
  2152. void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event)
  2153. {
  2154. struct ib_event ibevent;
  2155. if (!iwqp->ibqp.event_handler)
  2156. return;
  2157. switch (event) {
  2158. case IRDMA_QP_EVENT_CATASTROPHIC:
  2159. ibevent.event = IB_EVENT_QP_FATAL;
  2160. break;
  2161. case IRDMA_QP_EVENT_ACCESS_ERR:
  2162. ibevent.event = IB_EVENT_QP_ACCESS_ERR;
  2163. break;
  2164. case IRDMA_QP_EVENT_REQ_ERR:
  2165. ibevent.event = IB_EVENT_QP_REQ_ERR;
  2166. break;
  2167. }
  2168. ibevent.device = iwqp->ibqp.device;
  2169. ibevent.element.qp = &iwqp->ibqp;
  2170. iwqp->ibqp.event_handler(&ibevent, iwqp->ibqp.qp_context);
  2171. }
  2172. bool irdma_cq_empty(struct irdma_cq *iwcq)
  2173. {
  2174. struct irdma_cq_uk *ukcq;
  2175. u64 qword3;
  2176. __le64 *cqe;
  2177. u8 polarity;
  2178. ukcq = &iwcq->sc_cq.cq_uk;
  2179. cqe = IRDMA_GET_CURRENT_CQ_ELEM(ukcq);
  2180. get_64bit_val(cqe, 24, &qword3);
  2181. polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3);
  2182. return polarity != ukcq->polarity;
  2183. }
  2184. void irdma_remove_cmpls_list(struct irdma_cq *iwcq)
  2185. {
  2186. struct irdma_cmpl_gen *cmpl_node;
  2187. struct list_head *tmp_node, *list_node;
  2188. list_for_each_safe (list_node, tmp_node, &iwcq->cmpl_generated) {
  2189. cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list);
  2190. list_del(&cmpl_node->list);
  2191. kfree(cmpl_node);
  2192. }
  2193. }
  2194. int irdma_generated_cmpls(struct irdma_cq *iwcq, struct irdma_cq_poll_info *cq_poll_info)
  2195. {
  2196. struct irdma_cmpl_gen *cmpl;
  2197. if (list_empty(&iwcq->cmpl_generated))
  2198. return -ENOENT;
  2199. cmpl = list_first_entry_or_null(&iwcq->cmpl_generated, struct irdma_cmpl_gen, list);
  2200. list_del(&cmpl->list);
  2201. memcpy(cq_poll_info, &cmpl->cpi, sizeof(*cq_poll_info));
  2202. kfree(cmpl);
  2203. ibdev_dbg(iwcq->ibcq.device,
  2204. "VERBS: %s: Poll artificially generated completion for QP 0x%X, op %u, wr_id=0x%llx\n",
  2205. __func__, cq_poll_info->qp_id, cq_poll_info->op_type,
  2206. cq_poll_info->wr_id);
  2207. return 0;
  2208. }
  2209. /**
  2210. * irdma_set_cpi_common_values - fill in values for polling info struct
  2211. * @cpi: resulting structure of cq_poll_info type
  2212. * @qp: QPair
  2213. * @qp_num: id of the QP
  2214. */
  2215. static void irdma_set_cpi_common_values(struct irdma_cq_poll_info *cpi,
  2216. struct irdma_qp_uk *qp, u32 qp_num)
  2217. {
  2218. cpi->comp_status = IRDMA_COMPL_STATUS_FLUSHED;
  2219. cpi->error = true;
  2220. cpi->major_err = IRDMA_FLUSH_MAJOR_ERR;
  2221. cpi->minor_err = FLUSH_GENERAL_ERR;
  2222. cpi->qp_handle = (irdma_qp_handle)(uintptr_t)qp;
  2223. cpi->qp_id = qp_num;
  2224. }
  2225. static inline void irdma_comp_handler(struct irdma_cq *cq)
  2226. {
  2227. if (!cq->ibcq.comp_handler)
  2228. return;
  2229. if (atomic_cmpxchg(&cq->armed, 1, 0))
  2230. cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  2231. }
  2232. void irdma_generate_flush_completions(struct irdma_qp *iwqp)
  2233. {
  2234. struct irdma_qp_uk *qp = &iwqp->sc_qp.qp_uk;
  2235. struct irdma_ring *sq_ring = &qp->sq_ring;
  2236. struct irdma_ring *rq_ring = &qp->rq_ring;
  2237. struct irdma_cmpl_gen *cmpl;
  2238. __le64 *sw_wqe;
  2239. u64 wqe_qword;
  2240. u32 wqe_idx;
  2241. bool compl_generated = false;
  2242. unsigned long flags1;
  2243. spin_lock_irqsave(&iwqp->iwscq->lock, flags1);
  2244. if (irdma_cq_empty(iwqp->iwscq)) {
  2245. unsigned long flags2;
  2246. spin_lock_irqsave(&iwqp->lock, flags2);
  2247. while (IRDMA_RING_MORE_WORK(*sq_ring)) {
  2248. cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC);
  2249. if (!cmpl) {
  2250. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2251. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2252. return;
  2253. }
  2254. wqe_idx = sq_ring->tail;
  2255. irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id);
  2256. cmpl->cpi.wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
  2257. sw_wqe = qp->sq_base[wqe_idx].elem;
  2258. get_64bit_val(sw_wqe, 24, &wqe_qword);
  2259. cmpl->cpi.op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, IRDMAQPSQ_OPCODE);
  2260. cmpl->cpi.q_type = IRDMA_CQE_QTYPE_SQ;
  2261. /* remove the SQ WR by moving SQ tail*/
  2262. IRDMA_RING_SET_TAIL(*sq_ring,
  2263. sq_ring->tail + qp->sq_wrtrk_array[sq_ring->tail].quanta);
  2264. if (cmpl->cpi.op_type == IRDMAQP_OP_NOP) {
  2265. kfree(cmpl);
  2266. continue;
  2267. }
  2268. ibdev_dbg(iwqp->iwscq->ibcq.device,
  2269. "DEV: %s: adding wr_id = 0x%llx SQ Completion to list qp_id=%d\n",
  2270. __func__, cmpl->cpi.wr_id, qp->qp_id);
  2271. list_add_tail(&cmpl->list, &iwqp->iwscq->cmpl_generated);
  2272. compl_generated = true;
  2273. }
  2274. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2275. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2276. if (compl_generated)
  2277. irdma_comp_handler(iwqp->iwscq);
  2278. } else {
  2279. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2280. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2281. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2282. }
  2283. spin_lock_irqsave(&iwqp->iwrcq->lock, flags1);
  2284. if (irdma_cq_empty(iwqp->iwrcq)) {
  2285. unsigned long flags2;
  2286. spin_lock_irqsave(&iwqp->lock, flags2);
  2287. while (IRDMA_RING_MORE_WORK(*rq_ring)) {
  2288. cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC);
  2289. if (!cmpl) {
  2290. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2291. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2292. return;
  2293. }
  2294. wqe_idx = rq_ring->tail;
  2295. irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id);
  2296. cmpl->cpi.wr_id = qp->rq_wrid_array[wqe_idx];
  2297. cmpl->cpi.op_type = IRDMA_OP_TYPE_REC;
  2298. cmpl->cpi.q_type = IRDMA_CQE_QTYPE_RQ;
  2299. /* remove the RQ WR by moving RQ tail */
  2300. IRDMA_RING_SET_TAIL(*rq_ring, rq_ring->tail + 1);
  2301. ibdev_dbg(iwqp->iwrcq->ibcq.device,
  2302. "DEV: %s: adding wr_id = 0x%llx RQ Completion to list qp_id=%d, wqe_idx=%d\n",
  2303. __func__, cmpl->cpi.wr_id, qp->qp_id,
  2304. wqe_idx);
  2305. list_add_tail(&cmpl->list, &iwqp->iwrcq->cmpl_generated);
  2306. compl_generated = true;
  2307. }
  2308. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2309. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2310. if (compl_generated)
  2311. irdma_comp_handler(iwqp->iwrcq);
  2312. } else {
  2313. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2314. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2315. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2316. }
  2317. }