erdma_verbs.c 37 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Authors: Cheng Xu <[email protected]> */
  3. /* Kai Shen <[email protected]> */
  4. /* Copyright (c) 2020-2022, Alibaba Group. */
  5. /* Authors: Bernard Metzler <[email protected]> */
  6. /* Copyright (c) 2008-2019, IBM Corporation */
  7. /* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. */
  8. #include <linux/vmalloc.h>
  9. #include <net/addrconf.h>
  10. #include <rdma/erdma-abi.h>
  11. #include <rdma/ib_umem.h>
  12. #include <rdma/uverbs_ioctl.h>
  13. #include "erdma.h"
  14. #include "erdma_cm.h"
  15. #include "erdma_verbs.h"
  16. static int create_qp_cmd(struct erdma_dev *dev, struct erdma_qp *qp)
  17. {
  18. struct erdma_cmdq_create_qp_req req;
  19. struct erdma_pd *pd = to_epd(qp->ibqp.pd);
  20. struct erdma_uqp *user_qp;
  21. u64 resp0, resp1;
  22. int err;
  23. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA,
  24. CMDQ_OPCODE_CREATE_QP);
  25. req.cfg0 = FIELD_PREP(ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK,
  26. ilog2(qp->attrs.sq_size)) |
  27. FIELD_PREP(ERDMA_CMD_CREATE_QP_QPN_MASK, QP_ID(qp));
  28. req.cfg1 = FIELD_PREP(ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK,
  29. ilog2(qp->attrs.rq_size)) |
  30. FIELD_PREP(ERDMA_CMD_CREATE_QP_PD_MASK, pd->pdn);
  31. if (rdma_is_kernel_res(&qp->ibqp.res)) {
  32. u32 pgsz_range = ilog2(SZ_1M) - ERDMA_HW_PAGE_SHIFT;
  33. req.sq_cqn_mtt_cfg =
  34. FIELD_PREP(ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK,
  35. pgsz_range) |
  36. FIELD_PREP(ERDMA_CMD_CREATE_QP_CQN_MASK, qp->scq->cqn);
  37. req.rq_cqn_mtt_cfg =
  38. FIELD_PREP(ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK,
  39. pgsz_range) |
  40. FIELD_PREP(ERDMA_CMD_CREATE_QP_CQN_MASK, qp->rcq->cqn);
  41. req.sq_mtt_cfg =
  42. FIELD_PREP(ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK, 0) |
  43. FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_CNT_MASK, 1) |
  44. FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_TYPE_MASK,
  45. ERDMA_MR_INLINE_MTT);
  46. req.rq_mtt_cfg = req.sq_mtt_cfg;
  47. req.rq_buf_addr = qp->kern_qp.rq_buf_dma_addr;
  48. req.sq_buf_addr = qp->kern_qp.sq_buf_dma_addr;
  49. req.sq_db_info_dma_addr = qp->kern_qp.sq_buf_dma_addr +
  50. (qp->attrs.sq_size << SQEBB_SHIFT);
  51. req.rq_db_info_dma_addr = qp->kern_qp.rq_buf_dma_addr +
  52. (qp->attrs.rq_size << RQE_SHIFT);
  53. } else {
  54. user_qp = &qp->user_qp;
  55. req.sq_cqn_mtt_cfg = FIELD_PREP(
  56. ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK,
  57. ilog2(user_qp->sq_mtt.page_size) - ERDMA_HW_PAGE_SHIFT);
  58. req.sq_cqn_mtt_cfg |=
  59. FIELD_PREP(ERDMA_CMD_CREATE_QP_CQN_MASK, qp->scq->cqn);
  60. req.rq_cqn_mtt_cfg = FIELD_PREP(
  61. ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK,
  62. ilog2(user_qp->rq_mtt.page_size) - ERDMA_HW_PAGE_SHIFT);
  63. req.rq_cqn_mtt_cfg |=
  64. FIELD_PREP(ERDMA_CMD_CREATE_QP_CQN_MASK, qp->rcq->cqn);
  65. req.sq_mtt_cfg = user_qp->sq_mtt.page_offset;
  66. req.sq_mtt_cfg |= FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_CNT_MASK,
  67. user_qp->sq_mtt.mtt_nents) |
  68. FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_TYPE_MASK,
  69. user_qp->sq_mtt.mtt_type);
  70. req.rq_mtt_cfg = user_qp->rq_mtt.page_offset;
  71. req.rq_mtt_cfg |= FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_CNT_MASK,
  72. user_qp->rq_mtt.mtt_nents) |
  73. FIELD_PREP(ERDMA_CMD_CREATE_QP_MTT_TYPE_MASK,
  74. user_qp->rq_mtt.mtt_type);
  75. req.sq_buf_addr = user_qp->sq_mtt.mtt_entry[0];
  76. req.rq_buf_addr = user_qp->rq_mtt.mtt_entry[0];
  77. req.sq_db_info_dma_addr = user_qp->sq_db_info_dma_addr;
  78. req.rq_db_info_dma_addr = user_qp->rq_db_info_dma_addr;
  79. }
  80. err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &resp0,
  81. &resp1);
  82. if (!err)
  83. qp->attrs.cookie =
  84. FIELD_GET(ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK, resp0);
  85. return err;
  86. }
  87. static int regmr_cmd(struct erdma_dev *dev, struct erdma_mr *mr)
  88. {
  89. struct erdma_cmdq_reg_mr_req req;
  90. struct erdma_pd *pd = to_epd(mr->ibmr.pd);
  91. u64 *phy_addr;
  92. int i;
  93. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, CMDQ_OPCODE_REG_MR);
  94. req.cfg0 = FIELD_PREP(ERDMA_CMD_MR_VALID_MASK, mr->valid) |
  95. FIELD_PREP(ERDMA_CMD_MR_KEY_MASK, mr->ibmr.lkey & 0xFF) |
  96. FIELD_PREP(ERDMA_CMD_MR_MPT_IDX_MASK, mr->ibmr.lkey >> 8);
  97. req.cfg1 = FIELD_PREP(ERDMA_CMD_REGMR_PD_MASK, pd->pdn) |
  98. FIELD_PREP(ERDMA_CMD_REGMR_TYPE_MASK, mr->type) |
  99. FIELD_PREP(ERDMA_CMD_REGMR_RIGHT_MASK, mr->access) |
  100. FIELD_PREP(ERDMA_CMD_REGMR_ACC_MODE_MASK, 0);
  101. req.cfg2 = FIELD_PREP(ERDMA_CMD_REGMR_PAGESIZE_MASK,
  102. ilog2(mr->mem.page_size)) |
  103. FIELD_PREP(ERDMA_CMD_REGMR_MTT_TYPE_MASK, mr->mem.mtt_type) |
  104. FIELD_PREP(ERDMA_CMD_REGMR_MTT_CNT_MASK, mr->mem.page_cnt);
  105. if (mr->type == ERDMA_MR_TYPE_DMA)
  106. goto post_cmd;
  107. if (mr->type == ERDMA_MR_TYPE_NORMAL) {
  108. req.start_va = mr->mem.va;
  109. req.size = mr->mem.len;
  110. }
  111. if (mr->type == ERDMA_MR_TYPE_FRMR ||
  112. mr->mem.mtt_type == ERDMA_MR_INDIRECT_MTT) {
  113. phy_addr = req.phy_addr;
  114. *phy_addr = mr->mem.mtt_entry[0];
  115. } else {
  116. phy_addr = req.phy_addr;
  117. for (i = 0; i < mr->mem.mtt_nents; i++)
  118. *phy_addr++ = mr->mem.mtt_entry[i];
  119. }
  120. post_cmd:
  121. return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  122. }
  123. static int create_cq_cmd(struct erdma_dev *dev, struct erdma_cq *cq)
  124. {
  125. struct erdma_cmdq_create_cq_req req;
  126. u32 page_size;
  127. struct erdma_mem *mtt;
  128. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA,
  129. CMDQ_OPCODE_CREATE_CQ);
  130. req.cfg0 = FIELD_PREP(ERDMA_CMD_CREATE_CQ_CQN_MASK, cq->cqn) |
  131. FIELD_PREP(ERDMA_CMD_CREATE_CQ_DEPTH_MASK, ilog2(cq->depth));
  132. req.cfg1 = FIELD_PREP(ERDMA_CMD_CREATE_CQ_EQN_MASK, cq->assoc_eqn);
  133. if (rdma_is_kernel_res(&cq->ibcq.res)) {
  134. page_size = SZ_32M;
  135. req.cfg0 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK,
  136. ilog2(page_size) - ERDMA_HW_PAGE_SHIFT);
  137. req.qbuf_addr_l = lower_32_bits(cq->kern_cq.qbuf_dma_addr);
  138. req.qbuf_addr_h = upper_32_bits(cq->kern_cq.qbuf_dma_addr);
  139. req.cfg1 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK, 1) |
  140. FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_TYPE_MASK,
  141. ERDMA_MR_INLINE_MTT);
  142. req.first_page_offset = 0;
  143. req.cq_db_info_addr =
  144. cq->kern_cq.qbuf_dma_addr + (cq->depth << CQE_SHIFT);
  145. } else {
  146. mtt = &cq->user_cq.qbuf_mtt;
  147. req.cfg0 |=
  148. FIELD_PREP(ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK,
  149. ilog2(mtt->page_size) - ERDMA_HW_PAGE_SHIFT);
  150. if (mtt->mtt_nents == 1) {
  151. req.qbuf_addr_l = lower_32_bits(*(u64 *)mtt->mtt_buf);
  152. req.qbuf_addr_h = upper_32_bits(*(u64 *)mtt->mtt_buf);
  153. } else {
  154. req.qbuf_addr_l = lower_32_bits(mtt->mtt_entry[0]);
  155. req.qbuf_addr_h = upper_32_bits(mtt->mtt_entry[0]);
  156. }
  157. req.cfg1 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK,
  158. mtt->mtt_nents);
  159. req.cfg1 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_TYPE_MASK,
  160. mtt->mtt_type);
  161. req.first_page_offset = mtt->page_offset;
  162. req.cq_db_info_addr = cq->user_cq.db_info_dma_addr;
  163. }
  164. return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  165. }
  166. static int erdma_alloc_idx(struct erdma_resource_cb *res_cb)
  167. {
  168. int idx;
  169. unsigned long flags;
  170. spin_lock_irqsave(&res_cb->lock, flags);
  171. idx = find_next_zero_bit(res_cb->bitmap, res_cb->max_cap,
  172. res_cb->next_alloc_idx);
  173. if (idx == res_cb->max_cap) {
  174. idx = find_first_zero_bit(res_cb->bitmap, res_cb->max_cap);
  175. if (idx == res_cb->max_cap) {
  176. res_cb->next_alloc_idx = 1;
  177. spin_unlock_irqrestore(&res_cb->lock, flags);
  178. return -ENOSPC;
  179. }
  180. }
  181. set_bit(idx, res_cb->bitmap);
  182. res_cb->next_alloc_idx = idx + 1;
  183. spin_unlock_irqrestore(&res_cb->lock, flags);
  184. return idx;
  185. }
  186. static inline void erdma_free_idx(struct erdma_resource_cb *res_cb, u32 idx)
  187. {
  188. unsigned long flags;
  189. u32 used;
  190. spin_lock_irqsave(&res_cb->lock, flags);
  191. used = __test_and_clear_bit(idx, res_cb->bitmap);
  192. spin_unlock_irqrestore(&res_cb->lock, flags);
  193. WARN_ON(!used);
  194. }
  195. static struct rdma_user_mmap_entry *
  196. erdma_user_mmap_entry_insert(struct erdma_ucontext *uctx, void *address,
  197. u32 size, u8 mmap_flag, u64 *mmap_offset)
  198. {
  199. struct erdma_user_mmap_entry *entry =
  200. kzalloc(sizeof(*entry), GFP_KERNEL);
  201. int ret;
  202. if (!entry)
  203. return NULL;
  204. entry->address = (u64)address;
  205. entry->mmap_flag = mmap_flag;
  206. size = PAGE_ALIGN(size);
  207. ret = rdma_user_mmap_entry_insert(&uctx->ibucontext, &entry->rdma_entry,
  208. size);
  209. if (ret) {
  210. kfree(entry);
  211. return NULL;
  212. }
  213. *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
  214. return &entry->rdma_entry;
  215. }
  216. int erdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr,
  217. struct ib_udata *unused)
  218. {
  219. struct erdma_dev *dev = to_edev(ibdev);
  220. memset(attr, 0, sizeof(*attr));
  221. attr->max_mr_size = dev->attrs.max_mr_size;
  222. attr->vendor_id = PCI_VENDOR_ID_ALIBABA;
  223. attr->vendor_part_id = dev->pdev->device;
  224. attr->hw_ver = dev->pdev->revision;
  225. attr->max_qp = dev->attrs.max_qp - 1;
  226. attr->max_qp_wr = min(dev->attrs.max_send_wr, dev->attrs.max_recv_wr);
  227. attr->max_qp_rd_atom = dev->attrs.max_ord;
  228. attr->max_qp_init_rd_atom = dev->attrs.max_ird;
  229. attr->max_res_rd_atom = dev->attrs.max_qp * dev->attrs.max_ird;
  230. attr->device_cap_flags = IB_DEVICE_MEM_MGT_EXTENSIONS;
  231. attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
  232. ibdev->local_dma_lkey = dev->attrs.local_dma_key;
  233. attr->max_send_sge = dev->attrs.max_send_sge;
  234. attr->max_recv_sge = dev->attrs.max_recv_sge;
  235. attr->max_sge_rd = dev->attrs.max_sge_rd;
  236. attr->max_cq = dev->attrs.max_cq - 1;
  237. attr->max_cqe = dev->attrs.max_cqe;
  238. attr->max_mr = dev->attrs.max_mr;
  239. attr->max_pd = dev->attrs.max_pd;
  240. attr->max_mw = dev->attrs.max_mw;
  241. attr->max_fast_reg_page_list_len = ERDMA_MAX_FRMR_PA;
  242. attr->page_size_cap = ERDMA_PAGE_SIZE_SUPPORT;
  243. attr->fw_ver = dev->attrs.fw_version;
  244. if (dev->netdev)
  245. addrconf_addr_eui48((u8 *)&attr->sys_image_guid,
  246. dev->netdev->dev_addr);
  247. return 0;
  248. }
  249. int erdma_query_gid(struct ib_device *ibdev, u32 port, int idx,
  250. union ib_gid *gid)
  251. {
  252. struct erdma_dev *dev = to_edev(ibdev);
  253. memset(gid, 0, sizeof(*gid));
  254. ether_addr_copy(gid->raw, dev->attrs.peer_addr);
  255. return 0;
  256. }
  257. int erdma_query_port(struct ib_device *ibdev, u32 port,
  258. struct ib_port_attr *attr)
  259. {
  260. struct erdma_dev *dev = to_edev(ibdev);
  261. struct net_device *ndev = dev->netdev;
  262. memset(attr, 0, sizeof(*attr));
  263. attr->gid_tbl_len = 1;
  264. attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP;
  265. attr->max_msg_sz = -1;
  266. if (!ndev)
  267. goto out;
  268. ib_get_eth_speed(ibdev, port, &attr->active_speed, &attr->active_width);
  269. attr->max_mtu = ib_mtu_int_to_enum(ndev->mtu);
  270. attr->active_mtu = ib_mtu_int_to_enum(ndev->mtu);
  271. if (netif_running(ndev) && netif_carrier_ok(ndev))
  272. dev->state = IB_PORT_ACTIVE;
  273. else
  274. dev->state = IB_PORT_DOWN;
  275. attr->state = dev->state;
  276. out:
  277. if (dev->state == IB_PORT_ACTIVE)
  278. attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
  279. else
  280. attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
  281. return 0;
  282. }
  283. int erdma_get_port_immutable(struct ib_device *ibdev, u32 port,
  284. struct ib_port_immutable *port_immutable)
  285. {
  286. port_immutable->gid_tbl_len = 1;
  287. port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  288. return 0;
  289. }
  290. int erdma_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  291. {
  292. struct erdma_pd *pd = to_epd(ibpd);
  293. struct erdma_dev *dev = to_edev(ibpd->device);
  294. int pdn;
  295. pdn = erdma_alloc_idx(&dev->res_cb[ERDMA_RES_TYPE_PD]);
  296. if (pdn < 0)
  297. return pdn;
  298. pd->pdn = pdn;
  299. return 0;
  300. }
  301. int erdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  302. {
  303. struct erdma_pd *pd = to_epd(ibpd);
  304. struct erdma_dev *dev = to_edev(ibpd->device);
  305. erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_PD], pd->pdn);
  306. return 0;
  307. }
  308. static int erdma_qp_validate_cap(struct erdma_dev *dev,
  309. struct ib_qp_init_attr *attrs)
  310. {
  311. if ((attrs->cap.max_send_wr > dev->attrs.max_send_wr) ||
  312. (attrs->cap.max_recv_wr > dev->attrs.max_recv_wr) ||
  313. (attrs->cap.max_send_sge > dev->attrs.max_send_sge) ||
  314. (attrs->cap.max_recv_sge > dev->attrs.max_recv_sge) ||
  315. (attrs->cap.max_inline_data > ERDMA_MAX_INLINE) ||
  316. !attrs->cap.max_send_wr || !attrs->cap.max_recv_wr) {
  317. return -EINVAL;
  318. }
  319. return 0;
  320. }
  321. static int erdma_qp_validate_attr(struct erdma_dev *dev,
  322. struct ib_qp_init_attr *attrs)
  323. {
  324. if (attrs->qp_type != IB_QPT_RC)
  325. return -EOPNOTSUPP;
  326. if (attrs->srq)
  327. return -EOPNOTSUPP;
  328. if (!attrs->send_cq || !attrs->recv_cq)
  329. return -EOPNOTSUPP;
  330. return 0;
  331. }
  332. static void free_kernel_qp(struct erdma_qp *qp)
  333. {
  334. struct erdma_dev *dev = qp->dev;
  335. vfree(qp->kern_qp.swr_tbl);
  336. vfree(qp->kern_qp.rwr_tbl);
  337. if (qp->kern_qp.sq_buf)
  338. dma_free_coherent(
  339. &dev->pdev->dev,
  340. WARPPED_BUFSIZE(qp->attrs.sq_size << SQEBB_SHIFT),
  341. qp->kern_qp.sq_buf, qp->kern_qp.sq_buf_dma_addr);
  342. if (qp->kern_qp.rq_buf)
  343. dma_free_coherent(
  344. &dev->pdev->dev,
  345. WARPPED_BUFSIZE(qp->attrs.rq_size << RQE_SHIFT),
  346. qp->kern_qp.rq_buf, qp->kern_qp.rq_buf_dma_addr);
  347. }
  348. static int init_kernel_qp(struct erdma_dev *dev, struct erdma_qp *qp,
  349. struct ib_qp_init_attr *attrs)
  350. {
  351. struct erdma_kqp *kqp = &qp->kern_qp;
  352. int size;
  353. if (attrs->sq_sig_type == IB_SIGNAL_ALL_WR)
  354. kqp->sig_all = 1;
  355. kqp->sq_pi = 0;
  356. kqp->sq_ci = 0;
  357. kqp->rq_pi = 0;
  358. kqp->rq_ci = 0;
  359. kqp->hw_sq_db =
  360. dev->func_bar + (ERDMA_SDB_SHARED_PAGE_INDEX << PAGE_SHIFT);
  361. kqp->hw_rq_db = dev->func_bar + ERDMA_BAR_RQDB_SPACE_OFFSET;
  362. kqp->swr_tbl = vmalloc(qp->attrs.sq_size * sizeof(u64));
  363. kqp->rwr_tbl = vmalloc(qp->attrs.rq_size * sizeof(u64));
  364. if (!kqp->swr_tbl || !kqp->rwr_tbl)
  365. goto err_out;
  366. size = (qp->attrs.sq_size << SQEBB_SHIFT) + ERDMA_EXTRA_BUFFER_SIZE;
  367. kqp->sq_buf = dma_alloc_coherent(&dev->pdev->dev, size,
  368. &kqp->sq_buf_dma_addr, GFP_KERNEL);
  369. if (!kqp->sq_buf)
  370. goto err_out;
  371. size = (qp->attrs.rq_size << RQE_SHIFT) + ERDMA_EXTRA_BUFFER_SIZE;
  372. kqp->rq_buf = dma_alloc_coherent(&dev->pdev->dev, size,
  373. &kqp->rq_buf_dma_addr, GFP_KERNEL);
  374. if (!kqp->rq_buf)
  375. goto err_out;
  376. kqp->sq_db_info = kqp->sq_buf + (qp->attrs.sq_size << SQEBB_SHIFT);
  377. kqp->rq_db_info = kqp->rq_buf + (qp->attrs.rq_size << RQE_SHIFT);
  378. return 0;
  379. err_out:
  380. free_kernel_qp(qp);
  381. return -ENOMEM;
  382. }
  383. static int get_mtt_entries(struct erdma_dev *dev, struct erdma_mem *mem,
  384. u64 start, u64 len, int access, u64 virt,
  385. unsigned long req_page_size, u8 force_indirect_mtt)
  386. {
  387. struct ib_block_iter biter;
  388. uint64_t *phy_addr = NULL;
  389. int ret = 0;
  390. mem->umem = ib_umem_get(&dev->ibdev, start, len, access);
  391. if (IS_ERR(mem->umem)) {
  392. ret = PTR_ERR(mem->umem);
  393. mem->umem = NULL;
  394. return ret;
  395. }
  396. mem->va = virt;
  397. mem->len = len;
  398. mem->page_size = ib_umem_find_best_pgsz(mem->umem, req_page_size, virt);
  399. mem->page_offset = start & (mem->page_size - 1);
  400. mem->mtt_nents = ib_umem_num_dma_blocks(mem->umem, mem->page_size);
  401. mem->page_cnt = mem->mtt_nents;
  402. if (mem->page_cnt > ERDMA_MAX_INLINE_MTT_ENTRIES ||
  403. force_indirect_mtt) {
  404. mem->mtt_type = ERDMA_MR_INDIRECT_MTT;
  405. mem->mtt_buf =
  406. alloc_pages_exact(MTT_SIZE(mem->page_cnt), GFP_KERNEL);
  407. if (!mem->mtt_buf) {
  408. ret = -ENOMEM;
  409. goto error_ret;
  410. }
  411. phy_addr = mem->mtt_buf;
  412. } else {
  413. mem->mtt_type = ERDMA_MR_INLINE_MTT;
  414. phy_addr = mem->mtt_entry;
  415. }
  416. rdma_umem_for_each_dma_block(mem->umem, &biter, mem->page_size) {
  417. *phy_addr = rdma_block_iter_dma_address(&biter);
  418. phy_addr++;
  419. }
  420. if (mem->mtt_type == ERDMA_MR_INDIRECT_MTT) {
  421. mem->mtt_entry[0] =
  422. dma_map_single(&dev->pdev->dev, mem->mtt_buf,
  423. MTT_SIZE(mem->page_cnt), DMA_TO_DEVICE);
  424. if (dma_mapping_error(&dev->pdev->dev, mem->mtt_entry[0])) {
  425. free_pages_exact(mem->mtt_buf, MTT_SIZE(mem->page_cnt));
  426. mem->mtt_buf = NULL;
  427. ret = -ENOMEM;
  428. goto error_ret;
  429. }
  430. }
  431. return 0;
  432. error_ret:
  433. if (mem->umem) {
  434. ib_umem_release(mem->umem);
  435. mem->umem = NULL;
  436. }
  437. return ret;
  438. }
  439. static void put_mtt_entries(struct erdma_dev *dev, struct erdma_mem *mem)
  440. {
  441. if (mem->mtt_buf) {
  442. dma_unmap_single(&dev->pdev->dev, mem->mtt_entry[0],
  443. MTT_SIZE(mem->page_cnt), DMA_TO_DEVICE);
  444. free_pages_exact(mem->mtt_buf, MTT_SIZE(mem->page_cnt));
  445. }
  446. if (mem->umem) {
  447. ib_umem_release(mem->umem);
  448. mem->umem = NULL;
  449. }
  450. }
  451. static int erdma_map_user_dbrecords(struct erdma_ucontext *ctx,
  452. u64 dbrecords_va,
  453. struct erdma_user_dbrecords_page **dbr_page,
  454. dma_addr_t *dma_addr)
  455. {
  456. struct erdma_user_dbrecords_page *page = NULL;
  457. int rv = 0;
  458. mutex_lock(&ctx->dbrecords_page_mutex);
  459. list_for_each_entry(page, &ctx->dbrecords_page_list, list)
  460. if (page->va == (dbrecords_va & PAGE_MASK))
  461. goto found;
  462. page = kmalloc(sizeof(*page), GFP_KERNEL);
  463. if (!page) {
  464. rv = -ENOMEM;
  465. goto out;
  466. }
  467. page->va = (dbrecords_va & PAGE_MASK);
  468. page->refcnt = 0;
  469. page->umem = ib_umem_get(ctx->ibucontext.device,
  470. dbrecords_va & PAGE_MASK, PAGE_SIZE, 0);
  471. if (IS_ERR(page->umem)) {
  472. rv = PTR_ERR(page->umem);
  473. kfree(page);
  474. goto out;
  475. }
  476. list_add(&page->list, &ctx->dbrecords_page_list);
  477. found:
  478. *dma_addr = sg_dma_address(page->umem->sgt_append.sgt.sgl) +
  479. (dbrecords_va & ~PAGE_MASK);
  480. *dbr_page = page;
  481. page->refcnt++;
  482. out:
  483. mutex_unlock(&ctx->dbrecords_page_mutex);
  484. return rv;
  485. }
  486. static void
  487. erdma_unmap_user_dbrecords(struct erdma_ucontext *ctx,
  488. struct erdma_user_dbrecords_page **dbr_page)
  489. {
  490. if (!ctx || !(*dbr_page))
  491. return;
  492. mutex_lock(&ctx->dbrecords_page_mutex);
  493. if (--(*dbr_page)->refcnt == 0) {
  494. list_del(&(*dbr_page)->list);
  495. ib_umem_release((*dbr_page)->umem);
  496. kfree(*dbr_page);
  497. }
  498. *dbr_page = NULL;
  499. mutex_unlock(&ctx->dbrecords_page_mutex);
  500. }
  501. static int init_user_qp(struct erdma_qp *qp, struct erdma_ucontext *uctx,
  502. u64 va, u32 len, u64 db_info_va)
  503. {
  504. dma_addr_t db_info_dma_addr;
  505. u32 rq_offset;
  506. int ret;
  507. if (len < (ALIGN(qp->attrs.sq_size * SQEBB_SIZE, ERDMA_HW_PAGE_SIZE) +
  508. qp->attrs.rq_size * RQE_SIZE))
  509. return -EINVAL;
  510. ret = get_mtt_entries(qp->dev, &qp->user_qp.sq_mtt, va,
  511. qp->attrs.sq_size << SQEBB_SHIFT, 0, va,
  512. (SZ_1M - SZ_4K), 1);
  513. if (ret)
  514. return ret;
  515. rq_offset = ALIGN(qp->attrs.sq_size << SQEBB_SHIFT, ERDMA_HW_PAGE_SIZE);
  516. qp->user_qp.rq_offset = rq_offset;
  517. ret = get_mtt_entries(qp->dev, &qp->user_qp.rq_mtt, va + rq_offset,
  518. qp->attrs.rq_size << RQE_SHIFT, 0, va + rq_offset,
  519. (SZ_1M - SZ_4K), 1);
  520. if (ret)
  521. goto put_sq_mtt;
  522. ret = erdma_map_user_dbrecords(uctx, db_info_va,
  523. &qp->user_qp.user_dbr_page,
  524. &db_info_dma_addr);
  525. if (ret)
  526. goto put_rq_mtt;
  527. qp->user_qp.sq_db_info_dma_addr = db_info_dma_addr;
  528. qp->user_qp.rq_db_info_dma_addr = db_info_dma_addr + ERDMA_DB_SIZE;
  529. return 0;
  530. put_rq_mtt:
  531. put_mtt_entries(qp->dev, &qp->user_qp.rq_mtt);
  532. put_sq_mtt:
  533. put_mtt_entries(qp->dev, &qp->user_qp.sq_mtt);
  534. return ret;
  535. }
  536. static void free_user_qp(struct erdma_qp *qp, struct erdma_ucontext *uctx)
  537. {
  538. put_mtt_entries(qp->dev, &qp->user_qp.sq_mtt);
  539. put_mtt_entries(qp->dev, &qp->user_qp.rq_mtt);
  540. erdma_unmap_user_dbrecords(uctx, &qp->user_qp.user_dbr_page);
  541. }
  542. int erdma_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,
  543. struct ib_udata *udata)
  544. {
  545. struct erdma_qp *qp = to_eqp(ibqp);
  546. struct erdma_dev *dev = to_edev(ibqp->device);
  547. struct erdma_ucontext *uctx = rdma_udata_to_drv_context(
  548. udata, struct erdma_ucontext, ibucontext);
  549. struct erdma_ureq_create_qp ureq;
  550. struct erdma_uresp_create_qp uresp;
  551. int ret;
  552. ret = erdma_qp_validate_cap(dev, attrs);
  553. if (ret)
  554. goto err_out;
  555. ret = erdma_qp_validate_attr(dev, attrs);
  556. if (ret)
  557. goto err_out;
  558. qp->scq = to_ecq(attrs->send_cq);
  559. qp->rcq = to_ecq(attrs->recv_cq);
  560. qp->dev = dev;
  561. qp->attrs.cc = dev->attrs.cc;
  562. init_rwsem(&qp->state_lock);
  563. kref_init(&qp->ref);
  564. init_completion(&qp->safe_free);
  565. ret = xa_alloc_cyclic(&dev->qp_xa, &qp->ibqp.qp_num, qp,
  566. XA_LIMIT(1, dev->attrs.max_qp - 1),
  567. &dev->next_alloc_qpn, GFP_KERNEL);
  568. if (ret < 0) {
  569. ret = -ENOMEM;
  570. goto err_out;
  571. }
  572. qp->attrs.sq_size = roundup_pow_of_two(attrs->cap.max_send_wr *
  573. ERDMA_MAX_WQEBB_PER_SQE);
  574. qp->attrs.rq_size = roundup_pow_of_two(attrs->cap.max_recv_wr);
  575. if (uctx) {
  576. ret = ib_copy_from_udata(&ureq, udata,
  577. min(sizeof(ureq), udata->inlen));
  578. if (ret)
  579. goto err_out_xa;
  580. ret = init_user_qp(qp, uctx, ureq.qbuf_va, ureq.qbuf_len,
  581. ureq.db_record_va);
  582. if (ret)
  583. goto err_out_xa;
  584. memset(&uresp, 0, sizeof(uresp));
  585. uresp.num_sqe = qp->attrs.sq_size;
  586. uresp.num_rqe = qp->attrs.rq_size;
  587. uresp.qp_id = QP_ID(qp);
  588. uresp.rq_offset = qp->user_qp.rq_offset;
  589. ret = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  590. if (ret)
  591. goto err_out_cmd;
  592. } else {
  593. init_kernel_qp(dev, qp, attrs);
  594. }
  595. qp->attrs.max_send_sge = attrs->cap.max_send_sge;
  596. qp->attrs.max_recv_sge = attrs->cap.max_recv_sge;
  597. qp->attrs.state = ERDMA_QP_STATE_IDLE;
  598. ret = create_qp_cmd(dev, qp);
  599. if (ret)
  600. goto err_out_cmd;
  601. spin_lock_init(&qp->lock);
  602. return 0;
  603. err_out_cmd:
  604. if (uctx)
  605. free_user_qp(qp, uctx);
  606. else
  607. free_kernel_qp(qp);
  608. err_out_xa:
  609. xa_erase(&dev->qp_xa, QP_ID(qp));
  610. err_out:
  611. return ret;
  612. }
  613. static int erdma_create_stag(struct erdma_dev *dev, u32 *stag)
  614. {
  615. int stag_idx;
  616. stag_idx = erdma_alloc_idx(&dev->res_cb[ERDMA_RES_TYPE_STAG_IDX]);
  617. if (stag_idx < 0)
  618. return stag_idx;
  619. /* For now, we always let key field be zero. */
  620. *stag = (stag_idx << 8);
  621. return 0;
  622. }
  623. struct ib_mr *erdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  624. {
  625. struct erdma_dev *dev = to_edev(ibpd->device);
  626. struct erdma_mr *mr;
  627. u32 stag;
  628. int ret;
  629. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  630. if (!mr)
  631. return ERR_PTR(-ENOMEM);
  632. ret = erdma_create_stag(dev, &stag);
  633. if (ret)
  634. goto out_free;
  635. mr->type = ERDMA_MR_TYPE_DMA;
  636. mr->ibmr.lkey = stag;
  637. mr->ibmr.rkey = stag;
  638. mr->ibmr.pd = ibpd;
  639. mr->access = ERDMA_MR_ACC_LR | to_erdma_access_flags(acc);
  640. ret = regmr_cmd(dev, mr);
  641. if (ret)
  642. goto out_remove_stag;
  643. return &mr->ibmr;
  644. out_remove_stag:
  645. erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_STAG_IDX],
  646. mr->ibmr.lkey >> 8);
  647. out_free:
  648. kfree(mr);
  649. return ERR_PTR(ret);
  650. }
  651. struct ib_mr *erdma_ib_alloc_mr(struct ib_pd *ibpd, enum ib_mr_type mr_type,
  652. u32 max_num_sg)
  653. {
  654. struct erdma_mr *mr;
  655. struct erdma_dev *dev = to_edev(ibpd->device);
  656. int ret;
  657. u32 stag;
  658. if (mr_type != IB_MR_TYPE_MEM_REG)
  659. return ERR_PTR(-EOPNOTSUPP);
  660. if (max_num_sg > ERDMA_MR_MAX_MTT_CNT)
  661. return ERR_PTR(-EINVAL);
  662. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  663. if (!mr)
  664. return ERR_PTR(-ENOMEM);
  665. ret = erdma_create_stag(dev, &stag);
  666. if (ret)
  667. goto out_free;
  668. mr->type = ERDMA_MR_TYPE_FRMR;
  669. mr->ibmr.lkey = stag;
  670. mr->ibmr.rkey = stag;
  671. mr->ibmr.pd = ibpd;
  672. /* update it in FRMR. */
  673. mr->access = ERDMA_MR_ACC_LR | ERDMA_MR_ACC_LW | ERDMA_MR_ACC_RR |
  674. ERDMA_MR_ACC_RW;
  675. mr->mem.page_size = PAGE_SIZE; /* update it later. */
  676. mr->mem.page_cnt = max_num_sg;
  677. mr->mem.mtt_type = ERDMA_MR_INDIRECT_MTT;
  678. mr->mem.mtt_buf =
  679. alloc_pages_exact(MTT_SIZE(mr->mem.page_cnt), GFP_KERNEL);
  680. if (!mr->mem.mtt_buf) {
  681. ret = -ENOMEM;
  682. goto out_remove_stag;
  683. }
  684. mr->mem.mtt_entry[0] =
  685. dma_map_single(&dev->pdev->dev, mr->mem.mtt_buf,
  686. MTT_SIZE(mr->mem.page_cnt), DMA_TO_DEVICE);
  687. if (dma_mapping_error(&dev->pdev->dev, mr->mem.mtt_entry[0])) {
  688. ret = -ENOMEM;
  689. goto out_free_mtt;
  690. }
  691. ret = regmr_cmd(dev, mr);
  692. if (ret)
  693. goto out_dma_unmap;
  694. return &mr->ibmr;
  695. out_dma_unmap:
  696. dma_unmap_single(&dev->pdev->dev, mr->mem.mtt_entry[0],
  697. MTT_SIZE(mr->mem.page_cnt), DMA_TO_DEVICE);
  698. out_free_mtt:
  699. free_pages_exact(mr->mem.mtt_buf, MTT_SIZE(mr->mem.page_cnt));
  700. out_remove_stag:
  701. erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_STAG_IDX],
  702. mr->ibmr.lkey >> 8);
  703. out_free:
  704. kfree(mr);
  705. return ERR_PTR(ret);
  706. }
  707. static int erdma_set_page(struct ib_mr *ibmr, u64 addr)
  708. {
  709. struct erdma_mr *mr = to_emr(ibmr);
  710. if (mr->mem.mtt_nents >= mr->mem.page_cnt)
  711. return -1;
  712. *((u64 *)mr->mem.mtt_buf + mr->mem.mtt_nents) = addr;
  713. mr->mem.mtt_nents++;
  714. return 0;
  715. }
  716. int erdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
  717. unsigned int *sg_offset)
  718. {
  719. struct erdma_mr *mr = to_emr(ibmr);
  720. int num;
  721. mr->mem.mtt_nents = 0;
  722. num = ib_sg_to_pages(&mr->ibmr, sg, sg_nents, sg_offset,
  723. erdma_set_page);
  724. return num;
  725. }
  726. struct ib_mr *erdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  727. u64 virt, int access, struct ib_udata *udata)
  728. {
  729. struct erdma_mr *mr = NULL;
  730. struct erdma_dev *dev = to_edev(ibpd->device);
  731. u32 stag;
  732. int ret;
  733. if (!len || len > dev->attrs.max_mr_size)
  734. return ERR_PTR(-EINVAL);
  735. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  736. if (!mr)
  737. return ERR_PTR(-ENOMEM);
  738. ret = get_mtt_entries(dev, &mr->mem, start, len, access, virt,
  739. SZ_2G - SZ_4K, 0);
  740. if (ret)
  741. goto err_out_free;
  742. ret = erdma_create_stag(dev, &stag);
  743. if (ret)
  744. goto err_out_put_mtt;
  745. mr->ibmr.lkey = mr->ibmr.rkey = stag;
  746. mr->ibmr.pd = ibpd;
  747. mr->mem.va = virt;
  748. mr->mem.len = len;
  749. mr->access = ERDMA_MR_ACC_LR | to_erdma_access_flags(access);
  750. mr->valid = 1;
  751. mr->type = ERDMA_MR_TYPE_NORMAL;
  752. ret = regmr_cmd(dev, mr);
  753. if (ret)
  754. goto err_out_mr;
  755. return &mr->ibmr;
  756. err_out_mr:
  757. erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_STAG_IDX],
  758. mr->ibmr.lkey >> 8);
  759. err_out_put_mtt:
  760. put_mtt_entries(dev, &mr->mem);
  761. err_out_free:
  762. kfree(mr);
  763. return ERR_PTR(ret);
  764. }
  765. int erdma_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
  766. {
  767. struct erdma_mr *mr;
  768. struct erdma_dev *dev = to_edev(ibmr->device);
  769. struct erdma_cmdq_dereg_mr_req req;
  770. int ret;
  771. mr = to_emr(ibmr);
  772. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA,
  773. CMDQ_OPCODE_DEREG_MR);
  774. req.cfg = FIELD_PREP(ERDMA_CMD_MR_MPT_IDX_MASK, ibmr->lkey >> 8) |
  775. FIELD_PREP(ERDMA_CMD_MR_KEY_MASK, ibmr->lkey & 0xFF);
  776. ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  777. if (ret)
  778. return ret;
  779. erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_STAG_IDX], ibmr->lkey >> 8);
  780. put_mtt_entries(dev, &mr->mem);
  781. kfree(mr);
  782. return 0;
  783. }
  784. int erdma_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
  785. {
  786. struct erdma_cq *cq = to_ecq(ibcq);
  787. struct erdma_dev *dev = to_edev(ibcq->device);
  788. struct erdma_ucontext *ctx = rdma_udata_to_drv_context(
  789. udata, struct erdma_ucontext, ibucontext);
  790. int err;
  791. struct erdma_cmdq_destroy_cq_req req;
  792. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA,
  793. CMDQ_OPCODE_DESTROY_CQ);
  794. req.cqn = cq->cqn;
  795. err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  796. if (err)
  797. return err;
  798. if (rdma_is_kernel_res(&cq->ibcq.res)) {
  799. dma_free_coherent(&dev->pdev->dev,
  800. WARPPED_BUFSIZE(cq->depth << CQE_SHIFT),
  801. cq->kern_cq.qbuf, cq->kern_cq.qbuf_dma_addr);
  802. } else {
  803. erdma_unmap_user_dbrecords(ctx, &cq->user_cq.user_dbr_page);
  804. put_mtt_entries(dev, &cq->user_cq.qbuf_mtt);
  805. }
  806. xa_erase(&dev->cq_xa, cq->cqn);
  807. return 0;
  808. }
  809. int erdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
  810. {
  811. struct erdma_qp *qp = to_eqp(ibqp);
  812. struct erdma_dev *dev = to_edev(ibqp->device);
  813. struct erdma_ucontext *ctx = rdma_udata_to_drv_context(
  814. udata, struct erdma_ucontext, ibucontext);
  815. struct erdma_qp_attrs qp_attrs;
  816. int err;
  817. struct erdma_cmdq_destroy_qp_req req;
  818. down_write(&qp->state_lock);
  819. qp_attrs.state = ERDMA_QP_STATE_ERROR;
  820. erdma_modify_qp_internal(qp, &qp_attrs, ERDMA_QP_ATTR_STATE);
  821. up_write(&qp->state_lock);
  822. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA,
  823. CMDQ_OPCODE_DESTROY_QP);
  824. req.qpn = QP_ID(qp);
  825. err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  826. if (err)
  827. return err;
  828. erdma_qp_put(qp);
  829. wait_for_completion(&qp->safe_free);
  830. if (rdma_is_kernel_res(&qp->ibqp.res)) {
  831. vfree(qp->kern_qp.swr_tbl);
  832. vfree(qp->kern_qp.rwr_tbl);
  833. dma_free_coherent(
  834. &dev->pdev->dev,
  835. WARPPED_BUFSIZE(qp->attrs.rq_size << RQE_SHIFT),
  836. qp->kern_qp.rq_buf, qp->kern_qp.rq_buf_dma_addr);
  837. dma_free_coherent(
  838. &dev->pdev->dev,
  839. WARPPED_BUFSIZE(qp->attrs.sq_size << SQEBB_SHIFT),
  840. qp->kern_qp.sq_buf, qp->kern_qp.sq_buf_dma_addr);
  841. } else {
  842. put_mtt_entries(dev, &qp->user_qp.sq_mtt);
  843. put_mtt_entries(dev, &qp->user_qp.rq_mtt);
  844. erdma_unmap_user_dbrecords(ctx, &qp->user_qp.user_dbr_page);
  845. }
  846. if (qp->cep)
  847. erdma_cep_put(qp->cep);
  848. xa_erase(&dev->qp_xa, QP_ID(qp));
  849. return 0;
  850. }
  851. void erdma_qp_get_ref(struct ib_qp *ibqp)
  852. {
  853. erdma_qp_get(to_eqp(ibqp));
  854. }
  855. void erdma_qp_put_ref(struct ib_qp *ibqp)
  856. {
  857. erdma_qp_put(to_eqp(ibqp));
  858. }
  859. int erdma_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma)
  860. {
  861. struct rdma_user_mmap_entry *rdma_entry;
  862. struct erdma_user_mmap_entry *entry;
  863. pgprot_t prot;
  864. int err;
  865. rdma_entry = rdma_user_mmap_entry_get(ctx, vma);
  866. if (!rdma_entry)
  867. return -EINVAL;
  868. entry = to_emmap(rdma_entry);
  869. switch (entry->mmap_flag) {
  870. case ERDMA_MMAP_IO_NC:
  871. /* map doorbell. */
  872. prot = pgprot_device(vma->vm_page_prot);
  873. break;
  874. default:
  875. err = -EINVAL;
  876. goto put_entry;
  877. }
  878. err = rdma_user_mmap_io(ctx, vma, PFN_DOWN(entry->address), PAGE_SIZE,
  879. prot, rdma_entry);
  880. put_entry:
  881. rdma_user_mmap_entry_put(rdma_entry);
  882. return err;
  883. }
  884. void erdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
  885. {
  886. struct erdma_user_mmap_entry *entry = to_emmap(rdma_entry);
  887. kfree(entry);
  888. }
  889. #define ERDMA_SDB_PAGE 0
  890. #define ERDMA_SDB_ENTRY 1
  891. #define ERDMA_SDB_SHARED 2
  892. static void alloc_db_resources(struct erdma_dev *dev,
  893. struct erdma_ucontext *ctx)
  894. {
  895. u32 bitmap_idx;
  896. struct erdma_devattr *attrs = &dev->attrs;
  897. if (attrs->disable_dwqe)
  898. goto alloc_normal_db;
  899. /* Try to alloc independent SDB page. */
  900. spin_lock(&dev->db_bitmap_lock);
  901. bitmap_idx = find_first_zero_bit(dev->sdb_page, attrs->dwqe_pages);
  902. if (bitmap_idx != attrs->dwqe_pages) {
  903. set_bit(bitmap_idx, dev->sdb_page);
  904. spin_unlock(&dev->db_bitmap_lock);
  905. ctx->sdb_type = ERDMA_SDB_PAGE;
  906. ctx->sdb_idx = bitmap_idx;
  907. ctx->sdb_page_idx = bitmap_idx;
  908. ctx->sdb = dev->func_bar_addr + ERDMA_BAR_SQDB_SPACE_OFFSET +
  909. (bitmap_idx << PAGE_SHIFT);
  910. ctx->sdb_page_off = 0;
  911. return;
  912. }
  913. bitmap_idx = find_first_zero_bit(dev->sdb_entry, attrs->dwqe_entries);
  914. if (bitmap_idx != attrs->dwqe_entries) {
  915. set_bit(bitmap_idx, dev->sdb_entry);
  916. spin_unlock(&dev->db_bitmap_lock);
  917. ctx->sdb_type = ERDMA_SDB_ENTRY;
  918. ctx->sdb_idx = bitmap_idx;
  919. ctx->sdb_page_idx = attrs->dwqe_pages +
  920. bitmap_idx / ERDMA_DWQE_TYPE1_CNT_PER_PAGE;
  921. ctx->sdb_page_off = bitmap_idx % ERDMA_DWQE_TYPE1_CNT_PER_PAGE;
  922. ctx->sdb = dev->func_bar_addr + ERDMA_BAR_SQDB_SPACE_OFFSET +
  923. (ctx->sdb_page_idx << PAGE_SHIFT);
  924. return;
  925. }
  926. spin_unlock(&dev->db_bitmap_lock);
  927. alloc_normal_db:
  928. ctx->sdb_type = ERDMA_SDB_SHARED;
  929. ctx->sdb_idx = 0;
  930. ctx->sdb_page_idx = ERDMA_SDB_SHARED_PAGE_INDEX;
  931. ctx->sdb_page_off = 0;
  932. ctx->sdb = dev->func_bar_addr + (ctx->sdb_page_idx << PAGE_SHIFT);
  933. }
  934. static void erdma_uctx_user_mmap_entries_remove(struct erdma_ucontext *uctx)
  935. {
  936. rdma_user_mmap_entry_remove(uctx->sq_db_mmap_entry);
  937. rdma_user_mmap_entry_remove(uctx->rq_db_mmap_entry);
  938. rdma_user_mmap_entry_remove(uctx->cq_db_mmap_entry);
  939. }
  940. int erdma_alloc_ucontext(struct ib_ucontext *ibctx, struct ib_udata *udata)
  941. {
  942. struct erdma_ucontext *ctx = to_ectx(ibctx);
  943. struct erdma_dev *dev = to_edev(ibctx->device);
  944. int ret;
  945. struct erdma_uresp_alloc_ctx uresp = {};
  946. if (atomic_inc_return(&dev->num_ctx) > ERDMA_MAX_CONTEXT) {
  947. ret = -ENOMEM;
  948. goto err_out;
  949. }
  950. INIT_LIST_HEAD(&ctx->dbrecords_page_list);
  951. mutex_init(&ctx->dbrecords_page_mutex);
  952. alloc_db_resources(dev, ctx);
  953. ctx->rdb = dev->func_bar_addr + ERDMA_BAR_RQDB_SPACE_OFFSET;
  954. ctx->cdb = dev->func_bar_addr + ERDMA_BAR_CQDB_SPACE_OFFSET;
  955. if (udata->outlen < sizeof(uresp)) {
  956. ret = -EINVAL;
  957. goto err_out;
  958. }
  959. ctx->sq_db_mmap_entry = erdma_user_mmap_entry_insert(
  960. ctx, (void *)ctx->sdb, PAGE_SIZE, ERDMA_MMAP_IO_NC, &uresp.sdb);
  961. if (!ctx->sq_db_mmap_entry) {
  962. ret = -ENOMEM;
  963. goto err_out;
  964. }
  965. ctx->rq_db_mmap_entry = erdma_user_mmap_entry_insert(
  966. ctx, (void *)ctx->rdb, PAGE_SIZE, ERDMA_MMAP_IO_NC, &uresp.rdb);
  967. if (!ctx->rq_db_mmap_entry) {
  968. ret = -EINVAL;
  969. goto err_out;
  970. }
  971. ctx->cq_db_mmap_entry = erdma_user_mmap_entry_insert(
  972. ctx, (void *)ctx->cdb, PAGE_SIZE, ERDMA_MMAP_IO_NC, &uresp.cdb);
  973. if (!ctx->cq_db_mmap_entry) {
  974. ret = -EINVAL;
  975. goto err_out;
  976. }
  977. uresp.dev_id = dev->pdev->device;
  978. uresp.sdb_type = ctx->sdb_type;
  979. uresp.sdb_offset = ctx->sdb_page_off;
  980. ret = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  981. if (ret)
  982. goto err_out;
  983. return 0;
  984. err_out:
  985. erdma_uctx_user_mmap_entries_remove(ctx);
  986. atomic_dec(&dev->num_ctx);
  987. return ret;
  988. }
  989. void erdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  990. {
  991. struct erdma_ucontext *ctx = to_ectx(ibctx);
  992. struct erdma_dev *dev = to_edev(ibctx->device);
  993. spin_lock(&dev->db_bitmap_lock);
  994. if (ctx->sdb_type == ERDMA_SDB_PAGE)
  995. clear_bit(ctx->sdb_idx, dev->sdb_page);
  996. else if (ctx->sdb_type == ERDMA_SDB_ENTRY)
  997. clear_bit(ctx->sdb_idx, dev->sdb_entry);
  998. erdma_uctx_user_mmap_entries_remove(ctx);
  999. spin_unlock(&dev->db_bitmap_lock);
  1000. atomic_dec(&dev->num_ctx);
  1001. }
  1002. static int ib_qp_state_to_erdma_qp_state[IB_QPS_ERR + 1] = {
  1003. [IB_QPS_RESET] = ERDMA_QP_STATE_IDLE,
  1004. [IB_QPS_INIT] = ERDMA_QP_STATE_IDLE,
  1005. [IB_QPS_RTR] = ERDMA_QP_STATE_RTR,
  1006. [IB_QPS_RTS] = ERDMA_QP_STATE_RTS,
  1007. [IB_QPS_SQD] = ERDMA_QP_STATE_CLOSING,
  1008. [IB_QPS_SQE] = ERDMA_QP_STATE_TERMINATE,
  1009. [IB_QPS_ERR] = ERDMA_QP_STATE_ERROR
  1010. };
  1011. int erdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
  1012. struct ib_udata *udata)
  1013. {
  1014. struct erdma_qp_attrs new_attrs;
  1015. enum erdma_qp_attr_mask erdma_attr_mask = 0;
  1016. struct erdma_qp *qp = to_eqp(ibqp);
  1017. int ret = 0;
  1018. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  1019. return -EOPNOTSUPP;
  1020. memset(&new_attrs, 0, sizeof(new_attrs));
  1021. if (attr_mask & IB_QP_STATE) {
  1022. new_attrs.state = ib_qp_state_to_erdma_qp_state[attr->qp_state];
  1023. erdma_attr_mask |= ERDMA_QP_ATTR_STATE;
  1024. }
  1025. down_write(&qp->state_lock);
  1026. ret = erdma_modify_qp_internal(qp, &new_attrs, erdma_attr_mask);
  1027. up_write(&qp->state_lock);
  1028. return ret;
  1029. }
  1030. int erdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
  1031. int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1032. {
  1033. struct erdma_qp *qp;
  1034. struct erdma_dev *dev;
  1035. if (ibqp && qp_attr && qp_init_attr) {
  1036. qp = to_eqp(ibqp);
  1037. dev = to_edev(ibqp->device);
  1038. } else {
  1039. return -EINVAL;
  1040. }
  1041. qp_attr->cap.max_inline_data = ERDMA_MAX_INLINE;
  1042. qp_init_attr->cap.max_inline_data = ERDMA_MAX_INLINE;
  1043. qp_attr->cap.max_send_wr = qp->attrs.sq_size;
  1044. qp_attr->cap.max_recv_wr = qp->attrs.rq_size;
  1045. qp_attr->cap.max_send_sge = qp->attrs.max_send_sge;
  1046. qp_attr->cap.max_recv_sge = qp->attrs.max_recv_sge;
  1047. qp_attr->path_mtu = ib_mtu_int_to_enum(dev->netdev->mtu);
  1048. qp_attr->max_rd_atomic = qp->attrs.irq_size;
  1049. qp_attr->max_dest_rd_atomic = qp->attrs.orq_size;
  1050. qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE |
  1051. IB_ACCESS_REMOTE_WRITE |
  1052. IB_ACCESS_REMOTE_READ;
  1053. qp_init_attr->cap = qp_attr->cap;
  1054. return 0;
  1055. }
  1056. static int erdma_init_user_cq(struct erdma_ucontext *ctx, struct erdma_cq *cq,
  1057. struct erdma_ureq_create_cq *ureq)
  1058. {
  1059. int ret;
  1060. struct erdma_dev *dev = to_edev(cq->ibcq.device);
  1061. ret = get_mtt_entries(dev, &cq->user_cq.qbuf_mtt, ureq->qbuf_va,
  1062. ureq->qbuf_len, 0, ureq->qbuf_va, SZ_64M - SZ_4K,
  1063. 1);
  1064. if (ret)
  1065. return ret;
  1066. ret = erdma_map_user_dbrecords(ctx, ureq->db_record_va,
  1067. &cq->user_cq.user_dbr_page,
  1068. &cq->user_cq.db_info_dma_addr);
  1069. if (ret)
  1070. put_mtt_entries(dev, &cq->user_cq.qbuf_mtt);
  1071. return ret;
  1072. }
  1073. static int erdma_init_kernel_cq(struct erdma_cq *cq)
  1074. {
  1075. struct erdma_dev *dev = to_edev(cq->ibcq.device);
  1076. cq->kern_cq.qbuf =
  1077. dma_alloc_coherent(&dev->pdev->dev,
  1078. WARPPED_BUFSIZE(cq->depth << CQE_SHIFT),
  1079. &cq->kern_cq.qbuf_dma_addr, GFP_KERNEL);
  1080. if (!cq->kern_cq.qbuf)
  1081. return -ENOMEM;
  1082. cq->kern_cq.db_record =
  1083. (u64 *)(cq->kern_cq.qbuf + (cq->depth << CQE_SHIFT));
  1084. spin_lock_init(&cq->kern_cq.lock);
  1085. /* use default cqdb addr */
  1086. cq->kern_cq.db = dev->func_bar + ERDMA_BAR_CQDB_SPACE_OFFSET;
  1087. return 0;
  1088. }
  1089. int erdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
  1090. struct ib_udata *udata)
  1091. {
  1092. struct erdma_cq *cq = to_ecq(ibcq);
  1093. struct erdma_dev *dev = to_edev(ibcq->device);
  1094. unsigned int depth = attr->cqe;
  1095. int ret;
  1096. struct erdma_ucontext *ctx = rdma_udata_to_drv_context(
  1097. udata, struct erdma_ucontext, ibucontext);
  1098. if (depth > dev->attrs.max_cqe)
  1099. return -EINVAL;
  1100. depth = roundup_pow_of_two(depth);
  1101. cq->ibcq.cqe = depth;
  1102. cq->depth = depth;
  1103. cq->assoc_eqn = attr->comp_vector + 1;
  1104. ret = xa_alloc_cyclic(&dev->cq_xa, &cq->cqn, cq,
  1105. XA_LIMIT(1, dev->attrs.max_cq - 1),
  1106. &dev->next_alloc_cqn, GFP_KERNEL);
  1107. if (ret < 0)
  1108. return ret;
  1109. if (!rdma_is_kernel_res(&ibcq->res)) {
  1110. struct erdma_ureq_create_cq ureq;
  1111. struct erdma_uresp_create_cq uresp;
  1112. ret = ib_copy_from_udata(&ureq, udata,
  1113. min(udata->inlen, sizeof(ureq)));
  1114. if (ret)
  1115. goto err_out_xa;
  1116. ret = erdma_init_user_cq(ctx, cq, &ureq);
  1117. if (ret)
  1118. goto err_out_xa;
  1119. uresp.cq_id = cq->cqn;
  1120. uresp.num_cqe = depth;
  1121. ret = ib_copy_to_udata(udata, &uresp,
  1122. min(sizeof(uresp), udata->outlen));
  1123. if (ret)
  1124. goto err_free_res;
  1125. } else {
  1126. ret = erdma_init_kernel_cq(cq);
  1127. if (ret)
  1128. goto err_out_xa;
  1129. }
  1130. ret = create_cq_cmd(dev, cq);
  1131. if (ret)
  1132. goto err_free_res;
  1133. return 0;
  1134. err_free_res:
  1135. if (!rdma_is_kernel_res(&ibcq->res)) {
  1136. erdma_unmap_user_dbrecords(ctx, &cq->user_cq.user_dbr_page);
  1137. put_mtt_entries(dev, &cq->user_cq.qbuf_mtt);
  1138. } else {
  1139. dma_free_coherent(&dev->pdev->dev,
  1140. WARPPED_BUFSIZE(depth << CQE_SHIFT),
  1141. cq->kern_cq.qbuf, cq->kern_cq.qbuf_dma_addr);
  1142. }
  1143. err_out_xa:
  1144. xa_erase(&dev->cq_xa, cq->cqn);
  1145. return ret;
  1146. }
  1147. void erdma_set_mtu(struct erdma_dev *dev, u32 mtu)
  1148. {
  1149. struct erdma_cmdq_config_mtu_req req;
  1150. erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_COMMON,
  1151. CMDQ_OPCODE_CONF_MTU);
  1152. req.mtu = mtu;
  1153. erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL);
  1154. }
  1155. void erdma_port_event(struct erdma_dev *dev, enum ib_event_type reason)
  1156. {
  1157. struct ib_event event;
  1158. event.device = &dev->ibdev;
  1159. event.element.port_num = 1;
  1160. event.event = reason;
  1161. ib_dispatch_event(&event);
  1162. }