device.c 43 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. static int allow_db_fc_on_t5;
  44. module_param(allow_db_fc_on_t5, int, 0644);
  45. MODULE_PARM_DESC(allow_db_fc_on_t5,
  46. "Allow DB Flow Control on T5 (default = 0)");
  47. static int allow_db_coalescing_on_t5;
  48. module_param(allow_db_coalescing_on_t5, int, 0644);
  49. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  50. "Allow DB Coalescing on T5 (default = 0)");
  51. int c4iw_wr_log = 0;
  52. module_param(c4iw_wr_log, int, 0444);
  53. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  54. static int c4iw_wr_log_size_order = 12;
  55. module_param(c4iw_wr_log_size_order, int, 0444);
  56. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  57. "Number of entries (log2) in the work request timing log.");
  58. static LIST_HEAD(uld_ctx_list);
  59. static DEFINE_MUTEX(dev_mutex);
  60. static struct workqueue_struct *reg_workq;
  61. #define DB_FC_RESUME_SIZE 64
  62. #define DB_FC_RESUME_DELAY 1
  63. #define DB_FC_DRAIN_THRESH 0
  64. static struct dentry *c4iw_debugfs_root;
  65. struct c4iw_debugfs_data {
  66. struct c4iw_dev *devp;
  67. char *buf;
  68. int bufsize;
  69. int pos;
  70. };
  71. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  72. loff_t *ppos)
  73. {
  74. struct c4iw_debugfs_data *d = file->private_data;
  75. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  76. }
  77. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  78. {
  79. struct wr_log_entry le;
  80. int idx;
  81. if (!wq->rdev->wr_log)
  82. return;
  83. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  84. (wq->rdev->wr_log_size - 1);
  85. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  86. le.poll_host_time = ktime_get();
  87. le.valid = 1;
  88. le.cqe_sge_ts = CQE_TS(cqe);
  89. if (SQ_TYPE(cqe)) {
  90. le.qid = wq->sq.qid;
  91. le.opcode = CQE_OPCODE(cqe);
  92. le.post_host_time = wq->sq.sw_sq[wq->sq.cidx].host_time;
  93. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  94. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  95. } else {
  96. le.qid = wq->rq.qid;
  97. le.opcode = FW_RI_RECEIVE;
  98. le.post_host_time = wq->rq.sw_rq[wq->rq.cidx].host_time;
  99. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  100. le.wr_id = CQE_WRID_MSN(cqe);
  101. }
  102. wq->rdev->wr_log[idx] = le;
  103. }
  104. static int wr_log_show(struct seq_file *seq, void *v)
  105. {
  106. struct c4iw_dev *dev = seq->private;
  107. ktime_t prev_time;
  108. struct wr_log_entry *lep;
  109. int prev_time_set = 0;
  110. int idx, end;
  111. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  112. idx = atomic_read(&dev->rdev.wr_log_idx) &
  113. (dev->rdev.wr_log_size - 1);
  114. end = idx - 1;
  115. if (end < 0)
  116. end = dev->rdev.wr_log_size - 1;
  117. lep = &dev->rdev.wr_log[idx];
  118. while (idx != end) {
  119. if (lep->valid) {
  120. if (!prev_time_set) {
  121. prev_time_set = 1;
  122. prev_time = lep->poll_host_time;
  123. }
  124. seq_printf(seq, "%04u: nsec %llu qid %u opcode "
  125. "%u %s 0x%x host_wr_delta nsec %llu "
  126. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  127. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  128. "cqe_poll_delta_ns %llu\n",
  129. idx,
  130. ktime_to_ns(ktime_sub(lep->poll_host_time,
  131. prev_time)),
  132. lep->qid, lep->opcode,
  133. lep->opcode == FW_RI_RECEIVE ?
  134. "msn" : "wrid",
  135. lep->wr_id,
  136. ktime_to_ns(ktime_sub(lep->poll_host_time,
  137. lep->post_host_time)),
  138. lep->post_sge_ts, lep->cqe_sge_ts,
  139. lep->poll_sge_ts,
  140. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  141. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  142. prev_time = lep->poll_host_time;
  143. }
  144. idx++;
  145. if (idx > (dev->rdev.wr_log_size - 1))
  146. idx = 0;
  147. lep = &dev->rdev.wr_log[idx];
  148. }
  149. #undef ts2ns
  150. return 0;
  151. }
  152. static int wr_log_open(struct inode *inode, struct file *file)
  153. {
  154. return single_open(file, wr_log_show, inode->i_private);
  155. }
  156. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  157. size_t count, loff_t *pos)
  158. {
  159. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  160. int i;
  161. if (dev->rdev.wr_log)
  162. for (i = 0; i < dev->rdev.wr_log_size; i++)
  163. dev->rdev.wr_log[i].valid = 0;
  164. return count;
  165. }
  166. static const struct file_operations wr_log_debugfs_fops = {
  167. .owner = THIS_MODULE,
  168. .open = wr_log_open,
  169. .release = single_release,
  170. .read = seq_read,
  171. .llseek = seq_lseek,
  172. .write = wr_log_clear,
  173. };
  174. static struct sockaddr_in zero_sin = {
  175. .sin_family = AF_INET,
  176. };
  177. static struct sockaddr_in6 zero_sin6 = {
  178. .sin6_family = AF_INET6,
  179. };
  180. static void set_ep_sin_addrs(struct c4iw_ep *ep,
  181. struct sockaddr_in **lsin,
  182. struct sockaddr_in **rsin,
  183. struct sockaddr_in **m_lsin,
  184. struct sockaddr_in **m_rsin)
  185. {
  186. struct iw_cm_id *id = ep->com.cm_id;
  187. *m_lsin = (struct sockaddr_in *)&ep->com.local_addr;
  188. *m_rsin = (struct sockaddr_in *)&ep->com.remote_addr;
  189. if (id) {
  190. *lsin = (struct sockaddr_in *)&id->local_addr;
  191. *rsin = (struct sockaddr_in *)&id->remote_addr;
  192. } else {
  193. *lsin = &zero_sin;
  194. *rsin = &zero_sin;
  195. }
  196. }
  197. static void set_ep_sin6_addrs(struct c4iw_ep *ep,
  198. struct sockaddr_in6 **lsin6,
  199. struct sockaddr_in6 **rsin6,
  200. struct sockaddr_in6 **m_lsin6,
  201. struct sockaddr_in6 **m_rsin6)
  202. {
  203. struct iw_cm_id *id = ep->com.cm_id;
  204. *m_lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
  205. *m_rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
  206. if (id) {
  207. *lsin6 = (struct sockaddr_in6 *)&id->local_addr;
  208. *rsin6 = (struct sockaddr_in6 *)&id->remote_addr;
  209. } else {
  210. *lsin6 = &zero_sin6;
  211. *rsin6 = &zero_sin6;
  212. }
  213. }
  214. static int dump_qp(unsigned long id, struct c4iw_qp *qp,
  215. struct c4iw_debugfs_data *qpd)
  216. {
  217. int space;
  218. int cc;
  219. if (id != qp->wq.sq.qid)
  220. return 0;
  221. space = qpd->bufsize - qpd->pos - 1;
  222. if (space == 0)
  223. return 1;
  224. if (qp->ep) {
  225. struct c4iw_ep *ep = qp->ep;
  226. if (ep->com.local_addr.ss_family == AF_INET) {
  227. struct sockaddr_in *lsin;
  228. struct sockaddr_in *rsin;
  229. struct sockaddr_in *m_lsin;
  230. struct sockaddr_in *m_rsin;
  231. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  232. cc = snprintf(qpd->buf + qpd->pos, space,
  233. "rc qp sq id %u %s id %u state %u "
  234. "onchip %u ep tid %u state %u "
  235. "%pI4:%u/%u->%pI4:%u/%u\n",
  236. qp->wq.sq.qid, qp->srq ? "srq" : "rq",
  237. qp->srq ? qp->srq->idx : qp->wq.rq.qid,
  238. (int)qp->attr.state,
  239. qp->wq.sq.flags & T4_SQ_ONCHIP,
  240. ep->hwtid, (int)ep->com.state,
  241. &lsin->sin_addr, ntohs(lsin->sin_port),
  242. ntohs(m_lsin->sin_port),
  243. &rsin->sin_addr, ntohs(rsin->sin_port),
  244. ntohs(m_rsin->sin_port));
  245. } else {
  246. struct sockaddr_in6 *lsin6;
  247. struct sockaddr_in6 *rsin6;
  248. struct sockaddr_in6 *m_lsin6;
  249. struct sockaddr_in6 *m_rsin6;
  250. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
  251. &m_rsin6);
  252. cc = snprintf(qpd->buf + qpd->pos, space,
  253. "rc qp sq id %u rq id %u state %u "
  254. "onchip %u ep tid %u state %u "
  255. "%pI6:%u/%u->%pI6:%u/%u\n",
  256. qp->wq.sq.qid, qp->wq.rq.qid,
  257. (int)qp->attr.state,
  258. qp->wq.sq.flags & T4_SQ_ONCHIP,
  259. ep->hwtid, (int)ep->com.state,
  260. &lsin6->sin6_addr,
  261. ntohs(lsin6->sin6_port),
  262. ntohs(m_lsin6->sin6_port),
  263. &rsin6->sin6_addr,
  264. ntohs(rsin6->sin6_port),
  265. ntohs(m_rsin6->sin6_port));
  266. }
  267. } else
  268. cc = snprintf(qpd->buf + qpd->pos, space,
  269. "qp sq id %u rq id %u state %u onchip %u\n",
  270. qp->wq.sq.qid, qp->wq.rq.qid,
  271. (int)qp->attr.state,
  272. qp->wq.sq.flags & T4_SQ_ONCHIP);
  273. if (cc < space)
  274. qpd->pos += cc;
  275. return 0;
  276. }
  277. static int qp_release(struct inode *inode, struct file *file)
  278. {
  279. struct c4iw_debugfs_data *qpd = file->private_data;
  280. if (!qpd) {
  281. pr_info("%s null qpd?\n", __func__);
  282. return 0;
  283. }
  284. vfree(qpd->buf);
  285. kfree(qpd);
  286. return 0;
  287. }
  288. static int qp_open(struct inode *inode, struct file *file)
  289. {
  290. struct c4iw_qp *qp;
  291. struct c4iw_debugfs_data *qpd;
  292. unsigned long index;
  293. int count = 1;
  294. qpd = kmalloc(sizeof(*qpd), GFP_KERNEL);
  295. if (!qpd)
  296. return -ENOMEM;
  297. qpd->devp = inode->i_private;
  298. qpd->pos = 0;
  299. /*
  300. * No need to lock; we drop the lock to call vmalloc so it's racy
  301. * anyway. Someone who cares should switch this over to seq_file
  302. */
  303. xa_for_each(&qpd->devp->qps, index, qp)
  304. count++;
  305. qpd->bufsize = count * 180;
  306. qpd->buf = vmalloc(qpd->bufsize);
  307. if (!qpd->buf) {
  308. kfree(qpd);
  309. return -ENOMEM;
  310. }
  311. xa_lock_irq(&qpd->devp->qps);
  312. xa_for_each(&qpd->devp->qps, index, qp)
  313. dump_qp(index, qp, qpd);
  314. xa_unlock_irq(&qpd->devp->qps);
  315. qpd->buf[qpd->pos++] = 0;
  316. file->private_data = qpd;
  317. return 0;
  318. }
  319. static const struct file_operations qp_debugfs_fops = {
  320. .owner = THIS_MODULE,
  321. .open = qp_open,
  322. .release = qp_release,
  323. .read = debugfs_read,
  324. .llseek = default_llseek,
  325. };
  326. static int dump_stag(unsigned long id, struct c4iw_debugfs_data *stagd)
  327. {
  328. int space;
  329. int cc;
  330. struct fw_ri_tpte tpte;
  331. int ret;
  332. space = stagd->bufsize - stagd->pos - 1;
  333. if (space == 0)
  334. return 1;
  335. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  336. (__be32 *)&tpte);
  337. if (ret) {
  338. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  339. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  340. return ret;
  341. }
  342. cc = snprintf(stagd->buf + stagd->pos, space,
  343. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  344. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  345. (u32)id<<8,
  346. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  347. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  348. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  349. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  350. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  351. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  352. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  353. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  354. if (cc < space)
  355. stagd->pos += cc;
  356. return 0;
  357. }
  358. static int stag_release(struct inode *inode, struct file *file)
  359. {
  360. struct c4iw_debugfs_data *stagd = file->private_data;
  361. if (!stagd) {
  362. pr_info("%s null stagd?\n", __func__);
  363. return 0;
  364. }
  365. vfree(stagd->buf);
  366. kfree(stagd);
  367. return 0;
  368. }
  369. static int stag_open(struct inode *inode, struct file *file)
  370. {
  371. struct c4iw_debugfs_data *stagd;
  372. void *p;
  373. unsigned long index;
  374. int ret = 0;
  375. int count = 1;
  376. stagd = kmalloc(sizeof(*stagd), GFP_KERNEL);
  377. if (!stagd) {
  378. ret = -ENOMEM;
  379. goto out;
  380. }
  381. stagd->devp = inode->i_private;
  382. stagd->pos = 0;
  383. xa_for_each(&stagd->devp->mrs, index, p)
  384. count++;
  385. stagd->bufsize = count * 256;
  386. stagd->buf = vmalloc(stagd->bufsize);
  387. if (!stagd->buf) {
  388. ret = -ENOMEM;
  389. goto err1;
  390. }
  391. xa_lock_irq(&stagd->devp->mrs);
  392. xa_for_each(&stagd->devp->mrs, index, p)
  393. dump_stag(index, stagd);
  394. xa_unlock_irq(&stagd->devp->mrs);
  395. stagd->buf[stagd->pos++] = 0;
  396. file->private_data = stagd;
  397. goto out;
  398. err1:
  399. kfree(stagd);
  400. out:
  401. return ret;
  402. }
  403. static const struct file_operations stag_debugfs_fops = {
  404. .owner = THIS_MODULE,
  405. .open = stag_open,
  406. .release = stag_release,
  407. .read = debugfs_read,
  408. .llseek = default_llseek,
  409. };
  410. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  411. static int stats_show(struct seq_file *seq, void *v)
  412. {
  413. struct c4iw_dev *dev = seq->private;
  414. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  415. "Max", "Fail");
  416. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  417. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  418. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  419. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  420. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  421. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  422. seq_printf(seq, " SRQS: %10llu %10llu %10llu %10llu\n",
  423. dev->rdev.stats.srqt.total, dev->rdev.stats.srqt.cur,
  424. dev->rdev.stats.srqt.max, dev->rdev.stats.srqt.fail);
  425. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  426. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  427. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  428. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  429. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  430. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  431. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  432. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  433. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  434. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  435. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  436. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  437. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  438. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  439. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  440. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  441. db_state_str[dev->db_state],
  442. dev->rdev.stats.db_state_transitions,
  443. dev->rdev.stats.db_fc_interruptions);
  444. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  445. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  446. dev->rdev.stats.act_ofld_conn_fails);
  447. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  448. dev->rdev.stats.pas_ofld_conn_fails);
  449. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  450. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  451. return 0;
  452. }
  453. static int stats_open(struct inode *inode, struct file *file)
  454. {
  455. return single_open(file, stats_show, inode->i_private);
  456. }
  457. static ssize_t stats_clear(struct file *file, const char __user *buf,
  458. size_t count, loff_t *pos)
  459. {
  460. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  461. mutex_lock(&dev->rdev.stats.lock);
  462. dev->rdev.stats.pd.max = 0;
  463. dev->rdev.stats.pd.fail = 0;
  464. dev->rdev.stats.qid.max = 0;
  465. dev->rdev.stats.qid.fail = 0;
  466. dev->rdev.stats.stag.max = 0;
  467. dev->rdev.stats.stag.fail = 0;
  468. dev->rdev.stats.pbl.max = 0;
  469. dev->rdev.stats.pbl.fail = 0;
  470. dev->rdev.stats.rqt.max = 0;
  471. dev->rdev.stats.rqt.fail = 0;
  472. dev->rdev.stats.rqt.max = 0;
  473. dev->rdev.stats.rqt.fail = 0;
  474. dev->rdev.stats.ocqp.max = 0;
  475. dev->rdev.stats.ocqp.fail = 0;
  476. dev->rdev.stats.db_full = 0;
  477. dev->rdev.stats.db_empty = 0;
  478. dev->rdev.stats.db_drop = 0;
  479. dev->rdev.stats.db_state_transitions = 0;
  480. dev->rdev.stats.tcam_full = 0;
  481. dev->rdev.stats.act_ofld_conn_fails = 0;
  482. dev->rdev.stats.pas_ofld_conn_fails = 0;
  483. mutex_unlock(&dev->rdev.stats.lock);
  484. return count;
  485. }
  486. static const struct file_operations stats_debugfs_fops = {
  487. .owner = THIS_MODULE,
  488. .open = stats_open,
  489. .release = single_release,
  490. .read = seq_read,
  491. .llseek = seq_lseek,
  492. .write = stats_clear,
  493. };
  494. static int dump_ep(struct c4iw_ep *ep, struct c4iw_debugfs_data *epd)
  495. {
  496. int space;
  497. int cc;
  498. space = epd->bufsize - epd->pos - 1;
  499. if (space == 0)
  500. return 1;
  501. if (ep->com.local_addr.ss_family == AF_INET) {
  502. struct sockaddr_in *lsin;
  503. struct sockaddr_in *rsin;
  504. struct sockaddr_in *m_lsin;
  505. struct sockaddr_in *m_rsin;
  506. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  507. cc = snprintf(epd->buf + epd->pos, space,
  508. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  509. "history 0x%lx hwtid %d atid %d "
  510. "conn_na %u abort_na %u "
  511. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  512. ep, ep->com.cm_id, ep->com.qp,
  513. (int)ep->com.state, ep->com.flags,
  514. ep->com.history, ep->hwtid, ep->atid,
  515. ep->stats.connect_neg_adv,
  516. ep->stats.abort_neg_adv,
  517. &lsin->sin_addr, ntohs(lsin->sin_port),
  518. ntohs(m_lsin->sin_port),
  519. &rsin->sin_addr, ntohs(rsin->sin_port),
  520. ntohs(m_rsin->sin_port));
  521. } else {
  522. struct sockaddr_in6 *lsin6;
  523. struct sockaddr_in6 *rsin6;
  524. struct sockaddr_in6 *m_lsin6;
  525. struct sockaddr_in6 *m_rsin6;
  526. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
  527. cc = snprintf(epd->buf + epd->pos, space,
  528. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  529. "history 0x%lx hwtid %d atid %d "
  530. "conn_na %u abort_na %u "
  531. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  532. ep, ep->com.cm_id, ep->com.qp,
  533. (int)ep->com.state, ep->com.flags,
  534. ep->com.history, ep->hwtid, ep->atid,
  535. ep->stats.connect_neg_adv,
  536. ep->stats.abort_neg_adv,
  537. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  538. ntohs(m_lsin6->sin6_port),
  539. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  540. ntohs(m_rsin6->sin6_port));
  541. }
  542. if (cc < space)
  543. epd->pos += cc;
  544. return 0;
  545. }
  546. static
  547. int dump_listen_ep(struct c4iw_listen_ep *ep, struct c4iw_debugfs_data *epd)
  548. {
  549. int space;
  550. int cc;
  551. space = epd->bufsize - epd->pos - 1;
  552. if (space == 0)
  553. return 1;
  554. if (ep->com.local_addr.ss_family == AF_INET) {
  555. struct sockaddr_in *lsin = (struct sockaddr_in *)
  556. &ep->com.cm_id->local_addr;
  557. struct sockaddr_in *m_lsin = (struct sockaddr_in *)
  558. &ep->com.cm_id->m_local_addr;
  559. cc = snprintf(epd->buf + epd->pos, space,
  560. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  561. "backlog %d %pI4:%d/%d\n",
  562. ep, ep->com.cm_id, (int)ep->com.state,
  563. ep->com.flags, ep->stid, ep->backlog,
  564. &lsin->sin_addr, ntohs(lsin->sin_port),
  565. ntohs(m_lsin->sin_port));
  566. } else {
  567. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  568. &ep->com.cm_id->local_addr;
  569. struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
  570. &ep->com.cm_id->m_local_addr;
  571. cc = snprintf(epd->buf + epd->pos, space,
  572. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  573. "backlog %d %pI6:%d/%d\n",
  574. ep, ep->com.cm_id, (int)ep->com.state,
  575. ep->com.flags, ep->stid, ep->backlog,
  576. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  577. ntohs(m_lsin6->sin6_port));
  578. }
  579. if (cc < space)
  580. epd->pos += cc;
  581. return 0;
  582. }
  583. static int ep_release(struct inode *inode, struct file *file)
  584. {
  585. struct c4iw_debugfs_data *epd = file->private_data;
  586. if (!epd) {
  587. pr_info("%s null qpd?\n", __func__);
  588. return 0;
  589. }
  590. vfree(epd->buf);
  591. kfree(epd);
  592. return 0;
  593. }
  594. static int ep_open(struct inode *inode, struct file *file)
  595. {
  596. struct c4iw_ep *ep;
  597. struct c4iw_listen_ep *lep;
  598. unsigned long index;
  599. struct c4iw_debugfs_data *epd;
  600. int ret = 0;
  601. int count = 1;
  602. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  603. if (!epd) {
  604. ret = -ENOMEM;
  605. goto out;
  606. }
  607. epd->devp = inode->i_private;
  608. epd->pos = 0;
  609. xa_for_each(&epd->devp->hwtids, index, ep)
  610. count++;
  611. xa_for_each(&epd->devp->atids, index, ep)
  612. count++;
  613. xa_for_each(&epd->devp->stids, index, lep)
  614. count++;
  615. epd->bufsize = count * 240;
  616. epd->buf = vmalloc(epd->bufsize);
  617. if (!epd->buf) {
  618. ret = -ENOMEM;
  619. goto err1;
  620. }
  621. xa_lock_irq(&epd->devp->hwtids);
  622. xa_for_each(&epd->devp->hwtids, index, ep)
  623. dump_ep(ep, epd);
  624. xa_unlock_irq(&epd->devp->hwtids);
  625. xa_lock_irq(&epd->devp->atids);
  626. xa_for_each(&epd->devp->atids, index, ep)
  627. dump_ep(ep, epd);
  628. xa_unlock_irq(&epd->devp->atids);
  629. xa_lock_irq(&epd->devp->stids);
  630. xa_for_each(&epd->devp->stids, index, lep)
  631. dump_listen_ep(lep, epd);
  632. xa_unlock_irq(&epd->devp->stids);
  633. file->private_data = epd;
  634. goto out;
  635. err1:
  636. kfree(epd);
  637. out:
  638. return ret;
  639. }
  640. static const struct file_operations ep_debugfs_fops = {
  641. .owner = THIS_MODULE,
  642. .open = ep_open,
  643. .release = ep_release,
  644. .read = debugfs_read,
  645. };
  646. static void setup_debugfs(struct c4iw_dev *devp)
  647. {
  648. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  649. (void *)devp, &qp_debugfs_fops, 4096);
  650. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  651. (void *)devp, &stag_debugfs_fops, 4096);
  652. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  653. (void *)devp, &stats_debugfs_fops, 4096);
  654. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  655. (void *)devp, &ep_debugfs_fops, 4096);
  656. if (c4iw_wr_log)
  657. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  658. (void *)devp, &wr_log_debugfs_fops, 4096);
  659. }
  660. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  661. struct c4iw_dev_ucontext *uctx)
  662. {
  663. struct list_head *pos, *nxt;
  664. struct c4iw_qid_list *entry;
  665. mutex_lock(&uctx->lock);
  666. list_for_each_safe(pos, nxt, &uctx->qpids) {
  667. entry = list_entry(pos, struct c4iw_qid_list, entry);
  668. list_del_init(&entry->entry);
  669. if (!(entry->qid & rdev->qpmask)) {
  670. c4iw_put_resource(&rdev->resource.qid_table,
  671. entry->qid);
  672. mutex_lock(&rdev->stats.lock);
  673. rdev->stats.qid.cur -= rdev->qpmask + 1;
  674. mutex_unlock(&rdev->stats.lock);
  675. }
  676. kfree(entry);
  677. }
  678. list_for_each_safe(pos, nxt, &uctx->cqids) {
  679. entry = list_entry(pos, struct c4iw_qid_list, entry);
  680. list_del_init(&entry->entry);
  681. kfree(entry);
  682. }
  683. mutex_unlock(&uctx->lock);
  684. }
  685. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  686. struct c4iw_dev_ucontext *uctx)
  687. {
  688. INIT_LIST_HEAD(&uctx->qpids);
  689. INIT_LIST_HEAD(&uctx->cqids);
  690. mutex_init(&uctx->lock);
  691. }
  692. /* Caller takes care of locking if needed */
  693. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  694. {
  695. int err;
  696. unsigned int factor;
  697. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  698. /*
  699. * This implementation assumes udb_density == ucq_density! Eventually
  700. * we might need to support this but for now fail the open. Also the
  701. * cqid and qpid range must match for now.
  702. */
  703. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  704. pr_err("%s: unsupported udb/ucq densities %u/%u\n",
  705. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  706. rdev->lldi.ucq_density);
  707. return -EINVAL;
  708. }
  709. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  710. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  711. pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
  712. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  713. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  714. rdev->lldi.vr->cq.size);
  715. return -EINVAL;
  716. }
  717. /* This implementation requires a sge_host_page_size <= PAGE_SIZE. */
  718. if (rdev->lldi.sge_host_page_size > PAGE_SIZE) {
  719. pr_err("%s: unsupported sge host page size %u\n",
  720. pci_name(rdev->lldi.pdev),
  721. rdev->lldi.sge_host_page_size);
  722. return -EINVAL;
  723. }
  724. factor = PAGE_SIZE / rdev->lldi.sge_host_page_size;
  725. rdev->qpmask = (rdev->lldi.udb_density * factor) - 1;
  726. rdev->cqmask = (rdev->lldi.ucq_density * factor) - 1;
  727. pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u srq size %u\n",
  728. pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  729. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  730. rdev->lldi.vr->pbl.start,
  731. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  732. rdev->lldi.vr->rq.size,
  733. rdev->lldi.vr->qp.start,
  734. rdev->lldi.vr->qp.size,
  735. rdev->lldi.vr->cq.start,
  736. rdev->lldi.vr->cq.size,
  737. rdev->lldi.vr->srq.size);
  738. pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
  739. &rdev->lldi.pdev->resource[2],
  740. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  741. rdev->qpmask, rdev->cqmask);
  742. if (c4iw_num_stags(rdev) == 0)
  743. return -EINVAL;
  744. rdev->stats.pd.total = T4_MAX_NUM_PD;
  745. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  746. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  747. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  748. rdev->stats.srqt.total = rdev->lldi.vr->srq.size;
  749. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  750. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  751. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev),
  752. T4_MAX_NUM_PD, rdev->lldi.vr->srq.size);
  753. if (err) {
  754. pr_err("error %d initializing resources\n", err);
  755. return err;
  756. }
  757. err = c4iw_pblpool_create(rdev);
  758. if (err) {
  759. pr_err("error %d initializing pbl pool\n", err);
  760. goto destroy_resource;
  761. }
  762. err = c4iw_rqtpool_create(rdev);
  763. if (err) {
  764. pr_err("error %d initializing rqt pool\n", err);
  765. goto destroy_pblpool;
  766. }
  767. err = c4iw_ocqp_pool_create(rdev);
  768. if (err) {
  769. pr_err("error %d initializing ocqp pool\n", err);
  770. goto destroy_rqtpool;
  771. }
  772. rdev->status_page = (struct t4_dev_status_page *)
  773. __get_free_page(GFP_KERNEL);
  774. if (!rdev->status_page) {
  775. err = -ENOMEM;
  776. goto destroy_ocqp_pool;
  777. }
  778. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  779. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  780. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  781. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  782. rdev->status_page->write_cmpl_supported = rdev->lldi.write_cmpl_support;
  783. if (c4iw_wr_log) {
  784. rdev->wr_log = kcalloc(1 << c4iw_wr_log_size_order,
  785. sizeof(*rdev->wr_log),
  786. GFP_KERNEL);
  787. if (rdev->wr_log) {
  788. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  789. atomic_set(&rdev->wr_log_idx, 0);
  790. }
  791. }
  792. rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
  793. if (!rdev->free_workq) {
  794. err = -ENOMEM;
  795. goto err_free_status_page_and_wr_log;
  796. }
  797. rdev->status_page->db_off = 0;
  798. init_completion(&rdev->rqt_compl);
  799. init_completion(&rdev->pbl_compl);
  800. kref_init(&rdev->rqt_kref);
  801. kref_init(&rdev->pbl_kref);
  802. return 0;
  803. err_free_status_page_and_wr_log:
  804. if (c4iw_wr_log && rdev->wr_log)
  805. kfree(rdev->wr_log);
  806. free_page((unsigned long)rdev->status_page);
  807. destroy_ocqp_pool:
  808. c4iw_ocqp_pool_destroy(rdev);
  809. destroy_rqtpool:
  810. c4iw_rqtpool_destroy(rdev);
  811. destroy_pblpool:
  812. c4iw_pblpool_destroy(rdev);
  813. destroy_resource:
  814. c4iw_destroy_resource(&rdev->resource);
  815. return err;
  816. }
  817. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  818. {
  819. kfree(rdev->wr_log);
  820. c4iw_release_dev_ucontext(rdev, &rdev->uctx);
  821. free_page((unsigned long)rdev->status_page);
  822. c4iw_pblpool_destroy(rdev);
  823. c4iw_rqtpool_destroy(rdev);
  824. wait_for_completion(&rdev->pbl_compl);
  825. wait_for_completion(&rdev->rqt_compl);
  826. c4iw_ocqp_pool_destroy(rdev);
  827. destroy_workqueue(rdev->free_workq);
  828. c4iw_destroy_resource(&rdev->resource);
  829. }
  830. void c4iw_dealloc(struct uld_ctx *ctx)
  831. {
  832. c4iw_rdev_close(&ctx->dev->rdev);
  833. WARN_ON(!xa_empty(&ctx->dev->cqs));
  834. WARN_ON(!xa_empty(&ctx->dev->qps));
  835. WARN_ON(!xa_empty(&ctx->dev->mrs));
  836. wait_event(ctx->dev->wait, xa_empty(&ctx->dev->hwtids));
  837. WARN_ON(!xa_empty(&ctx->dev->stids));
  838. WARN_ON(!xa_empty(&ctx->dev->atids));
  839. if (ctx->dev->rdev.bar2_kva)
  840. iounmap(ctx->dev->rdev.bar2_kva);
  841. if (ctx->dev->rdev.oc_mw_kva)
  842. iounmap(ctx->dev->rdev.oc_mw_kva);
  843. ib_dealloc_device(&ctx->dev->ibdev);
  844. ctx->dev = NULL;
  845. }
  846. static void c4iw_remove(struct uld_ctx *ctx)
  847. {
  848. pr_debug("c4iw_dev %p\n", ctx->dev);
  849. debugfs_remove_recursive(ctx->dev->debugfs_root);
  850. c4iw_unregister_device(ctx->dev);
  851. c4iw_dealloc(ctx);
  852. }
  853. static int rdma_supported(const struct cxgb4_lld_info *infop)
  854. {
  855. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  856. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  857. infop->vr->cq.size > 0;
  858. }
  859. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  860. {
  861. struct c4iw_dev *devp;
  862. int ret;
  863. if (!rdma_supported(infop)) {
  864. pr_info("%s: RDMA not supported on this device\n",
  865. pci_name(infop->pdev));
  866. return ERR_PTR(-ENOSYS);
  867. }
  868. if (!ocqp_supported(infop))
  869. pr_info("%s: On-Chip Queues not supported on this device\n",
  870. pci_name(infop->pdev));
  871. devp = ib_alloc_device(c4iw_dev, ibdev);
  872. if (!devp) {
  873. pr_err("Cannot allocate ib device\n");
  874. return ERR_PTR(-ENOMEM);
  875. }
  876. devp->rdev.lldi = *infop;
  877. /* init various hw-queue params based on lld info */
  878. pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  879. devp->rdev.lldi.sge_ingpadboundary,
  880. devp->rdev.lldi.sge_egrstatuspagesize);
  881. devp->rdev.hw_queue.t4_eq_status_entries =
  882. devp->rdev.lldi.sge_egrstatuspagesize / 64;
  883. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  884. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  885. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  886. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  887. devp->rdev.hw_queue.t4_max_sq_size =
  888. devp->rdev.hw_queue.t4_max_eq_size -
  889. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  890. devp->rdev.hw_queue.t4_max_qp_depth =
  891. devp->rdev.hw_queue.t4_max_rq_size;
  892. devp->rdev.hw_queue.t4_max_cq_depth =
  893. devp->rdev.hw_queue.t4_max_iq_size - 2;
  894. devp->rdev.hw_queue.t4_stat_len =
  895. devp->rdev.lldi.sge_egrstatuspagesize;
  896. /*
  897. * For T5/T6 devices, we map all of BAR2 with WC.
  898. * For T4 devices with onchip qp mem, we map only that part
  899. * of BAR2 with WC.
  900. */
  901. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  902. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  903. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  904. pci_resource_len(devp->rdev.lldi.pdev, 2));
  905. if (!devp->rdev.bar2_kva) {
  906. pr_err("Unable to ioremap BAR2\n");
  907. ib_dealloc_device(&devp->ibdev);
  908. return ERR_PTR(-EINVAL);
  909. }
  910. } else if (ocqp_supported(infop)) {
  911. devp->rdev.oc_mw_pa =
  912. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  913. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  914. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  915. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  916. devp->rdev.lldi.vr->ocq.size);
  917. if (!devp->rdev.oc_mw_kva) {
  918. pr_err("Unable to ioremap onchip mem\n");
  919. ib_dealloc_device(&devp->ibdev);
  920. return ERR_PTR(-EINVAL);
  921. }
  922. }
  923. pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  924. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  925. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  926. ret = c4iw_rdev_open(&devp->rdev);
  927. if (ret) {
  928. pr_err("Unable to open CXIO rdev err %d\n", ret);
  929. ib_dealloc_device(&devp->ibdev);
  930. return ERR_PTR(ret);
  931. }
  932. xa_init_flags(&devp->cqs, XA_FLAGS_LOCK_IRQ);
  933. xa_init_flags(&devp->qps, XA_FLAGS_LOCK_IRQ);
  934. xa_init_flags(&devp->mrs, XA_FLAGS_LOCK_IRQ);
  935. xa_init_flags(&devp->hwtids, XA_FLAGS_LOCK_IRQ);
  936. xa_init_flags(&devp->atids, XA_FLAGS_LOCK_IRQ);
  937. xa_init_flags(&devp->stids, XA_FLAGS_LOCK_IRQ);
  938. mutex_init(&devp->rdev.stats.lock);
  939. mutex_init(&devp->db_mutex);
  940. INIT_LIST_HEAD(&devp->db_fc_list);
  941. init_waitqueue_head(&devp->wait);
  942. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  943. if (c4iw_debugfs_root) {
  944. devp->debugfs_root = debugfs_create_dir(
  945. pci_name(devp->rdev.lldi.pdev),
  946. c4iw_debugfs_root);
  947. setup_debugfs(devp);
  948. }
  949. return devp;
  950. }
  951. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  952. {
  953. struct uld_ctx *ctx;
  954. static int vers_printed;
  955. int i;
  956. if (!vers_printed++)
  957. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  958. DRV_VERSION);
  959. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  960. if (!ctx) {
  961. ctx = ERR_PTR(-ENOMEM);
  962. goto out;
  963. }
  964. ctx->lldi = *infop;
  965. pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  966. pci_name(ctx->lldi.pdev),
  967. ctx->lldi.nchan, ctx->lldi.nrxq,
  968. ctx->lldi.ntxq, ctx->lldi.nports);
  969. mutex_lock(&dev_mutex);
  970. list_add_tail(&ctx->entry, &uld_ctx_list);
  971. mutex_unlock(&dev_mutex);
  972. for (i = 0; i < ctx->lldi.nrxq; i++)
  973. pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  974. out:
  975. return ctx;
  976. }
  977. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  978. const __be64 *rsp,
  979. u32 pktshift)
  980. {
  981. struct sk_buff *skb;
  982. /*
  983. * Allocate space for cpl_pass_accept_req which will be synthesized by
  984. * driver. Once the driver synthesizes the request the skb will go
  985. * through the regular cpl_pass_accept_req processing.
  986. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  987. * cpl_rx_pkt.
  988. */
  989. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  990. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  991. if (unlikely(!skb))
  992. return NULL;
  993. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  994. sizeof(struct rss_header) - pktshift);
  995. /*
  996. * This skb will contain:
  997. * rss_header from the rspq descriptor (1 flit)
  998. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  999. * space for the difference between the size of an
  1000. * rx_pkt and pass_accept_req cpl (1 flit)
  1001. * the packet data from the gl
  1002. */
  1003. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  1004. sizeof(struct rss_header));
  1005. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  1006. sizeof(struct cpl_pass_accept_req),
  1007. gl->va + pktshift,
  1008. gl->tot_len - pktshift);
  1009. return skb;
  1010. }
  1011. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  1012. const __be64 *rsp)
  1013. {
  1014. unsigned int opcode = *(u8 *)rsp;
  1015. struct sk_buff *skb;
  1016. if (opcode != CPL_RX_PKT)
  1017. goto out;
  1018. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  1019. if (skb == NULL)
  1020. goto out;
  1021. if (c4iw_handlers[opcode] == NULL) {
  1022. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1023. kfree_skb(skb);
  1024. goto out;
  1025. }
  1026. c4iw_handlers[opcode](dev, skb);
  1027. return 1;
  1028. out:
  1029. return 0;
  1030. }
  1031. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1032. const struct pkt_gl *gl)
  1033. {
  1034. struct uld_ctx *ctx = handle;
  1035. struct c4iw_dev *dev = ctx->dev;
  1036. struct sk_buff *skb;
  1037. u8 opcode;
  1038. if (gl == NULL) {
  1039. /* omit RSS and rsp_ctrl at end of descriptor */
  1040. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1041. skb = alloc_skb(256, GFP_ATOMIC);
  1042. if (!skb)
  1043. goto nomem;
  1044. __skb_put(skb, len);
  1045. skb_copy_to_linear_data(skb, &rsp[1], len);
  1046. } else if (gl == CXGB4_MSG_AN) {
  1047. const struct rsp_ctrl *rc = (void *)rsp;
  1048. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1049. c4iw_ev_handler(dev, qid);
  1050. return 0;
  1051. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1052. if (recv_rx_pkt(dev, gl, rsp))
  1053. return 0;
  1054. pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
  1055. pci_name(ctx->lldi.pdev), gl->va,
  1056. be64_to_cpu(*rsp),
  1057. be64_to_cpu(*(__force __be64 *)gl->va),
  1058. gl->tot_len);
  1059. return 0;
  1060. } else {
  1061. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1062. if (unlikely(!skb))
  1063. goto nomem;
  1064. }
  1065. opcode = *(u8 *)rsp;
  1066. if (c4iw_handlers[opcode]) {
  1067. c4iw_handlers[opcode](dev, skb);
  1068. } else {
  1069. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1070. kfree_skb(skb);
  1071. }
  1072. return 0;
  1073. nomem:
  1074. return -1;
  1075. }
  1076. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1077. {
  1078. struct uld_ctx *ctx = handle;
  1079. pr_debug("new_state %u\n", new_state);
  1080. switch (new_state) {
  1081. case CXGB4_STATE_UP:
  1082. pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
  1083. if (!ctx->dev) {
  1084. ctx->dev = c4iw_alloc(&ctx->lldi);
  1085. if (IS_ERR(ctx->dev)) {
  1086. pr_err("%s: initialization failed: %ld\n",
  1087. pci_name(ctx->lldi.pdev),
  1088. PTR_ERR(ctx->dev));
  1089. ctx->dev = NULL;
  1090. break;
  1091. }
  1092. INIT_WORK(&ctx->reg_work, c4iw_register_device);
  1093. queue_work(reg_workq, &ctx->reg_work);
  1094. }
  1095. break;
  1096. case CXGB4_STATE_DOWN:
  1097. pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
  1098. if (ctx->dev)
  1099. c4iw_remove(ctx);
  1100. break;
  1101. case CXGB4_STATE_FATAL_ERROR:
  1102. case CXGB4_STATE_START_RECOVERY:
  1103. pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
  1104. if (ctx->dev) {
  1105. struct ib_event event = {};
  1106. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1107. event.event = IB_EVENT_DEVICE_FATAL;
  1108. event.device = &ctx->dev->ibdev;
  1109. ib_dispatch_event(&event);
  1110. c4iw_remove(ctx);
  1111. }
  1112. break;
  1113. case CXGB4_STATE_DETACH:
  1114. pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
  1115. if (ctx->dev)
  1116. c4iw_remove(ctx);
  1117. break;
  1118. }
  1119. return 0;
  1120. }
  1121. static void stop_queues(struct uld_ctx *ctx)
  1122. {
  1123. struct c4iw_qp *qp;
  1124. unsigned long index, flags;
  1125. xa_lock_irqsave(&ctx->dev->qps, flags);
  1126. ctx->dev->rdev.stats.db_state_transitions++;
  1127. ctx->dev->db_state = STOPPED;
  1128. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1129. xa_for_each(&ctx->dev->qps, index, qp)
  1130. t4_disable_wq_db(&qp->wq);
  1131. } else {
  1132. ctx->dev->rdev.status_page->db_off = 1;
  1133. }
  1134. xa_unlock_irqrestore(&ctx->dev->qps, flags);
  1135. }
  1136. static void resume_rc_qp(struct c4iw_qp *qp)
  1137. {
  1138. spin_lock(&qp->lock);
  1139. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1140. qp->wq.sq.wq_pidx_inc = 0;
  1141. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1142. qp->wq.rq.wq_pidx_inc = 0;
  1143. spin_unlock(&qp->lock);
  1144. }
  1145. static void resume_a_chunk(struct uld_ctx *ctx)
  1146. {
  1147. int i;
  1148. struct c4iw_qp *qp;
  1149. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1150. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1151. db_fc_entry);
  1152. list_del_init(&qp->db_fc_entry);
  1153. resume_rc_qp(qp);
  1154. if (list_empty(&ctx->dev->db_fc_list))
  1155. break;
  1156. }
  1157. }
  1158. static void resume_queues(struct uld_ctx *ctx)
  1159. {
  1160. xa_lock_irq(&ctx->dev->qps);
  1161. if (ctx->dev->db_state != STOPPED)
  1162. goto out;
  1163. ctx->dev->db_state = FLOW_CONTROL;
  1164. while (1) {
  1165. if (list_empty(&ctx->dev->db_fc_list)) {
  1166. struct c4iw_qp *qp;
  1167. unsigned long index;
  1168. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1169. ctx->dev->db_state = NORMAL;
  1170. ctx->dev->rdev.stats.db_state_transitions++;
  1171. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1172. xa_for_each(&ctx->dev->qps, index, qp)
  1173. t4_enable_wq_db(&qp->wq);
  1174. } else {
  1175. ctx->dev->rdev.status_page->db_off = 0;
  1176. }
  1177. break;
  1178. } else {
  1179. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1180. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1181. DB_FC_DRAIN_THRESH)) {
  1182. resume_a_chunk(ctx);
  1183. }
  1184. if (!list_empty(&ctx->dev->db_fc_list)) {
  1185. xa_unlock_irq(&ctx->dev->qps);
  1186. if (DB_FC_RESUME_DELAY) {
  1187. set_current_state(TASK_UNINTERRUPTIBLE);
  1188. schedule_timeout(DB_FC_RESUME_DELAY);
  1189. }
  1190. xa_lock_irq(&ctx->dev->qps);
  1191. if (ctx->dev->db_state != FLOW_CONTROL)
  1192. break;
  1193. }
  1194. }
  1195. }
  1196. out:
  1197. if (ctx->dev->db_state != NORMAL)
  1198. ctx->dev->rdev.stats.db_fc_interruptions++;
  1199. xa_unlock_irq(&ctx->dev->qps);
  1200. }
  1201. struct qp_list {
  1202. unsigned idx;
  1203. struct c4iw_qp **qps;
  1204. };
  1205. static void deref_qps(struct qp_list *qp_list)
  1206. {
  1207. int idx;
  1208. for (idx = 0; idx < qp_list->idx; idx++)
  1209. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1210. }
  1211. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1212. {
  1213. int idx;
  1214. int ret;
  1215. for (idx = 0; idx < qp_list->idx; idx++) {
  1216. struct c4iw_qp *qp = qp_list->qps[idx];
  1217. xa_lock_irq(&qp->rhp->qps);
  1218. spin_lock(&qp->lock);
  1219. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1220. qp->wq.sq.qid,
  1221. t4_sq_host_wq_pidx(&qp->wq),
  1222. t4_sq_wq_size(&qp->wq));
  1223. if (ret) {
  1224. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
  1225. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1226. spin_unlock(&qp->lock);
  1227. xa_unlock_irq(&qp->rhp->qps);
  1228. return;
  1229. }
  1230. qp->wq.sq.wq_pidx_inc = 0;
  1231. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1232. qp->wq.rq.qid,
  1233. t4_rq_host_wq_pidx(&qp->wq),
  1234. t4_rq_wq_size(&qp->wq));
  1235. if (ret) {
  1236. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
  1237. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1238. spin_unlock(&qp->lock);
  1239. xa_unlock_irq(&qp->rhp->qps);
  1240. return;
  1241. }
  1242. qp->wq.rq.wq_pidx_inc = 0;
  1243. spin_unlock(&qp->lock);
  1244. xa_unlock_irq(&qp->rhp->qps);
  1245. /* Wait for the dbfifo to drain */
  1246. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1247. set_current_state(TASK_UNINTERRUPTIBLE);
  1248. schedule_timeout(usecs_to_jiffies(10));
  1249. }
  1250. }
  1251. }
  1252. static void recover_queues(struct uld_ctx *ctx)
  1253. {
  1254. struct c4iw_qp *qp;
  1255. unsigned long index;
  1256. int count = 0;
  1257. struct qp_list qp_list;
  1258. int ret;
  1259. /* slow everybody down */
  1260. set_current_state(TASK_UNINTERRUPTIBLE);
  1261. schedule_timeout(usecs_to_jiffies(1000));
  1262. /* flush the SGE contexts */
  1263. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1264. if (ret) {
  1265. pr_err("%s: Fatal error - DB overflow recovery failed\n",
  1266. pci_name(ctx->lldi.pdev));
  1267. return;
  1268. }
  1269. /* Count active queues so we can build a list of queues to recover */
  1270. xa_lock_irq(&ctx->dev->qps);
  1271. WARN_ON(ctx->dev->db_state != STOPPED);
  1272. ctx->dev->db_state = RECOVERY;
  1273. xa_for_each(&ctx->dev->qps, index, qp)
  1274. count++;
  1275. qp_list.qps = kcalloc(count, sizeof(*qp_list.qps), GFP_ATOMIC);
  1276. if (!qp_list.qps) {
  1277. xa_unlock_irq(&ctx->dev->qps);
  1278. return;
  1279. }
  1280. qp_list.idx = 0;
  1281. /* add and ref each qp so it doesn't get freed */
  1282. xa_for_each(&ctx->dev->qps, index, qp) {
  1283. c4iw_qp_add_ref(&qp->ibqp);
  1284. qp_list.qps[qp_list.idx++] = qp;
  1285. }
  1286. xa_unlock_irq(&ctx->dev->qps);
  1287. /* now traverse the list in a safe context to recover the db state*/
  1288. recover_lost_dbs(ctx, &qp_list);
  1289. /* we're almost done! deref the qps and clean up */
  1290. deref_qps(&qp_list);
  1291. kfree(qp_list.qps);
  1292. xa_lock_irq(&ctx->dev->qps);
  1293. WARN_ON(ctx->dev->db_state != RECOVERY);
  1294. ctx->dev->db_state = STOPPED;
  1295. xa_unlock_irq(&ctx->dev->qps);
  1296. }
  1297. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1298. {
  1299. struct uld_ctx *ctx = handle;
  1300. switch (control) {
  1301. case CXGB4_CONTROL_DB_FULL:
  1302. stop_queues(ctx);
  1303. ctx->dev->rdev.stats.db_full++;
  1304. break;
  1305. case CXGB4_CONTROL_DB_EMPTY:
  1306. resume_queues(ctx);
  1307. mutex_lock(&ctx->dev->rdev.stats.lock);
  1308. ctx->dev->rdev.stats.db_empty++;
  1309. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1310. break;
  1311. case CXGB4_CONTROL_DB_DROP:
  1312. recover_queues(ctx);
  1313. mutex_lock(&ctx->dev->rdev.stats.lock);
  1314. ctx->dev->rdev.stats.db_drop++;
  1315. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1316. break;
  1317. default:
  1318. pr_warn("%s: unknown control cmd %u\n",
  1319. pci_name(ctx->lldi.pdev), control);
  1320. break;
  1321. }
  1322. return 0;
  1323. }
  1324. static struct cxgb4_uld_info c4iw_uld_info = {
  1325. .name = DRV_NAME,
  1326. .nrxq = MAX_ULD_QSETS,
  1327. .ntxq = MAX_ULD_QSETS,
  1328. .rxq_size = 511,
  1329. .ciq = true,
  1330. .lro = false,
  1331. .add = c4iw_uld_add,
  1332. .rx_handler = c4iw_uld_rx_handler,
  1333. .state_change = c4iw_uld_state_change,
  1334. .control = c4iw_uld_control,
  1335. };
  1336. void _c4iw_free_wr_wait(struct kref *kref)
  1337. {
  1338. struct c4iw_wr_wait *wr_waitp;
  1339. wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
  1340. pr_debug("Free wr_wait %p\n", wr_waitp);
  1341. kfree(wr_waitp);
  1342. }
  1343. struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
  1344. {
  1345. struct c4iw_wr_wait *wr_waitp;
  1346. wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
  1347. if (wr_waitp) {
  1348. kref_init(&wr_waitp->kref);
  1349. pr_debug("wr_wait %p\n", wr_waitp);
  1350. }
  1351. return wr_waitp;
  1352. }
  1353. static int __init c4iw_init_module(void)
  1354. {
  1355. int err;
  1356. err = c4iw_cm_init();
  1357. if (err)
  1358. return err;
  1359. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1360. reg_workq = create_singlethread_workqueue("Register_iWARP_device");
  1361. if (!reg_workq) {
  1362. pr_err("Failed creating workqueue to register iwarp device\n");
  1363. return -ENOMEM;
  1364. }
  1365. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1366. return 0;
  1367. }
  1368. static void __exit c4iw_exit_module(void)
  1369. {
  1370. struct uld_ctx *ctx, *tmp;
  1371. mutex_lock(&dev_mutex);
  1372. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1373. if (ctx->dev)
  1374. c4iw_remove(ctx);
  1375. kfree(ctx);
  1376. }
  1377. mutex_unlock(&dev_mutex);
  1378. destroy_workqueue(reg_workq);
  1379. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1380. c4iw_cm_term();
  1381. debugfs_remove_recursive(c4iw_debugfs_root);
  1382. }
  1383. module_init(c4iw_init_module);
  1384. module_exit(c4iw_exit_module);