ipu-common.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2010 Sascha Hauer <[email protected]>
  4. * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/export.h>
  8. #include <linux/types.h>
  9. #include <linux/reset.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/err.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/clk.h>
  17. #include <linux/list.h>
  18. #include <linux/irq.h>
  19. #include <linux/irqchip/chained_irq.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of_graph.h>
  23. #include <drm/drm_fourcc.h>
  24. #include <video/imx-ipu-v3.h>
  25. #include "ipu-prv.h"
  26. static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  27. {
  28. return readl(ipu->cm_reg + offset);
  29. }
  30. static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  31. {
  32. writel(value, ipu->cm_reg + offset);
  33. }
  34. int ipu_get_num(struct ipu_soc *ipu)
  35. {
  36. return ipu->id;
  37. }
  38. EXPORT_SYMBOL_GPL(ipu_get_num);
  39. void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
  40. {
  41. u32 val;
  42. val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  43. val &= ~DP_S_SRM_MODE_MASK;
  44. val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
  45. DP_S_SRM_MODE_NOW;
  46. ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  47. }
  48. EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
  49. enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  50. {
  51. switch (drm_fourcc) {
  52. case DRM_FORMAT_ARGB1555:
  53. case DRM_FORMAT_ABGR1555:
  54. case DRM_FORMAT_RGBA5551:
  55. case DRM_FORMAT_BGRA5551:
  56. case DRM_FORMAT_RGB565:
  57. case DRM_FORMAT_BGR565:
  58. case DRM_FORMAT_RGB888:
  59. case DRM_FORMAT_BGR888:
  60. case DRM_FORMAT_ARGB4444:
  61. case DRM_FORMAT_XRGB8888:
  62. case DRM_FORMAT_XBGR8888:
  63. case DRM_FORMAT_RGBX8888:
  64. case DRM_FORMAT_BGRX8888:
  65. case DRM_FORMAT_ARGB8888:
  66. case DRM_FORMAT_ABGR8888:
  67. case DRM_FORMAT_RGBA8888:
  68. case DRM_FORMAT_BGRA8888:
  69. case DRM_FORMAT_RGB565_A8:
  70. case DRM_FORMAT_BGR565_A8:
  71. case DRM_FORMAT_RGB888_A8:
  72. case DRM_FORMAT_BGR888_A8:
  73. case DRM_FORMAT_RGBX8888_A8:
  74. case DRM_FORMAT_BGRX8888_A8:
  75. return IPUV3_COLORSPACE_RGB;
  76. case DRM_FORMAT_YUYV:
  77. case DRM_FORMAT_UYVY:
  78. case DRM_FORMAT_YUV420:
  79. case DRM_FORMAT_YVU420:
  80. case DRM_FORMAT_YUV422:
  81. case DRM_FORMAT_YVU422:
  82. case DRM_FORMAT_YUV444:
  83. case DRM_FORMAT_YVU444:
  84. case DRM_FORMAT_NV12:
  85. case DRM_FORMAT_NV21:
  86. case DRM_FORMAT_NV16:
  87. case DRM_FORMAT_NV61:
  88. return IPUV3_COLORSPACE_YUV;
  89. default:
  90. return IPUV3_COLORSPACE_UNKNOWN;
  91. }
  92. }
  93. EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
  94. enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
  95. {
  96. switch (pixelformat) {
  97. case V4L2_PIX_FMT_YUV420:
  98. case V4L2_PIX_FMT_YVU420:
  99. case V4L2_PIX_FMT_YUV422P:
  100. case V4L2_PIX_FMT_UYVY:
  101. case V4L2_PIX_FMT_YUYV:
  102. case V4L2_PIX_FMT_NV12:
  103. case V4L2_PIX_FMT_NV21:
  104. case V4L2_PIX_FMT_NV16:
  105. case V4L2_PIX_FMT_NV61:
  106. return IPUV3_COLORSPACE_YUV;
  107. case V4L2_PIX_FMT_RGB565:
  108. case V4L2_PIX_FMT_BGR24:
  109. case V4L2_PIX_FMT_RGB24:
  110. case V4L2_PIX_FMT_ABGR32:
  111. case V4L2_PIX_FMT_XBGR32:
  112. case V4L2_PIX_FMT_BGRA32:
  113. case V4L2_PIX_FMT_BGRX32:
  114. case V4L2_PIX_FMT_RGBA32:
  115. case V4L2_PIX_FMT_RGBX32:
  116. case V4L2_PIX_FMT_ARGB32:
  117. case V4L2_PIX_FMT_XRGB32:
  118. case V4L2_PIX_FMT_RGB32:
  119. case V4L2_PIX_FMT_BGR32:
  120. return IPUV3_COLORSPACE_RGB;
  121. default:
  122. return IPUV3_COLORSPACE_UNKNOWN;
  123. }
  124. }
  125. EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
  126. int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
  127. bool hflip, bool vflip)
  128. {
  129. u32 r90, vf, hf;
  130. switch (degrees) {
  131. case 0:
  132. vf = hf = r90 = 0;
  133. break;
  134. case 90:
  135. vf = hf = 0;
  136. r90 = 1;
  137. break;
  138. case 180:
  139. vf = hf = 1;
  140. r90 = 0;
  141. break;
  142. case 270:
  143. vf = hf = r90 = 1;
  144. break;
  145. default:
  146. return -EINVAL;
  147. }
  148. hf ^= (u32)hflip;
  149. vf ^= (u32)vflip;
  150. *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
  151. return 0;
  152. }
  153. EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
  154. int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
  155. bool hflip, bool vflip)
  156. {
  157. u32 r90, vf, hf;
  158. r90 = ((u32)mode >> 2) & 0x1;
  159. hf = ((u32)mode >> 1) & 0x1;
  160. vf = ((u32)mode >> 0) & 0x1;
  161. hf ^= (u32)hflip;
  162. vf ^= (u32)vflip;
  163. switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
  164. case IPU_ROTATE_NONE:
  165. *degrees = 0;
  166. break;
  167. case IPU_ROTATE_90_RIGHT:
  168. *degrees = 90;
  169. break;
  170. case IPU_ROTATE_180:
  171. *degrees = 180;
  172. break;
  173. case IPU_ROTATE_90_LEFT:
  174. *degrees = 270;
  175. break;
  176. default:
  177. return -EINVAL;
  178. }
  179. return 0;
  180. }
  181. EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
  182. struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
  183. {
  184. struct ipuv3_channel *channel;
  185. dev_dbg(ipu->dev, "%s %d\n", __func__, num);
  186. if (num > 63)
  187. return ERR_PTR(-ENODEV);
  188. mutex_lock(&ipu->channel_lock);
  189. list_for_each_entry(channel, &ipu->channels, list) {
  190. if (channel->num == num) {
  191. channel = ERR_PTR(-EBUSY);
  192. goto out;
  193. }
  194. }
  195. channel = kzalloc(sizeof(*channel), GFP_KERNEL);
  196. if (!channel) {
  197. channel = ERR_PTR(-ENOMEM);
  198. goto out;
  199. }
  200. channel->num = num;
  201. channel->ipu = ipu;
  202. list_add(&channel->list, &ipu->channels);
  203. out:
  204. mutex_unlock(&ipu->channel_lock);
  205. return channel;
  206. }
  207. EXPORT_SYMBOL_GPL(ipu_idmac_get);
  208. void ipu_idmac_put(struct ipuv3_channel *channel)
  209. {
  210. struct ipu_soc *ipu = channel->ipu;
  211. dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
  212. mutex_lock(&ipu->channel_lock);
  213. list_del(&channel->list);
  214. kfree(channel);
  215. mutex_unlock(&ipu->channel_lock);
  216. }
  217. EXPORT_SYMBOL_GPL(ipu_idmac_put);
  218. #define idma_mask(ch) (1 << ((ch) & 0x1f))
  219. /*
  220. * This is an undocumented feature, a write one to a channel bit in
  221. * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
  222. * internal current buffer pointer so that transfers start from buffer
  223. * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
  224. * only says these are read-only registers). This operation is required
  225. * for channel linking to work correctly, for instance video capture
  226. * pipelines that carry out image rotations will fail after the first
  227. * streaming unless this function is called for each channel before
  228. * re-enabling the channels.
  229. */
  230. static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
  231. {
  232. struct ipu_soc *ipu = channel->ipu;
  233. unsigned int chno = channel->num;
  234. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
  235. }
  236. void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
  237. bool doublebuffer)
  238. {
  239. struct ipu_soc *ipu = channel->ipu;
  240. unsigned long flags;
  241. u32 reg;
  242. spin_lock_irqsave(&ipu->lock, flags);
  243. reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
  244. if (doublebuffer)
  245. reg |= idma_mask(channel->num);
  246. else
  247. reg &= ~idma_mask(channel->num);
  248. ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
  249. __ipu_idmac_reset_current_buffer(channel);
  250. spin_unlock_irqrestore(&ipu->lock, flags);
  251. }
  252. EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
  253. static const struct {
  254. int chnum;
  255. u32 reg;
  256. int shift;
  257. } idmac_lock_en_info[] = {
  258. { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
  259. { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
  260. { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
  261. { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
  262. { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
  263. { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
  264. { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
  265. { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
  266. { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
  267. { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
  268. { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
  269. { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
  270. { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
  271. { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
  272. { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
  273. { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
  274. { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
  275. };
  276. int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
  277. {
  278. struct ipu_soc *ipu = channel->ipu;
  279. unsigned long flags;
  280. u32 bursts, regval;
  281. int i;
  282. switch (num_bursts) {
  283. case 0:
  284. case 1:
  285. bursts = 0x00; /* locking disabled */
  286. break;
  287. case 2:
  288. bursts = 0x01;
  289. break;
  290. case 4:
  291. bursts = 0x02;
  292. break;
  293. case 8:
  294. bursts = 0x03;
  295. break;
  296. default:
  297. return -EINVAL;
  298. }
  299. /*
  300. * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
  301. * i.MX53 channel arbitration locking doesn't seem to work properly.
  302. * Allow enabling the lock feature on IPUv3H / i.MX6 only.
  303. */
  304. if (bursts && ipu->ipu_type != IPUV3H)
  305. return -EINVAL;
  306. for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
  307. if (channel->num == idmac_lock_en_info[i].chnum)
  308. break;
  309. }
  310. if (i >= ARRAY_SIZE(idmac_lock_en_info))
  311. return -EINVAL;
  312. spin_lock_irqsave(&ipu->lock, flags);
  313. regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
  314. regval &= ~(0x03 << idmac_lock_en_info[i].shift);
  315. regval |= (bursts << idmac_lock_en_info[i].shift);
  316. ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
  317. spin_unlock_irqrestore(&ipu->lock, flags);
  318. return 0;
  319. }
  320. EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
  321. int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
  322. {
  323. unsigned long lock_flags;
  324. u32 val;
  325. spin_lock_irqsave(&ipu->lock, lock_flags);
  326. val = ipu_cm_read(ipu, IPU_DISP_GEN);
  327. if (mask & IPU_CONF_DI0_EN)
  328. val |= IPU_DI0_COUNTER_RELEASE;
  329. if (mask & IPU_CONF_DI1_EN)
  330. val |= IPU_DI1_COUNTER_RELEASE;
  331. ipu_cm_write(ipu, val, IPU_DISP_GEN);
  332. val = ipu_cm_read(ipu, IPU_CONF);
  333. val |= mask;
  334. ipu_cm_write(ipu, val, IPU_CONF);
  335. spin_unlock_irqrestore(&ipu->lock, lock_flags);
  336. return 0;
  337. }
  338. EXPORT_SYMBOL_GPL(ipu_module_enable);
  339. int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
  340. {
  341. unsigned long lock_flags;
  342. u32 val;
  343. spin_lock_irqsave(&ipu->lock, lock_flags);
  344. val = ipu_cm_read(ipu, IPU_CONF);
  345. val &= ~mask;
  346. ipu_cm_write(ipu, val, IPU_CONF);
  347. val = ipu_cm_read(ipu, IPU_DISP_GEN);
  348. if (mask & IPU_CONF_DI0_EN)
  349. val &= ~IPU_DI0_COUNTER_RELEASE;
  350. if (mask & IPU_CONF_DI1_EN)
  351. val &= ~IPU_DI1_COUNTER_RELEASE;
  352. ipu_cm_write(ipu, val, IPU_DISP_GEN);
  353. spin_unlock_irqrestore(&ipu->lock, lock_flags);
  354. return 0;
  355. }
  356. EXPORT_SYMBOL_GPL(ipu_module_disable);
  357. int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
  358. {
  359. struct ipu_soc *ipu = channel->ipu;
  360. unsigned int chno = channel->num;
  361. return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
  362. }
  363. EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
  364. bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
  365. {
  366. struct ipu_soc *ipu = channel->ipu;
  367. unsigned long flags;
  368. u32 reg = 0;
  369. spin_lock_irqsave(&ipu->lock, flags);
  370. switch (buf_num) {
  371. case 0:
  372. reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
  373. break;
  374. case 1:
  375. reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
  376. break;
  377. case 2:
  378. reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
  379. break;
  380. }
  381. spin_unlock_irqrestore(&ipu->lock, flags);
  382. return ((reg & idma_mask(channel->num)) != 0);
  383. }
  384. EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
  385. void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
  386. {
  387. struct ipu_soc *ipu = channel->ipu;
  388. unsigned int chno = channel->num;
  389. unsigned long flags;
  390. spin_lock_irqsave(&ipu->lock, flags);
  391. /* Mark buffer as ready. */
  392. if (buf_num == 0)
  393. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
  394. else
  395. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
  396. spin_unlock_irqrestore(&ipu->lock, flags);
  397. }
  398. EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
  399. void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
  400. {
  401. struct ipu_soc *ipu = channel->ipu;
  402. unsigned int chno = channel->num;
  403. unsigned long flags;
  404. spin_lock_irqsave(&ipu->lock, flags);
  405. ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
  406. switch (buf_num) {
  407. case 0:
  408. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
  409. break;
  410. case 1:
  411. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
  412. break;
  413. case 2:
  414. ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
  415. break;
  416. default:
  417. break;
  418. }
  419. ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
  420. spin_unlock_irqrestore(&ipu->lock, flags);
  421. }
  422. EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
  423. int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
  424. {
  425. struct ipu_soc *ipu = channel->ipu;
  426. u32 val;
  427. unsigned long flags;
  428. spin_lock_irqsave(&ipu->lock, flags);
  429. val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
  430. val |= idma_mask(channel->num);
  431. ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
  432. spin_unlock_irqrestore(&ipu->lock, flags);
  433. return 0;
  434. }
  435. EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
  436. bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
  437. {
  438. return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
  439. }
  440. EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
  441. int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
  442. {
  443. struct ipu_soc *ipu = channel->ipu;
  444. unsigned long timeout;
  445. timeout = jiffies + msecs_to_jiffies(ms);
  446. while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
  447. idma_mask(channel->num)) {
  448. if (time_after(jiffies, timeout))
  449. return -ETIMEDOUT;
  450. cpu_relax();
  451. }
  452. return 0;
  453. }
  454. EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
  455. int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
  456. {
  457. struct ipu_soc *ipu = channel->ipu;
  458. u32 val;
  459. unsigned long flags;
  460. spin_lock_irqsave(&ipu->lock, flags);
  461. /* Disable DMA channel(s) */
  462. val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
  463. val &= ~idma_mask(channel->num);
  464. ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
  465. __ipu_idmac_reset_current_buffer(channel);
  466. /* Set channel buffers NOT to be ready */
  467. ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
  468. if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
  469. idma_mask(channel->num)) {
  470. ipu_cm_write(ipu, idma_mask(channel->num),
  471. IPU_CHA_BUF0_RDY(channel->num));
  472. }
  473. if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
  474. idma_mask(channel->num)) {
  475. ipu_cm_write(ipu, idma_mask(channel->num),
  476. IPU_CHA_BUF1_RDY(channel->num));
  477. }
  478. ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
  479. /* Reset the double buffer */
  480. val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
  481. val &= ~idma_mask(channel->num);
  482. ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
  483. spin_unlock_irqrestore(&ipu->lock, flags);
  484. return 0;
  485. }
  486. EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
  487. /*
  488. * The imx6 rev. D TRM says that enabling the WM feature will increase
  489. * a channel's priority. Refer to Table 36-8 Calculated priority value.
  490. * The sub-module that is the sink or source for the channel must enable
  491. * watermark signal for this to take effect (SMFC_WM for instance).
  492. */
  493. void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
  494. {
  495. struct ipu_soc *ipu = channel->ipu;
  496. unsigned long flags;
  497. u32 val;
  498. spin_lock_irqsave(&ipu->lock, flags);
  499. val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
  500. if (enable)
  501. val |= 1 << (channel->num % 32);
  502. else
  503. val &= ~(1 << (channel->num % 32));
  504. ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
  505. spin_unlock_irqrestore(&ipu->lock, flags);
  506. }
  507. EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
  508. static int ipu_memory_reset(struct ipu_soc *ipu)
  509. {
  510. unsigned long timeout;
  511. ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
  512. timeout = jiffies + msecs_to_jiffies(1000);
  513. while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
  514. if (time_after(jiffies, timeout))
  515. return -ETIME;
  516. cpu_relax();
  517. }
  518. return 0;
  519. }
  520. /*
  521. * Set the source mux for the given CSI. Selects either parallel or
  522. * MIPI CSI2 sources.
  523. */
  524. void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
  525. {
  526. unsigned long flags;
  527. u32 val, mask;
  528. mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
  529. IPU_CONF_CSI0_DATA_SOURCE;
  530. spin_lock_irqsave(&ipu->lock, flags);
  531. val = ipu_cm_read(ipu, IPU_CONF);
  532. if (mipi_csi2)
  533. val |= mask;
  534. else
  535. val &= ~mask;
  536. ipu_cm_write(ipu, val, IPU_CONF);
  537. spin_unlock_irqrestore(&ipu->lock, flags);
  538. }
  539. EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
  540. /*
  541. * Set the source mux for the IC. Selects either CSI[01] or the VDI.
  542. */
  543. void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
  544. {
  545. unsigned long flags;
  546. u32 val;
  547. spin_lock_irqsave(&ipu->lock, flags);
  548. val = ipu_cm_read(ipu, IPU_CONF);
  549. if (vdi)
  550. val |= IPU_CONF_IC_INPUT;
  551. else
  552. val &= ~IPU_CONF_IC_INPUT;
  553. if (csi_id == 1)
  554. val |= IPU_CONF_CSI_SEL;
  555. else
  556. val &= ~IPU_CONF_CSI_SEL;
  557. ipu_cm_write(ipu, val, IPU_CONF);
  558. spin_unlock_irqrestore(&ipu->lock, flags);
  559. }
  560. EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
  561. /* Frame Synchronization Unit Channel Linking */
  562. struct fsu_link_reg_info {
  563. int chno;
  564. u32 reg;
  565. u32 mask;
  566. u32 val;
  567. };
  568. struct fsu_link_info {
  569. struct fsu_link_reg_info src;
  570. struct fsu_link_reg_info sink;
  571. };
  572. static const struct fsu_link_info fsu_link_info[] = {
  573. {
  574. .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
  575. FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
  576. .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
  577. FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
  578. }, {
  579. .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
  580. FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
  581. .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
  582. FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
  583. }, {
  584. .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
  585. FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
  586. .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
  587. FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
  588. }, {
  589. .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
  590. .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
  591. FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
  592. },
  593. };
  594. static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
  595. {
  596. int i;
  597. for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
  598. if (src == fsu_link_info[i].src.chno &&
  599. sink == fsu_link_info[i].sink.chno)
  600. return &fsu_link_info[i];
  601. }
  602. return NULL;
  603. }
  604. /*
  605. * Links a source channel to a sink channel in the FSU.
  606. */
  607. int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
  608. {
  609. const struct fsu_link_info *link;
  610. u32 src_reg, sink_reg;
  611. unsigned long flags;
  612. link = find_fsu_link_info(src_ch, sink_ch);
  613. if (!link)
  614. return -EINVAL;
  615. spin_lock_irqsave(&ipu->lock, flags);
  616. if (link->src.mask) {
  617. src_reg = ipu_cm_read(ipu, link->src.reg);
  618. src_reg &= ~link->src.mask;
  619. src_reg |= link->src.val;
  620. ipu_cm_write(ipu, src_reg, link->src.reg);
  621. }
  622. if (link->sink.mask) {
  623. sink_reg = ipu_cm_read(ipu, link->sink.reg);
  624. sink_reg &= ~link->sink.mask;
  625. sink_reg |= link->sink.val;
  626. ipu_cm_write(ipu, sink_reg, link->sink.reg);
  627. }
  628. spin_unlock_irqrestore(&ipu->lock, flags);
  629. return 0;
  630. }
  631. EXPORT_SYMBOL_GPL(ipu_fsu_link);
  632. /*
  633. * Unlinks source and sink channels in the FSU.
  634. */
  635. int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
  636. {
  637. const struct fsu_link_info *link;
  638. u32 src_reg, sink_reg;
  639. unsigned long flags;
  640. link = find_fsu_link_info(src_ch, sink_ch);
  641. if (!link)
  642. return -EINVAL;
  643. spin_lock_irqsave(&ipu->lock, flags);
  644. if (link->src.mask) {
  645. src_reg = ipu_cm_read(ipu, link->src.reg);
  646. src_reg &= ~link->src.mask;
  647. ipu_cm_write(ipu, src_reg, link->src.reg);
  648. }
  649. if (link->sink.mask) {
  650. sink_reg = ipu_cm_read(ipu, link->sink.reg);
  651. sink_reg &= ~link->sink.mask;
  652. ipu_cm_write(ipu, sink_reg, link->sink.reg);
  653. }
  654. spin_unlock_irqrestore(&ipu->lock, flags);
  655. return 0;
  656. }
  657. EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
  658. /* Link IDMAC channels in the FSU */
  659. int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
  660. {
  661. return ipu_fsu_link(src->ipu, src->num, sink->num);
  662. }
  663. EXPORT_SYMBOL_GPL(ipu_idmac_link);
  664. /* Unlink IDMAC channels in the FSU */
  665. int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
  666. {
  667. return ipu_fsu_unlink(src->ipu, src->num, sink->num);
  668. }
  669. EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
  670. struct ipu_devtype {
  671. const char *name;
  672. unsigned long cm_ofs;
  673. unsigned long cpmem_ofs;
  674. unsigned long srm_ofs;
  675. unsigned long tpm_ofs;
  676. unsigned long csi0_ofs;
  677. unsigned long csi1_ofs;
  678. unsigned long ic_ofs;
  679. unsigned long disp0_ofs;
  680. unsigned long disp1_ofs;
  681. unsigned long dc_tmpl_ofs;
  682. unsigned long vdi_ofs;
  683. enum ipuv3_type type;
  684. };
  685. static struct ipu_devtype ipu_type_imx51 = {
  686. .name = "IPUv3EX",
  687. .cm_ofs = 0x1e000000,
  688. .cpmem_ofs = 0x1f000000,
  689. .srm_ofs = 0x1f040000,
  690. .tpm_ofs = 0x1f060000,
  691. .csi0_ofs = 0x1e030000,
  692. .csi1_ofs = 0x1e038000,
  693. .ic_ofs = 0x1e020000,
  694. .disp0_ofs = 0x1e040000,
  695. .disp1_ofs = 0x1e048000,
  696. .dc_tmpl_ofs = 0x1f080000,
  697. .vdi_ofs = 0x1e068000,
  698. .type = IPUV3EX,
  699. };
  700. static struct ipu_devtype ipu_type_imx53 = {
  701. .name = "IPUv3M",
  702. .cm_ofs = 0x06000000,
  703. .cpmem_ofs = 0x07000000,
  704. .srm_ofs = 0x07040000,
  705. .tpm_ofs = 0x07060000,
  706. .csi0_ofs = 0x06030000,
  707. .csi1_ofs = 0x06038000,
  708. .ic_ofs = 0x06020000,
  709. .disp0_ofs = 0x06040000,
  710. .disp1_ofs = 0x06048000,
  711. .dc_tmpl_ofs = 0x07080000,
  712. .vdi_ofs = 0x06068000,
  713. .type = IPUV3M,
  714. };
  715. static struct ipu_devtype ipu_type_imx6q = {
  716. .name = "IPUv3H",
  717. .cm_ofs = 0x00200000,
  718. .cpmem_ofs = 0x00300000,
  719. .srm_ofs = 0x00340000,
  720. .tpm_ofs = 0x00360000,
  721. .csi0_ofs = 0x00230000,
  722. .csi1_ofs = 0x00238000,
  723. .ic_ofs = 0x00220000,
  724. .disp0_ofs = 0x00240000,
  725. .disp1_ofs = 0x00248000,
  726. .dc_tmpl_ofs = 0x00380000,
  727. .vdi_ofs = 0x00268000,
  728. .type = IPUV3H,
  729. };
  730. static const struct of_device_id imx_ipu_dt_ids[] = {
  731. { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
  732. { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
  733. { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
  734. { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
  735. { /* sentinel */ }
  736. };
  737. MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
  738. static int ipu_submodules_init(struct ipu_soc *ipu,
  739. struct platform_device *pdev, unsigned long ipu_base,
  740. struct clk *ipu_clk)
  741. {
  742. char *unit;
  743. int ret;
  744. struct device *dev = &pdev->dev;
  745. const struct ipu_devtype *devtype = ipu->devtype;
  746. ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
  747. if (ret) {
  748. unit = "cpmem";
  749. goto err_cpmem;
  750. }
  751. ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
  752. IPU_CONF_CSI0_EN, ipu_clk);
  753. if (ret) {
  754. unit = "csi0";
  755. goto err_csi_0;
  756. }
  757. ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
  758. IPU_CONF_CSI1_EN, ipu_clk);
  759. if (ret) {
  760. unit = "csi1";
  761. goto err_csi_1;
  762. }
  763. ret = ipu_ic_init(ipu, dev,
  764. ipu_base + devtype->ic_ofs,
  765. ipu_base + devtype->tpm_ofs);
  766. if (ret) {
  767. unit = "ic";
  768. goto err_ic;
  769. }
  770. ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
  771. IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
  772. IPU_CONF_IC_INPUT);
  773. if (ret) {
  774. unit = "vdi";
  775. goto err_vdi;
  776. }
  777. ret = ipu_image_convert_init(ipu, dev);
  778. if (ret) {
  779. unit = "image_convert";
  780. goto err_image_convert;
  781. }
  782. ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
  783. IPU_CONF_DI0_EN, ipu_clk);
  784. if (ret) {
  785. unit = "di0";
  786. goto err_di_0;
  787. }
  788. ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
  789. IPU_CONF_DI1_EN, ipu_clk);
  790. if (ret) {
  791. unit = "di1";
  792. goto err_di_1;
  793. }
  794. ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
  795. IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
  796. if (ret) {
  797. unit = "dc_template";
  798. goto err_dc;
  799. }
  800. ret = ipu_dmfc_init(ipu, dev, ipu_base +
  801. devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
  802. if (ret) {
  803. unit = "dmfc";
  804. goto err_dmfc;
  805. }
  806. ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
  807. if (ret) {
  808. unit = "dp";
  809. goto err_dp;
  810. }
  811. ret = ipu_smfc_init(ipu, dev, ipu_base +
  812. devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
  813. if (ret) {
  814. unit = "smfc";
  815. goto err_smfc;
  816. }
  817. return 0;
  818. err_smfc:
  819. ipu_dp_exit(ipu);
  820. err_dp:
  821. ipu_dmfc_exit(ipu);
  822. err_dmfc:
  823. ipu_dc_exit(ipu);
  824. err_dc:
  825. ipu_di_exit(ipu, 1);
  826. err_di_1:
  827. ipu_di_exit(ipu, 0);
  828. err_di_0:
  829. ipu_image_convert_exit(ipu);
  830. err_image_convert:
  831. ipu_vdi_exit(ipu);
  832. err_vdi:
  833. ipu_ic_exit(ipu);
  834. err_ic:
  835. ipu_csi_exit(ipu, 1);
  836. err_csi_1:
  837. ipu_csi_exit(ipu, 0);
  838. err_csi_0:
  839. ipu_cpmem_exit(ipu);
  840. err_cpmem:
  841. dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
  842. return ret;
  843. }
  844. static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
  845. {
  846. unsigned long status;
  847. int i, bit;
  848. for (i = 0; i < num_regs; i++) {
  849. status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
  850. status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
  851. for_each_set_bit(bit, &status, 32)
  852. generic_handle_domain_irq(ipu->domain,
  853. regs[i] * 32 + bit);
  854. }
  855. }
  856. static void ipu_irq_handler(struct irq_desc *desc)
  857. {
  858. struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
  859. struct irq_chip *chip = irq_desc_get_chip(desc);
  860. static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
  861. chained_irq_enter(chip, desc);
  862. ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
  863. chained_irq_exit(chip, desc);
  864. }
  865. static void ipu_err_irq_handler(struct irq_desc *desc)
  866. {
  867. struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
  868. struct irq_chip *chip = irq_desc_get_chip(desc);
  869. static const int int_reg[] = { 4, 5, 8, 9};
  870. chained_irq_enter(chip, desc);
  871. ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
  872. chained_irq_exit(chip, desc);
  873. }
  874. int ipu_map_irq(struct ipu_soc *ipu, int irq)
  875. {
  876. int virq;
  877. virq = irq_linear_revmap(ipu->domain, irq);
  878. if (!virq)
  879. virq = irq_create_mapping(ipu->domain, irq);
  880. return virq;
  881. }
  882. EXPORT_SYMBOL_GPL(ipu_map_irq);
  883. int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
  884. enum ipu_channel_irq irq_type)
  885. {
  886. return ipu_map_irq(ipu, irq_type + channel->num);
  887. }
  888. EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
  889. static void ipu_submodules_exit(struct ipu_soc *ipu)
  890. {
  891. ipu_smfc_exit(ipu);
  892. ipu_dp_exit(ipu);
  893. ipu_dmfc_exit(ipu);
  894. ipu_dc_exit(ipu);
  895. ipu_di_exit(ipu, 1);
  896. ipu_di_exit(ipu, 0);
  897. ipu_image_convert_exit(ipu);
  898. ipu_vdi_exit(ipu);
  899. ipu_ic_exit(ipu);
  900. ipu_csi_exit(ipu, 1);
  901. ipu_csi_exit(ipu, 0);
  902. ipu_cpmem_exit(ipu);
  903. }
  904. static int platform_remove_devices_fn(struct device *dev, void *unused)
  905. {
  906. struct platform_device *pdev = to_platform_device(dev);
  907. platform_device_unregister(pdev);
  908. return 0;
  909. }
  910. static void platform_device_unregister_children(struct platform_device *pdev)
  911. {
  912. device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
  913. }
  914. struct ipu_platform_reg {
  915. struct ipu_client_platformdata pdata;
  916. const char *name;
  917. };
  918. /* These must be in the order of the corresponding device tree port nodes */
  919. static struct ipu_platform_reg client_reg[] = {
  920. {
  921. .pdata = {
  922. .csi = 0,
  923. .dma[0] = IPUV3_CHANNEL_CSI0,
  924. .dma[1] = -EINVAL,
  925. },
  926. .name = "imx-ipuv3-csi",
  927. }, {
  928. .pdata = {
  929. .csi = 1,
  930. .dma[0] = IPUV3_CHANNEL_CSI1,
  931. .dma[1] = -EINVAL,
  932. },
  933. .name = "imx-ipuv3-csi",
  934. }, {
  935. .pdata = {
  936. .di = 0,
  937. .dc = 5,
  938. .dp = IPU_DP_FLOW_SYNC_BG,
  939. .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
  940. .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
  941. },
  942. .name = "imx-ipuv3-crtc",
  943. }, {
  944. .pdata = {
  945. .di = 1,
  946. .dc = 1,
  947. .dp = -EINVAL,
  948. .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
  949. .dma[1] = -EINVAL,
  950. },
  951. .name = "imx-ipuv3-crtc",
  952. },
  953. };
  954. static DEFINE_MUTEX(ipu_client_id_mutex);
  955. static int ipu_client_id;
  956. static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
  957. {
  958. struct device *dev = ipu->dev;
  959. unsigned i;
  960. int id, ret;
  961. mutex_lock(&ipu_client_id_mutex);
  962. id = ipu_client_id;
  963. ipu_client_id += ARRAY_SIZE(client_reg);
  964. mutex_unlock(&ipu_client_id_mutex);
  965. for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
  966. struct ipu_platform_reg *reg = &client_reg[i];
  967. struct platform_device *pdev;
  968. struct device_node *of_node;
  969. /* Associate subdevice with the corresponding port node */
  970. of_node = of_graph_get_port_by_id(dev->of_node, i);
  971. if (!of_node) {
  972. dev_info(dev,
  973. "no port@%d node in %pOF, not using %s%d\n",
  974. i, dev->of_node,
  975. (i / 2) ? "DI" : "CSI", i % 2);
  976. continue;
  977. }
  978. pdev = platform_device_alloc(reg->name, id++);
  979. if (!pdev) {
  980. ret = -ENOMEM;
  981. of_node_put(of_node);
  982. goto err_register;
  983. }
  984. pdev->dev.parent = dev;
  985. reg->pdata.of_node = of_node;
  986. ret = platform_device_add_data(pdev, &reg->pdata,
  987. sizeof(reg->pdata));
  988. if (!ret)
  989. ret = platform_device_add(pdev);
  990. if (ret) {
  991. platform_device_put(pdev);
  992. goto err_register;
  993. }
  994. }
  995. return 0;
  996. err_register:
  997. platform_device_unregister_children(to_platform_device(dev));
  998. return ret;
  999. }
  1000. static int ipu_irq_init(struct ipu_soc *ipu)
  1001. {
  1002. struct irq_chip_generic *gc;
  1003. struct irq_chip_type *ct;
  1004. unsigned long unused[IPU_NUM_IRQS / 32] = {
  1005. 0x400100d0, 0xffe000fd,
  1006. 0x400100d0, 0xffe000fd,
  1007. 0x400100d0, 0xffe000fd,
  1008. 0x4077ffff, 0xffe7e1fd,
  1009. 0x23fffffe, 0x8880fff0,
  1010. 0xf98fe7d0, 0xfff81fff,
  1011. 0x400100d0, 0xffe000fd,
  1012. 0x00000000,
  1013. };
  1014. int ret, i;
  1015. ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
  1016. &irq_generic_chip_ops, ipu);
  1017. if (!ipu->domain) {
  1018. dev_err(ipu->dev, "failed to add irq domain\n");
  1019. return -ENODEV;
  1020. }
  1021. ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
  1022. handle_level_irq, 0, 0, 0);
  1023. if (ret < 0) {
  1024. dev_err(ipu->dev, "failed to alloc generic irq chips\n");
  1025. irq_domain_remove(ipu->domain);
  1026. return ret;
  1027. }
  1028. /* Mask and clear all interrupts */
  1029. for (i = 0; i < IPU_NUM_IRQS; i += 32) {
  1030. ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
  1031. ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
  1032. }
  1033. for (i = 0; i < IPU_NUM_IRQS; i += 32) {
  1034. gc = irq_get_domain_generic_chip(ipu->domain, i);
  1035. gc->reg_base = ipu->cm_reg;
  1036. gc->unused = unused[i / 32];
  1037. ct = gc->chip_types;
  1038. ct->chip.irq_ack = irq_gc_ack_set_bit;
  1039. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  1040. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  1041. ct->regs.ack = IPU_INT_STAT(i / 32);
  1042. ct->regs.mask = IPU_INT_CTRL(i / 32);
  1043. }
  1044. irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
  1045. irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
  1046. ipu);
  1047. return 0;
  1048. }
  1049. static void ipu_irq_exit(struct ipu_soc *ipu)
  1050. {
  1051. int i, irq;
  1052. irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
  1053. irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
  1054. /* TODO: remove irq_domain_generic_chips */
  1055. for (i = 0; i < IPU_NUM_IRQS; i++) {
  1056. irq = irq_linear_revmap(ipu->domain, i);
  1057. if (irq)
  1058. irq_dispose_mapping(irq);
  1059. }
  1060. irq_domain_remove(ipu->domain);
  1061. }
  1062. void ipu_dump(struct ipu_soc *ipu)
  1063. {
  1064. int i;
  1065. dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
  1066. ipu_cm_read(ipu, IPU_CONF));
  1067. dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
  1068. ipu_idmac_read(ipu, IDMAC_CONF));
  1069. dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
  1070. ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
  1071. dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
  1072. ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
  1073. dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
  1074. ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
  1075. dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
  1076. ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
  1077. dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
  1078. ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
  1079. dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
  1080. ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
  1081. dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
  1082. ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
  1083. dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
  1084. ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
  1085. dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
  1086. ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
  1087. dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
  1088. ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
  1089. dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
  1090. ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
  1091. dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
  1092. ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
  1093. for (i = 0; i < 15; i++)
  1094. dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
  1095. ipu_cm_read(ipu, IPU_INT_CTRL(i)));
  1096. }
  1097. EXPORT_SYMBOL_GPL(ipu_dump);
  1098. static int ipu_probe(struct platform_device *pdev)
  1099. {
  1100. struct device_node *np = pdev->dev.of_node;
  1101. struct ipu_soc *ipu;
  1102. struct resource *res;
  1103. unsigned long ipu_base;
  1104. int ret, irq_sync, irq_err;
  1105. const struct ipu_devtype *devtype;
  1106. devtype = of_device_get_match_data(&pdev->dev);
  1107. if (!devtype)
  1108. return -EINVAL;
  1109. irq_sync = platform_get_irq(pdev, 0);
  1110. irq_err = platform_get_irq(pdev, 1);
  1111. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1112. dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
  1113. irq_sync, irq_err);
  1114. if (!res || irq_sync < 0 || irq_err < 0)
  1115. return -ENODEV;
  1116. ipu_base = res->start;
  1117. ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
  1118. if (!ipu)
  1119. return -ENODEV;
  1120. ipu->id = of_alias_get_id(np, "ipu");
  1121. if (ipu->id < 0)
  1122. ipu->id = 0;
  1123. if (of_device_is_compatible(np, "fsl,imx6qp-ipu") &&
  1124. IS_ENABLED(CONFIG_DRM)) {
  1125. ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev,
  1126. "fsl,prg", ipu->id);
  1127. if (!ipu->prg_priv)
  1128. return -EPROBE_DEFER;
  1129. }
  1130. ipu->devtype = devtype;
  1131. ipu->ipu_type = devtype->type;
  1132. spin_lock_init(&ipu->lock);
  1133. mutex_init(&ipu->channel_lock);
  1134. INIT_LIST_HEAD(&ipu->channels);
  1135. dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
  1136. ipu_base + devtype->cm_ofs);
  1137. dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
  1138. ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
  1139. dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
  1140. ipu_base + devtype->cpmem_ofs);
  1141. dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
  1142. ipu_base + devtype->csi0_ofs);
  1143. dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
  1144. ipu_base + devtype->csi1_ofs);
  1145. dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
  1146. ipu_base + devtype->ic_ofs);
  1147. dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
  1148. ipu_base + devtype->disp0_ofs);
  1149. dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
  1150. ipu_base + devtype->disp1_ofs);
  1151. dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
  1152. ipu_base + devtype->srm_ofs);
  1153. dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
  1154. ipu_base + devtype->tpm_ofs);
  1155. dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
  1156. ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
  1157. dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
  1158. ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
  1159. dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
  1160. ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
  1161. dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
  1162. ipu_base + devtype->vdi_ofs);
  1163. ipu->cm_reg = devm_ioremap(&pdev->dev,
  1164. ipu_base + devtype->cm_ofs, PAGE_SIZE);
  1165. ipu->idmac_reg = devm_ioremap(&pdev->dev,
  1166. ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
  1167. PAGE_SIZE);
  1168. if (!ipu->cm_reg || !ipu->idmac_reg)
  1169. return -ENOMEM;
  1170. ipu->clk = devm_clk_get(&pdev->dev, "bus");
  1171. if (IS_ERR(ipu->clk)) {
  1172. ret = PTR_ERR(ipu->clk);
  1173. dev_err(&pdev->dev, "clk_get failed with %d", ret);
  1174. return ret;
  1175. }
  1176. platform_set_drvdata(pdev, ipu);
  1177. ret = clk_prepare_enable(ipu->clk);
  1178. if (ret) {
  1179. dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
  1180. return ret;
  1181. }
  1182. ipu->dev = &pdev->dev;
  1183. ipu->irq_sync = irq_sync;
  1184. ipu->irq_err = irq_err;
  1185. ret = device_reset(&pdev->dev);
  1186. if (ret) {
  1187. dev_err(&pdev->dev, "failed to reset: %d\n", ret);
  1188. goto out_failed_reset;
  1189. }
  1190. ret = ipu_memory_reset(ipu);
  1191. if (ret)
  1192. goto out_failed_reset;
  1193. ret = ipu_irq_init(ipu);
  1194. if (ret)
  1195. goto out_failed_irq;
  1196. /* Set MCU_T to divide MCU access window into 2 */
  1197. ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
  1198. IPU_DISP_GEN);
  1199. ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
  1200. if (ret)
  1201. goto failed_submodules_init;
  1202. ret = ipu_add_client_devices(ipu, ipu_base);
  1203. if (ret) {
  1204. dev_err(&pdev->dev, "adding client devices failed with %d\n",
  1205. ret);
  1206. goto failed_add_clients;
  1207. }
  1208. dev_info(&pdev->dev, "%s probed\n", devtype->name);
  1209. return 0;
  1210. failed_add_clients:
  1211. ipu_submodules_exit(ipu);
  1212. failed_submodules_init:
  1213. ipu_irq_exit(ipu);
  1214. out_failed_irq:
  1215. out_failed_reset:
  1216. clk_disable_unprepare(ipu->clk);
  1217. return ret;
  1218. }
  1219. static int ipu_remove(struct platform_device *pdev)
  1220. {
  1221. struct ipu_soc *ipu = platform_get_drvdata(pdev);
  1222. platform_device_unregister_children(pdev);
  1223. ipu_submodules_exit(ipu);
  1224. ipu_irq_exit(ipu);
  1225. clk_disable_unprepare(ipu->clk);
  1226. return 0;
  1227. }
  1228. static struct platform_driver imx_ipu_driver = {
  1229. .driver = {
  1230. .name = "imx-ipuv3",
  1231. .of_match_table = imx_ipu_dt_ids,
  1232. },
  1233. .probe = ipu_probe,
  1234. .remove = ipu_remove,
  1235. };
  1236. static struct platform_driver * const drivers[] = {
  1237. #if IS_ENABLED(CONFIG_DRM)
  1238. &ipu_pre_drv,
  1239. &ipu_prg_drv,
  1240. #endif
  1241. &imx_ipu_driver,
  1242. };
  1243. static int __init imx_ipu_init(void)
  1244. {
  1245. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  1246. }
  1247. module_init(imx_ipu_init);
  1248. static void __exit imx_ipu_exit(void)
  1249. {
  1250. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  1251. }
  1252. module_exit(imx_ipu_exit);
  1253. MODULE_ALIAS("platform:imx-ipuv3");
  1254. MODULE_DESCRIPTION("i.MX IPU v3 driver");
  1255. MODULE_AUTHOR("Sascha Hauer <[email protected]>");
  1256. MODULE_LICENSE("GPL");