dev.h 9.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2012-2015, NVIDIA Corporation.
  4. */
  5. #ifndef HOST1X_DEV_H
  6. #define HOST1X_DEV_H
  7. #include <linux/device.h>
  8. #include <linux/iommu.h>
  9. #include <linux/iova.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/reset.h>
  12. #include "cdma.h"
  13. #include "channel.h"
  14. #include "context.h"
  15. #include "intr.h"
  16. #include "job.h"
  17. #include "syncpt.h"
  18. struct host1x_syncpt;
  19. struct host1x_syncpt_base;
  20. struct host1x_channel;
  21. struct host1x_cdma;
  22. struct host1x_job;
  23. struct push_buffer;
  24. struct output;
  25. struct dentry;
  26. struct host1x_channel_ops {
  27. int (*init)(struct host1x_channel *channel, struct host1x *host,
  28. unsigned int id);
  29. int (*submit)(struct host1x_job *job);
  30. };
  31. struct host1x_cdma_ops {
  32. void (*start)(struct host1x_cdma *cdma);
  33. void (*stop)(struct host1x_cdma *cdma);
  34. void (*flush)(struct host1x_cdma *cdma);
  35. int (*timeout_init)(struct host1x_cdma *cdma);
  36. void (*timeout_destroy)(struct host1x_cdma *cdma);
  37. void (*freeze)(struct host1x_cdma *cdma);
  38. void (*resume)(struct host1x_cdma *cdma, u32 getptr);
  39. void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr,
  40. u32 syncpt_incrs, u32 syncval, u32 nr_slots);
  41. };
  42. struct host1x_pushbuffer_ops {
  43. void (*init)(struct push_buffer *pb);
  44. };
  45. struct host1x_debug_ops {
  46. void (*debug_init)(struct dentry *de);
  47. void (*show_channel_cdma)(struct host1x *host,
  48. struct host1x_channel *ch,
  49. struct output *o);
  50. void (*show_channel_fifo)(struct host1x *host,
  51. struct host1x_channel *ch,
  52. struct output *o);
  53. void (*show_mlocks)(struct host1x *host, struct output *output);
  54. };
  55. struct host1x_syncpt_ops {
  56. void (*restore)(struct host1x_syncpt *syncpt);
  57. void (*restore_wait_base)(struct host1x_syncpt *syncpt);
  58. void (*load_wait_base)(struct host1x_syncpt *syncpt);
  59. u32 (*load)(struct host1x_syncpt *syncpt);
  60. int (*cpu_incr)(struct host1x_syncpt *syncpt);
  61. void (*assign_to_channel)(struct host1x_syncpt *syncpt,
  62. struct host1x_channel *channel);
  63. void (*enable_protection)(struct host1x *host);
  64. };
  65. struct host1x_intr_ops {
  66. int (*init_host_sync)(struct host1x *host, u32 cpm,
  67. void (*syncpt_thresh_work)(struct work_struct *work));
  68. void (*set_syncpt_threshold)(
  69. struct host1x *host, unsigned int id, u32 thresh);
  70. void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
  71. void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
  72. void (*disable_all_syncpt_intrs)(struct host1x *host);
  73. int (*free_syncpt_irq)(struct host1x *host);
  74. };
  75. struct host1x_sid_entry {
  76. unsigned int base;
  77. unsigned int offset;
  78. unsigned int limit;
  79. };
  80. struct host1x_table_desc {
  81. unsigned int base;
  82. unsigned int count;
  83. };
  84. struct host1x_info {
  85. unsigned int nb_channels; /* host1x: number of channels supported */
  86. unsigned int nb_pts; /* host1x: number of syncpoints supported */
  87. unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
  88. unsigned int nb_mlocks; /* host1x: number of mlocks supported */
  89. int (*init)(struct host1x *host1x); /* initialize per SoC ops */
  90. unsigned int sync_offset; /* offset of syncpoint registers */
  91. u64 dma_mask; /* mask of addressable memory */
  92. bool has_wide_gather; /* supports GATHER_W opcode */
  93. bool has_hypervisor; /* has hypervisor registers */
  94. bool has_common; /* has common registers separate from hypervisor */
  95. unsigned int num_sid_entries;
  96. const struct host1x_sid_entry *sid_table;
  97. struct host1x_table_desc streamid_vm_table;
  98. struct host1x_table_desc classid_vm_table;
  99. struct host1x_table_desc mmio_vm_table;
  100. /*
  101. * On T20-T148, the boot chain may setup DC to increment syncpoints
  102. * 26/27 on VBLANK. As such we cannot use these syncpoints until
  103. * the display driver disables VBLANK increments.
  104. */
  105. bool reserve_vblank_syncpts;
  106. };
  107. struct host1x {
  108. const struct host1x_info *info;
  109. void __iomem *regs;
  110. void __iomem *hv_regs; /* hypervisor region */
  111. void __iomem *common_regs;
  112. struct host1x_syncpt *syncpt;
  113. struct host1x_syncpt_base *bases;
  114. struct device *dev;
  115. struct clk *clk;
  116. struct reset_control_bulk_data resets[2];
  117. unsigned int nresets;
  118. struct iommu_group *group;
  119. struct iommu_domain *domain;
  120. struct iova_domain iova;
  121. dma_addr_t iova_end;
  122. struct mutex intr_mutex;
  123. int intr_syncpt_irq;
  124. const struct host1x_syncpt_ops *syncpt_op;
  125. const struct host1x_intr_ops *intr_op;
  126. const struct host1x_channel_ops *channel_op;
  127. const struct host1x_cdma_ops *cdma_op;
  128. const struct host1x_pushbuffer_ops *cdma_pb_op;
  129. const struct host1x_debug_ops *debug_op;
  130. struct host1x_syncpt *nop_sp;
  131. struct mutex syncpt_mutex;
  132. struct host1x_channel_list channel_list;
  133. struct host1x_memory_context_list context_list;
  134. struct dentry *debugfs;
  135. struct mutex devices_lock;
  136. struct list_head devices;
  137. struct list_head list;
  138. struct device_dma_parameters dma_parms;
  139. struct host1x_bo_cache cache;
  140. };
  141. void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
  142. void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
  143. u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
  144. void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
  145. u32 host1x_sync_readl(struct host1x *host1x, u32 r);
  146. void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v);
  147. u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);
  148. static inline void host1x_hw_syncpt_restore(struct host1x *host,
  149. struct host1x_syncpt *sp)
  150. {
  151. host->syncpt_op->restore(sp);
  152. }
  153. static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host,
  154. struct host1x_syncpt *sp)
  155. {
  156. host->syncpt_op->restore_wait_base(sp);
  157. }
  158. static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host,
  159. struct host1x_syncpt *sp)
  160. {
  161. host->syncpt_op->load_wait_base(sp);
  162. }
  163. static inline u32 host1x_hw_syncpt_load(struct host1x *host,
  164. struct host1x_syncpt *sp)
  165. {
  166. return host->syncpt_op->load(sp);
  167. }
  168. static inline int host1x_hw_syncpt_cpu_incr(struct host1x *host,
  169. struct host1x_syncpt *sp)
  170. {
  171. return host->syncpt_op->cpu_incr(sp);
  172. }
  173. static inline void host1x_hw_syncpt_assign_to_channel(
  174. struct host1x *host, struct host1x_syncpt *sp,
  175. struct host1x_channel *ch)
  176. {
  177. return host->syncpt_op->assign_to_channel(sp, ch);
  178. }
  179. static inline void host1x_hw_syncpt_enable_protection(struct host1x *host)
  180. {
  181. return host->syncpt_op->enable_protection(host);
  182. }
  183. static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm,
  184. void (*syncpt_thresh_work)(struct work_struct *))
  185. {
  186. return host->intr_op->init_host_sync(host, cpm, syncpt_thresh_work);
  187. }
  188. static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host,
  189. unsigned int id,
  190. u32 thresh)
  191. {
  192. host->intr_op->set_syncpt_threshold(host, id, thresh);
  193. }
  194. static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host,
  195. unsigned int id)
  196. {
  197. host->intr_op->enable_syncpt_intr(host, id);
  198. }
  199. static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host,
  200. unsigned int id)
  201. {
  202. host->intr_op->disable_syncpt_intr(host, id);
  203. }
  204. static inline void host1x_hw_intr_disable_all_syncpt_intrs(struct host1x *host)
  205. {
  206. host->intr_op->disable_all_syncpt_intrs(host);
  207. }
  208. static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host)
  209. {
  210. return host->intr_op->free_syncpt_irq(host);
  211. }
  212. static inline int host1x_hw_channel_init(struct host1x *host,
  213. struct host1x_channel *channel,
  214. unsigned int id)
  215. {
  216. return host->channel_op->init(channel, host, id);
  217. }
  218. static inline int host1x_hw_channel_submit(struct host1x *host,
  219. struct host1x_job *job)
  220. {
  221. return host->channel_op->submit(job);
  222. }
  223. static inline void host1x_hw_cdma_start(struct host1x *host,
  224. struct host1x_cdma *cdma)
  225. {
  226. host->cdma_op->start(cdma);
  227. }
  228. static inline void host1x_hw_cdma_stop(struct host1x *host,
  229. struct host1x_cdma *cdma)
  230. {
  231. host->cdma_op->stop(cdma);
  232. }
  233. static inline void host1x_hw_cdma_flush(struct host1x *host,
  234. struct host1x_cdma *cdma)
  235. {
  236. host->cdma_op->flush(cdma);
  237. }
  238. static inline int host1x_hw_cdma_timeout_init(struct host1x *host,
  239. struct host1x_cdma *cdma)
  240. {
  241. return host->cdma_op->timeout_init(cdma);
  242. }
  243. static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host,
  244. struct host1x_cdma *cdma)
  245. {
  246. host->cdma_op->timeout_destroy(cdma);
  247. }
  248. static inline void host1x_hw_cdma_freeze(struct host1x *host,
  249. struct host1x_cdma *cdma)
  250. {
  251. host->cdma_op->freeze(cdma);
  252. }
  253. static inline void host1x_hw_cdma_resume(struct host1x *host,
  254. struct host1x_cdma *cdma, u32 getptr)
  255. {
  256. host->cdma_op->resume(cdma, getptr);
  257. }
  258. static inline void host1x_hw_cdma_timeout_cpu_incr(struct host1x *host,
  259. struct host1x_cdma *cdma,
  260. u32 getptr,
  261. u32 syncpt_incrs,
  262. u32 syncval, u32 nr_slots)
  263. {
  264. host->cdma_op->timeout_cpu_incr(cdma, getptr, syncpt_incrs, syncval,
  265. nr_slots);
  266. }
  267. static inline void host1x_hw_pushbuffer_init(struct host1x *host,
  268. struct push_buffer *pb)
  269. {
  270. host->cdma_pb_op->init(pb);
  271. }
  272. static inline void host1x_hw_debug_init(struct host1x *host, struct dentry *de)
  273. {
  274. if (host->debug_op && host->debug_op->debug_init)
  275. host->debug_op->debug_init(de);
  276. }
  277. static inline void host1x_hw_show_channel_cdma(struct host1x *host,
  278. struct host1x_channel *channel,
  279. struct output *o)
  280. {
  281. host->debug_op->show_channel_cdma(host, channel, o);
  282. }
  283. static inline void host1x_hw_show_channel_fifo(struct host1x *host,
  284. struct host1x_channel *channel,
  285. struct output *o)
  286. {
  287. host->debug_op->show_channel_fifo(host, channel, o);
  288. }
  289. static inline void host1x_hw_show_mlocks(struct host1x *host, struct output *o)
  290. {
  291. host->debug_op->show_mlocks(host, o);
  292. }
  293. extern struct platform_driver tegra_mipi_driver;
  294. #endif