Kconfig 8.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. #
  3. # FPGA framework configuration
  4. #
  5. menuconfig FPGA
  6. tristate "FPGA Configuration Framework"
  7. help
  8. Say Y here if you want support for configuring FPGAs from the
  9. kernel. The FPGA framework adds an FPGA manager class and FPGA
  10. manager drivers.
  11. if FPGA
  12. config FPGA_MGR_SOCFPGA
  13. tristate "Altera SOCFPGA FPGA Manager"
  14. depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
  15. help
  16. FPGA manager driver support for Altera SOCFPGA.
  17. config FPGA_MGR_SOCFPGA_A10
  18. tristate "Altera SoCFPGA Arria10"
  19. depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
  20. select REGMAP_MMIO
  21. help
  22. FPGA manager driver support for Altera Arria10 SoCFPGA.
  23. config ALTERA_PR_IP_CORE
  24. tristate "Altera Partial Reconfiguration IP Core"
  25. help
  26. Core driver support for Altera Partial Reconfiguration IP component
  27. config ALTERA_PR_IP_CORE_PLAT
  28. tristate "Platform support of Altera Partial Reconfiguration IP Core"
  29. depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
  30. help
  31. Platform driver support for Altera Partial Reconfiguration IP
  32. component
  33. config FPGA_MGR_ALTERA_PS_SPI
  34. tristate "Altera FPGA Passive Serial over SPI"
  35. depends on SPI
  36. select BITREVERSE
  37. help
  38. FPGA manager driver support for Altera Arria/Cyclone/Stratix
  39. using the passive serial interface over SPI.
  40. config FPGA_MGR_ALTERA_CVP
  41. tristate "Altera CvP FPGA Manager"
  42. depends on PCI
  43. help
  44. FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
  45. Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
  46. config FPGA_MGR_ZYNQ_FPGA
  47. tristate "Xilinx Zynq FPGA"
  48. depends on ARCH_ZYNQ || COMPILE_TEST
  49. help
  50. FPGA manager driver support for Xilinx Zynq FPGAs.
  51. config FPGA_MGR_STRATIX10_SOC
  52. tristate "Intel Stratix10 SoC FPGA Manager"
  53. depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
  54. help
  55. FPGA manager driver support for the Intel Stratix10 SoC.
  56. config FPGA_MGR_XILINX_SPI
  57. tristate "Xilinx Configuration over Slave Serial (SPI)"
  58. depends on SPI
  59. help
  60. FPGA manager driver support for Xilinx FPGA configuration
  61. over slave serial interface.
  62. config FPGA_MGR_ICE40_SPI
  63. tristate "Lattice iCE40 SPI"
  64. depends on OF && SPI
  65. help
  66. FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
  67. config FPGA_MGR_MACHXO2_SPI
  68. tristate "Lattice MachXO2 SPI"
  69. depends on SPI
  70. help
  71. FPGA manager driver support for Lattice MachXO2 configuration
  72. over slave SPI interface.
  73. config FPGA_MGR_TS73XX
  74. tristate "Technologic Systems TS-73xx SBC FPGA Manager"
  75. depends on ARCH_EP93XX && MACH_TS72XX
  76. help
  77. FPGA manager driver support for the Altera Cyclone II FPGA
  78. present on the TS-73xx SBC boards.
  79. config FPGA_BRIDGE
  80. tristate "FPGA Bridge Framework"
  81. help
  82. Say Y here if you want to support bridges connected between host
  83. processors and FPGAs or between FPGAs.
  84. config SOCFPGA_FPGA_BRIDGE
  85. tristate "Altera SoCFPGA FPGA Bridges"
  86. depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
  87. help
  88. Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
  89. devices.
  90. config ALTERA_FREEZE_BRIDGE
  91. tristate "Altera FPGA Freeze Bridge"
  92. depends on FPGA_BRIDGE && HAS_IOMEM
  93. help
  94. Say Y to enable drivers for Altera FPGA Freeze bridges. A
  95. freeze bridge is a bridge that exists in the FPGA fabric to
  96. isolate one region of the FPGA from the busses while that
  97. region is being reprogrammed.
  98. config XILINX_PR_DECOUPLER
  99. tristate "Xilinx LogiCORE PR Decoupler"
  100. depends on FPGA_BRIDGE
  101. depends on HAS_IOMEM
  102. help
  103. Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
  104. or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
  105. The PR Decoupler exists in the FPGA fabric to isolate one
  106. region of the FPGA from the busses while that region is
  107. being reprogrammed during partial reconfig.
  108. The Dynamic Function eXchange AXI shutdown manager prevents
  109. AXI traffic from passing through the bridge. The controller
  110. safely handles AXI4MM and AXI4-Lite interfaces on a
  111. Reconfigurable Partition when it is undergoing dynamic
  112. reconfiguration, preventing the system deadlock that can
  113. occur if AXI transactions are interrupted by DFX.
  114. config FPGA_REGION
  115. tristate "FPGA Region"
  116. depends on FPGA_BRIDGE
  117. help
  118. FPGA Region common code. An FPGA Region controls an FPGA Manager
  119. and the FPGA Bridges associated with either a reconfigurable
  120. region of an FPGA or a whole FPGA.
  121. config OF_FPGA_REGION
  122. tristate "FPGA Region Device Tree Overlay Support"
  123. depends on OF && FPGA_REGION
  124. help
  125. Support for loading FPGA images by applying a Device Tree
  126. overlay.
  127. config FPGA_DFL
  128. tristate "FPGA Device Feature List (DFL) support"
  129. select FPGA_BRIDGE
  130. select FPGA_REGION
  131. depends on HAS_IOMEM
  132. help
  133. Device Feature List (DFL) defines a feature list structure that
  134. creates a linked list of feature headers within the MMIO space
  135. to provide an extensible way of adding features for FPGA.
  136. Driver can walk through the feature headers to enumerate feature
  137. devices (e.g. FPGA Management Engine, Port and Accelerator
  138. Function Unit) and their private features for target FPGA devices.
  139. Select this option to enable common support for Field-Programmable
  140. Gate Array (FPGA) solutions which implement Device Feature List.
  141. It provides enumeration APIs and feature device infrastructure.
  142. config FPGA_DFL_FME
  143. tristate "FPGA DFL FME Driver"
  144. depends on FPGA_DFL && HWMON && PERF_EVENTS
  145. help
  146. The FPGA Management Engine (FME) is a feature device implemented
  147. under Device Feature List (DFL) framework. Select this option to
  148. enable the platform device driver for FME which implements all
  149. FPGA platform level management features. There shall be one FME
  150. per DFL based FPGA device.
  151. config FPGA_DFL_FME_MGR
  152. tristate "FPGA DFL FME Manager Driver"
  153. depends on FPGA_DFL_FME && HAS_IOMEM
  154. help
  155. Say Y to enable FPGA Manager driver for FPGA Management Engine.
  156. config FPGA_DFL_FME_BRIDGE
  157. tristate "FPGA DFL FME Bridge Driver"
  158. depends on FPGA_DFL_FME && HAS_IOMEM
  159. help
  160. Say Y to enable FPGA Bridge driver for FPGA Management Engine.
  161. config FPGA_DFL_FME_REGION
  162. tristate "FPGA DFL FME Region Driver"
  163. depends on FPGA_DFL_FME && HAS_IOMEM
  164. help
  165. Say Y to enable FPGA Region driver for FPGA Management Engine.
  166. config FPGA_DFL_AFU
  167. tristate "FPGA DFL AFU Driver"
  168. depends on FPGA_DFL
  169. help
  170. This is the driver for FPGA Accelerated Function Unit (AFU) which
  171. implements AFU and Port management features. A User AFU connects
  172. to the FPGA infrastructure via a Port. There may be more than one
  173. Port/AFU per DFL based FPGA device.
  174. config FPGA_DFL_NIOS_INTEL_PAC_N3000
  175. tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
  176. depends on FPGA_DFL
  177. select REGMAP
  178. help
  179. This is the driver for the N3000 Nios private feature on Intel
  180. PAC (Programmable Acceleration Card) N3000. It communicates
  181. with the embedded Nios processor to configure the retimers on
  182. the card. It also instantiates the SPI master (spi-altera) for
  183. the card's BMC (Board Management Controller).
  184. config FPGA_DFL_PCI
  185. tristate "FPGA DFL PCIe Device Driver"
  186. depends on PCI && FPGA_DFL
  187. help
  188. Select this option to enable PCIe driver for PCIe-based
  189. Field-Programmable Gate Array (FPGA) solutions which implement
  190. the Device Feature List (DFL). This driver provides interfaces
  191. for userspace applications to configure, enumerate, open and access
  192. FPGA accelerators on the FPGA DFL devices, enables system level
  193. management functions such as FPGA partial reconfiguration, power
  194. management and virtualization with DFL framework and DFL feature
  195. device drivers.
  196. To compile this as a module, choose M here.
  197. config FPGA_MGR_ZYNQMP_FPGA
  198. tristate "Xilinx ZynqMP FPGA"
  199. depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
  200. help
  201. FPGA manager driver support for Xilinx ZynqMP FPGAs.
  202. This driver uses the processor configuration port(PCAP)
  203. to configure the programmable logic(PL) through PS
  204. on ZynqMP SoC.
  205. config FPGA_MGR_VERSAL_FPGA
  206. tristate "Xilinx Versal FPGA"
  207. depends on ARCH_ZYNQMP || COMPILE_TEST
  208. help
  209. Select this option to enable FPGA manager driver support for
  210. Xilinx Versal SoC. This driver uses the firmware interface to
  211. configure the programmable logic(PL).
  212. To compile this as a module, choose M here.
  213. config FPGA_M10_BMC_SEC_UPDATE
  214. tristate "Intel MAX10 BMC Secure Update driver"
  215. depends on MFD_INTEL_M10_BMC
  216. select FW_LOADER
  217. select FW_UPLOAD
  218. help
  219. Secure update support for the Intel MAX10 board management
  220. controller.
  221. This is a subdriver of the Intel MAX10 board management controller
  222. (BMC) and provides support for secure updates for the BMC image,
  223. the FPGA image, the Root Entry Hashes, etc.
  224. config FPGA_MGR_MICROCHIP_SPI
  225. tristate "Microchip Polarfire SPI FPGA manager"
  226. depends on SPI
  227. help
  228. FPGA manager driver support for Microchip Polarfire FPGAs
  229. programming over slave SPI interface with .dat formatted
  230. bitstream image.
  231. endif # FPGA