k3-psil-am64.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
  4. * Author: Peter Ujfalusi <[email protected]>
  5. */
  6. #include <linux/kernel.h>
  7. #include "k3-psil-priv.h"
  8. #define PSIL_PDMA_XY_TR(x) \
  9. { \
  10. .thread_id = x, \
  11. .ep_config = { \
  12. .ep_type = PSIL_EP_PDMA_XY, \
  13. .mapped_channel_id = -1, \
  14. .default_flow_id = -1, \
  15. }, \
  16. }
  17. #define PSIL_PDMA_XY_PKT(x) \
  18. { \
  19. .thread_id = x, \
  20. .ep_config = { \
  21. .ep_type = PSIL_EP_PDMA_XY, \
  22. .mapped_channel_id = -1, \
  23. .default_flow_id = -1, \
  24. .pkt_mode = 1, \
  25. }, \
  26. }
  27. #define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
  28. { \
  29. .thread_id = x, \
  30. .ep_config = { \
  31. .ep_type = PSIL_EP_NATIVE, \
  32. .pkt_mode = 1, \
  33. .needs_epib = 1, \
  34. .psd_size = 16, \
  35. .mapped_channel_id = ch, \
  36. .flow_start = flow_base, \
  37. .flow_num = flow_cnt, \
  38. .default_flow_id = flow_base, \
  39. }, \
  40. }
  41. #define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
  42. { \
  43. .thread_id = x, \
  44. .ep_config = { \
  45. .ep_type = PSIL_EP_NATIVE, \
  46. .pkt_mode = 1, \
  47. .needs_epib = 1, \
  48. .psd_size = 64, \
  49. .mapped_channel_id = ch, \
  50. .flow_start = flow_base, \
  51. .flow_num = flow_cnt, \
  52. .default_flow_id = default_flow, \
  53. .notdpkt = tx, \
  54. }, \
  55. }
  56. /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
  57. static struct psil_ep am64_src_ep_map[] = {
  58. /* SAUL */
  59. PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
  60. PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
  61. PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
  62. PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
  63. /* ICSS_G0 */
  64. PSIL_ETHERNET(0x4100, 21, 48, 16),
  65. PSIL_ETHERNET(0x4101, 22, 64, 16),
  66. PSIL_ETHERNET(0x4102, 23, 80, 16),
  67. PSIL_ETHERNET(0x4103, 24, 96, 16),
  68. /* ICSS_G1 */
  69. PSIL_ETHERNET(0x4200, 25, 112, 16),
  70. PSIL_ETHERNET(0x4201, 26, 128, 16),
  71. PSIL_ETHERNET(0x4202, 27, 144, 16),
  72. PSIL_ETHERNET(0x4203, 28, 160, 16),
  73. /* PDMA_MAIN0 - SPI0-3 */
  74. PSIL_PDMA_XY_PKT(0x4300),
  75. PSIL_PDMA_XY_PKT(0x4301),
  76. PSIL_PDMA_XY_PKT(0x4302),
  77. PSIL_PDMA_XY_PKT(0x4303),
  78. PSIL_PDMA_XY_PKT(0x4304),
  79. PSIL_PDMA_XY_PKT(0x4305),
  80. PSIL_PDMA_XY_PKT(0x4306),
  81. PSIL_PDMA_XY_PKT(0x4307),
  82. PSIL_PDMA_XY_PKT(0x4308),
  83. PSIL_PDMA_XY_PKT(0x4309),
  84. PSIL_PDMA_XY_PKT(0x430a),
  85. PSIL_PDMA_XY_PKT(0x430b),
  86. PSIL_PDMA_XY_PKT(0x430c),
  87. PSIL_PDMA_XY_PKT(0x430d),
  88. PSIL_PDMA_XY_PKT(0x430e),
  89. PSIL_PDMA_XY_PKT(0x430f),
  90. /* PDMA_MAIN0 - USART0-1 */
  91. PSIL_PDMA_XY_PKT(0x4310),
  92. PSIL_PDMA_XY_PKT(0x4311),
  93. /* PDMA_MAIN1 - SPI4 */
  94. PSIL_PDMA_XY_PKT(0x4400),
  95. PSIL_PDMA_XY_PKT(0x4401),
  96. PSIL_PDMA_XY_PKT(0x4402),
  97. PSIL_PDMA_XY_PKT(0x4403),
  98. /* PDMA_MAIN1 - USART2-6 */
  99. PSIL_PDMA_XY_PKT(0x4404),
  100. PSIL_PDMA_XY_PKT(0x4405),
  101. PSIL_PDMA_XY_PKT(0x4406),
  102. PSIL_PDMA_XY_PKT(0x4407),
  103. PSIL_PDMA_XY_PKT(0x4408),
  104. /* PDMA_MAIN1 - ADCs */
  105. PSIL_PDMA_XY_TR(0x440f),
  106. PSIL_PDMA_XY_TR(0x4410),
  107. /* CPSW2 */
  108. PSIL_ETHERNET(0x4500, 16, 16, 16),
  109. };
  110. /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
  111. static struct psil_ep am64_dst_ep_map[] = {
  112. /* SAUL */
  113. PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
  114. PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
  115. /* ICSS_G0 */
  116. PSIL_ETHERNET(0xc100, 26, 96, 1),
  117. PSIL_ETHERNET(0xc101, 27, 97, 1),
  118. PSIL_ETHERNET(0xc102, 28, 98, 1),
  119. PSIL_ETHERNET(0xc103, 29, 99, 1),
  120. PSIL_ETHERNET(0xc104, 30, 100, 1),
  121. PSIL_ETHERNET(0xc105, 31, 101, 1),
  122. PSIL_ETHERNET(0xc106, 32, 102, 1),
  123. PSIL_ETHERNET(0xc107, 33, 103, 1),
  124. /* ICSS_G1 */
  125. PSIL_ETHERNET(0xc200, 34, 104, 1),
  126. PSIL_ETHERNET(0xc201, 35, 105, 1),
  127. PSIL_ETHERNET(0xc202, 36, 106, 1),
  128. PSIL_ETHERNET(0xc203, 37, 107, 1),
  129. PSIL_ETHERNET(0xc204, 38, 108, 1),
  130. PSIL_ETHERNET(0xc205, 39, 109, 1),
  131. PSIL_ETHERNET(0xc206, 40, 110, 1),
  132. PSIL_ETHERNET(0xc207, 41, 111, 1),
  133. /* CPSW2 */
  134. PSIL_ETHERNET(0xc500, 16, 16, 8),
  135. PSIL_ETHERNET(0xc501, 17, 24, 8),
  136. PSIL_ETHERNET(0xc502, 18, 32, 8),
  137. PSIL_ETHERNET(0xc503, 19, 40, 8),
  138. PSIL_ETHERNET(0xc504, 20, 48, 8),
  139. PSIL_ETHERNET(0xc505, 21, 56, 8),
  140. PSIL_ETHERNET(0xc506, 22, 64, 8),
  141. PSIL_ETHERNET(0xc507, 23, 72, 8),
  142. };
  143. struct psil_ep_map am64_ep_map = {
  144. .name = "am64",
  145. .src = am64_src_ep_map,
  146. .src_count = ARRAY_SIZE(am64_src_ep_map),
  147. .dst = am64_dst_ep_map,
  148. .dst_count = ARRAY_SIZE(am64_dst_ep_map),
  149. };