sf-pdma.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * SiFive FU540 Platform DMA driver
  4. * Copyright (C) 2019 SiFive
  5. *
  6. * Based partially on:
  7. * - drivers/dma/fsl-edma.c
  8. * - drivers/dma/dw-edma/
  9. * - drivers/dma/pxa-dma.c
  10. *
  11. * See the following sources for further documentation:
  12. * - Chapter 12 "Platform DMA Engine (PDMA)" of
  13. * SiFive FU540-C000 v1.0
  14. * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  15. */
  16. #ifndef _SF_PDMA_H
  17. #define _SF_PDMA_H
  18. #include <linux/dmaengine.h>
  19. #include <linux/dma-direction.h>
  20. #include "../dmaengine.h"
  21. #include "../virt-dma.h"
  22. #define PDMA_MAX_NR_CH 4
  23. #define PDMA_BASE_ADDR 0x3000000
  24. #define PDMA_CHAN_OFFSET 0x1000
  25. /* Register Offset */
  26. #define PDMA_CTRL 0x000
  27. #define PDMA_XFER_TYPE 0x004
  28. #define PDMA_XFER_SIZE 0x008
  29. #define PDMA_DST_ADDR 0x010
  30. #define PDMA_SRC_ADDR 0x018
  31. #define PDMA_ACT_TYPE 0x104 /* Read-only */
  32. #define PDMA_REMAINING_BYTE 0x108 /* Read-only */
  33. #define PDMA_CUR_DST_ADDR 0x110 /* Read-only*/
  34. #define PDMA_CUR_SRC_ADDR 0x118 /* Read-only*/
  35. /* CTRL */
  36. #define PDMA_CLEAR_CTRL 0x0
  37. #define PDMA_CLAIM_MASK GENMASK(0, 0)
  38. #define PDMA_RUN_MASK GENMASK(1, 1)
  39. #define PDMA_ENABLE_DONE_INT_MASK GENMASK(14, 14)
  40. #define PDMA_ENABLE_ERR_INT_MASK GENMASK(15, 15)
  41. #define PDMA_DONE_STATUS_MASK GENMASK(30, 30)
  42. #define PDMA_ERR_STATUS_MASK GENMASK(31, 31)
  43. /* Transfer Type */
  44. #define PDMA_FULL_SPEED 0xFF000008
  45. /* Error Recovery */
  46. #define MAX_RETRY 1
  47. #define SF_PDMA_REG_BASE(ch) (pdma->membase + (PDMA_CHAN_OFFSET * (ch)))
  48. struct pdma_regs {
  49. /* read-write regs */
  50. void __iomem *ctrl; /* 4 bytes */
  51. void __iomem *xfer_type; /* 4 bytes */
  52. void __iomem *xfer_size; /* 8 bytes */
  53. void __iomem *dst_addr; /* 8 bytes */
  54. void __iomem *src_addr; /* 8 bytes */
  55. /* read-only */
  56. void __iomem *act_type; /* 4 bytes */
  57. void __iomem *residue; /* 8 bytes */
  58. void __iomem *cur_dst_addr; /* 8 bytes */
  59. void __iomem *cur_src_addr; /* 8 bytes */
  60. };
  61. struct sf_pdma_desc {
  62. u32 xfer_type;
  63. u64 xfer_size;
  64. u64 dst_addr;
  65. u64 src_addr;
  66. struct virt_dma_desc vdesc;
  67. struct sf_pdma_chan *chan;
  68. enum dma_transfer_direction dirn;
  69. struct dma_async_tx_descriptor *async_tx;
  70. };
  71. enum sf_pdma_pm_state {
  72. RUNNING = 0,
  73. SUSPENDED,
  74. };
  75. struct sf_pdma_chan {
  76. struct virt_dma_chan vchan;
  77. enum dma_status status;
  78. enum sf_pdma_pm_state pm_state;
  79. u32 slave_id;
  80. struct sf_pdma *pdma;
  81. struct sf_pdma_desc *desc;
  82. struct dma_slave_config cfg;
  83. u32 attr;
  84. dma_addr_t dma_dev_addr;
  85. u32 dma_dev_size;
  86. struct tasklet_struct done_tasklet;
  87. struct tasklet_struct err_tasklet;
  88. struct pdma_regs regs;
  89. spinlock_t lock; /* protect chan data */
  90. bool xfer_err;
  91. int txirq;
  92. int errirq;
  93. int retries;
  94. };
  95. struct sf_pdma {
  96. struct dma_device dma_dev;
  97. void __iomem *membase;
  98. void __iomem *mappedbase;
  99. u32 n_chans;
  100. struct sf_pdma_chan chans[];
  101. };
  102. #endif /* _SF_PDMA_H */