of.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Platform driver for the Synopsys DesignWare DMA Controller
  4. *
  5. * Copyright (C) 2007-2008 Atmel Corporation
  6. * Copyright (C) 2010-2011 ST Microelectronics
  7. * Copyright (C) 2013 Intel Corporation
  8. */
  9. #include <linux/of.h>
  10. #include <linux/of_dma.h>
  11. #include <linux/platform_device.h>
  12. #include "internal.h"
  13. static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
  14. struct of_dma *ofdma)
  15. {
  16. struct dw_dma *dw = ofdma->of_dma_data;
  17. struct dw_dma_slave slave = {
  18. .dma_dev = dw->dma.dev,
  19. };
  20. dma_cap_mask_t cap;
  21. if (dma_spec->args_count < 3 || dma_spec->args_count > 4)
  22. return NULL;
  23. slave.src_id = dma_spec->args[0];
  24. slave.dst_id = dma_spec->args[0];
  25. slave.m_master = dma_spec->args[1];
  26. slave.p_master = dma_spec->args[2];
  27. if (dma_spec->args_count >= 4)
  28. slave.channels = dma_spec->args[3];
  29. if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
  30. slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
  31. slave.m_master >= dw->pdata->nr_masters ||
  32. slave.p_master >= dw->pdata->nr_masters ||
  33. slave.channels >= BIT(dw->pdata->nr_channels)))
  34. return NULL;
  35. dma_cap_zero(cap);
  36. dma_cap_set(DMA_SLAVE, cap);
  37. /* TODO: there should be a simpler way to do this */
  38. return dma_request_channel(cap, dw_dma_filter, &slave);
  39. }
  40. struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
  41. {
  42. struct device_node *np = pdev->dev.of_node;
  43. struct dw_dma_platform_data *pdata;
  44. u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
  45. u32 nr_masters;
  46. u32 nr_channels;
  47. if (of_property_read_u32(np, "dma-masters", &nr_masters))
  48. return NULL;
  49. if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
  50. return NULL;
  51. if (of_property_read_u32(np, "dma-channels", &nr_channels))
  52. return NULL;
  53. if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
  54. return NULL;
  55. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  56. if (!pdata)
  57. return NULL;
  58. pdata->nr_masters = nr_masters;
  59. pdata->nr_channels = nr_channels;
  60. of_property_read_u32(np, "chan_allocation_order", &pdata->chan_allocation_order);
  61. of_property_read_u32(np, "chan_priority", &pdata->chan_priority);
  62. of_property_read_u32(np, "block_size", &pdata->block_size);
  63. /* Try deprecated property first */
  64. if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
  65. for (tmp = 0; tmp < nr_masters; tmp++)
  66. pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
  67. }
  68. /* If "data_width" and "data-width" both provided use the latter one */
  69. of_property_read_u32_array(np, "data-width", pdata->data_width, nr_masters);
  70. memset32(pdata->multi_block, 1, nr_channels);
  71. of_property_read_u32_array(np, "multi-block", pdata->multi_block, nr_channels);
  72. memset32(pdata->max_burst, DW_DMA_MAX_BURST, nr_channels);
  73. of_property_read_u32_array(np, "snps,max-burst-len", pdata->max_burst, nr_channels);
  74. of_property_read_u32(np, "snps,dma-protection-control", &pdata->protctl);
  75. if (pdata->protctl > CHAN_PROTCTL_MASK)
  76. return NULL;
  77. return pdata;
  78. }
  79. void dw_dma_of_controller_register(struct dw_dma *dw)
  80. {
  81. struct device *dev = dw->dma.dev;
  82. int ret;
  83. if (!dev->of_node)
  84. return;
  85. ret = of_dma_controller_register(dev->of_node, dw_dma_of_xlate, dw);
  86. if (ret)
  87. dev_err(dev, "could not register of_dma_controller\n");
  88. }
  89. void dw_dma_of_controller_free(struct dw_dma *dw)
  90. {
  91. struct device *dev = dw->dma.dev;
  92. if (!dev->of_node)
  93. return;
  94. of_dma_controller_free(dev->of_node);
  95. }