qi.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * CAAM/SEC 4.x QI transport/backend driver
  4. * Queue Interface backend functionality
  5. *
  6. * Copyright 2013-2016 Freescale Semiconductor, Inc.
  7. * Copyright 2016-2017, 2019-2020 NXP
  8. */
  9. #include <linux/cpumask.h>
  10. #include <linux/kthread.h>
  11. #include <soc/fsl/qman.h>
  12. #include "debugfs.h"
  13. #include "regs.h"
  14. #include "qi.h"
  15. #include "desc.h"
  16. #include "intern.h"
  17. #include "desc_constr.h"
  18. #define PREHDR_RSLS_SHIFT 31
  19. #define PREHDR_ABS BIT(25)
  20. /*
  21. * Use a reasonable backlog of frames (per CPU) as congestion threshold,
  22. * so that resources used by the in-flight buffers do not become a memory hog.
  23. */
  24. #define MAX_RSP_FQ_BACKLOG_PER_CPU 256
  25. #define CAAM_QI_ENQUEUE_RETRIES 10000
  26. #define CAAM_NAPI_WEIGHT 63
  27. /*
  28. * caam_napi - struct holding CAAM NAPI-related params
  29. * @irqtask: IRQ task for QI backend
  30. * @p: QMan portal
  31. */
  32. struct caam_napi {
  33. struct napi_struct irqtask;
  34. struct qman_portal *p;
  35. };
  36. /*
  37. * caam_qi_pcpu_priv - percpu private data structure to main list of pending
  38. * responses expected on each cpu.
  39. * @caam_napi: CAAM NAPI params
  40. * @net_dev: netdev used by NAPI
  41. * @rsp_fq: response FQ from CAAM
  42. */
  43. struct caam_qi_pcpu_priv {
  44. struct caam_napi caam_napi;
  45. struct net_device net_dev;
  46. struct qman_fq *rsp_fq;
  47. } ____cacheline_aligned;
  48. static DEFINE_PER_CPU(struct caam_qi_pcpu_priv, pcpu_qipriv);
  49. static DEFINE_PER_CPU(int, last_cpu);
  50. /*
  51. * caam_qi_priv - CAAM QI backend private params
  52. * @cgr: QMan congestion group
  53. */
  54. struct caam_qi_priv {
  55. struct qman_cgr cgr;
  56. };
  57. static struct caam_qi_priv qipriv ____cacheline_aligned;
  58. /*
  59. * This is written by only one core - the one that initialized the CGR - and
  60. * read by multiple cores (all the others).
  61. */
  62. bool caam_congested __read_mostly;
  63. EXPORT_SYMBOL(caam_congested);
  64. /*
  65. * This is a cache of buffers, from which the users of CAAM QI driver
  66. * can allocate short (CAAM_QI_MEMCACHE_SIZE) buffers. It's faster than
  67. * doing malloc on the hotpath.
  68. * NOTE: A more elegant solution would be to have some headroom in the frames
  69. * being processed. This could be added by the dpaa-ethernet driver.
  70. * This would pose a problem for userspace application processing which
  71. * cannot know of this limitation. So for now, this will work.
  72. * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
  73. */
  74. static struct kmem_cache *qi_cache;
  75. static void *caam_iova_to_virt(struct iommu_domain *domain,
  76. dma_addr_t iova_addr)
  77. {
  78. phys_addr_t phys_addr;
  79. phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  80. return phys_to_virt(phys_addr);
  81. }
  82. int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req)
  83. {
  84. struct qm_fd fd;
  85. dma_addr_t addr;
  86. int ret;
  87. int num_retries = 0;
  88. qm_fd_clear_fd(&fd);
  89. qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1]));
  90. addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
  91. DMA_BIDIRECTIONAL);
  92. if (dma_mapping_error(qidev, addr)) {
  93. dev_err(qidev, "DMA mapping error for QI enqueue request\n");
  94. return -EIO;
  95. }
  96. qm_fd_addr_set64(&fd, addr);
  97. do {
  98. ret = qman_enqueue(req->drv_ctx->req_fq, &fd);
  99. if (likely(!ret)) {
  100. refcount_inc(&req->drv_ctx->refcnt);
  101. return 0;
  102. }
  103. if (ret != -EBUSY)
  104. break;
  105. num_retries++;
  106. } while (num_retries < CAAM_QI_ENQUEUE_RETRIES);
  107. dev_err(qidev, "qman_enqueue failed: %d\n", ret);
  108. return ret;
  109. }
  110. EXPORT_SYMBOL(caam_qi_enqueue);
  111. static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
  112. const union qm_mr_entry *msg)
  113. {
  114. const struct qm_fd *fd;
  115. struct caam_drv_req *drv_req;
  116. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  117. struct caam_drv_private *priv = dev_get_drvdata(qidev);
  118. fd = &msg->ern.fd;
  119. drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd));
  120. if (!drv_req) {
  121. dev_err(qidev,
  122. "Can't find original request for CAAM response\n");
  123. return;
  124. }
  125. refcount_dec(&drv_req->drv_ctx->refcnt);
  126. if (qm_fd_get_format(fd) != qm_fd_compound) {
  127. dev_err(qidev, "Non-compound FD from CAAM\n");
  128. return;
  129. }
  130. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  131. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  132. if (fd->status)
  133. drv_req->cbk(drv_req, be32_to_cpu(fd->status));
  134. else
  135. drv_req->cbk(drv_req, JRSTA_SSRC_QI);
  136. }
  137. static struct qman_fq *create_caam_req_fq(struct device *qidev,
  138. struct qman_fq *rsp_fq,
  139. dma_addr_t hwdesc,
  140. int fq_sched_flag)
  141. {
  142. int ret;
  143. struct qman_fq *req_fq;
  144. struct qm_mcc_initfq opts;
  145. req_fq = kzalloc(sizeof(*req_fq), GFP_ATOMIC);
  146. if (!req_fq)
  147. return ERR_PTR(-ENOMEM);
  148. req_fq->cb.ern = caam_fq_ern_cb;
  149. req_fq->cb.fqs = NULL;
  150. ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
  151. QMAN_FQ_FLAG_TO_DCPORTAL, req_fq);
  152. if (ret) {
  153. dev_err(qidev, "Failed to create session req FQ\n");
  154. goto create_req_fq_fail;
  155. }
  156. memset(&opts, 0, sizeof(opts));
  157. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  158. QM_INITFQ_WE_CONTEXTB |
  159. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  160. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  161. qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2);
  162. opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq));
  163. qm_fqd_context_a_set64(&opts.fqd, hwdesc);
  164. opts.fqd.cgid = qipriv.cgr.cgrid;
  165. ret = qman_init_fq(req_fq, fq_sched_flag, &opts);
  166. if (ret) {
  167. dev_err(qidev, "Failed to init session req FQ\n");
  168. goto init_req_fq_fail;
  169. }
  170. dev_dbg(qidev, "Allocated request FQ %u for CPU %u\n", req_fq->fqid,
  171. smp_processor_id());
  172. return req_fq;
  173. init_req_fq_fail:
  174. qman_destroy_fq(req_fq);
  175. create_req_fq_fail:
  176. kfree(req_fq);
  177. return ERR_PTR(ret);
  178. }
  179. static int empty_retired_fq(struct device *qidev, struct qman_fq *fq)
  180. {
  181. int ret;
  182. ret = qman_volatile_dequeue(fq, QMAN_VOLATILE_FLAG_WAIT_INT |
  183. QMAN_VOLATILE_FLAG_FINISH,
  184. QM_VDQCR_PRECEDENCE_VDQCR |
  185. QM_VDQCR_NUMFRAMES_TILLEMPTY);
  186. if (ret) {
  187. dev_err(qidev, "Volatile dequeue fail for FQ: %u\n", fq->fqid);
  188. return ret;
  189. }
  190. do {
  191. struct qman_portal *p;
  192. p = qman_get_affine_portal(smp_processor_id());
  193. qman_p_poll_dqrr(p, 16);
  194. } while (fq->flags & QMAN_FQ_STATE_NE);
  195. return 0;
  196. }
  197. static int kill_fq(struct device *qidev, struct qman_fq *fq)
  198. {
  199. u32 flags;
  200. int ret;
  201. ret = qman_retire_fq(fq, &flags);
  202. if (ret < 0) {
  203. dev_err(qidev, "qman_retire_fq failed: %d\n", ret);
  204. return ret;
  205. }
  206. if (!ret)
  207. goto empty_fq;
  208. /* Async FQ retirement condition */
  209. if (ret == 1) {
  210. /* Retry till FQ gets in retired state */
  211. do {
  212. msleep(20);
  213. } while (fq->state != qman_fq_state_retired);
  214. WARN_ON(fq->flags & QMAN_FQ_STATE_BLOCKOOS);
  215. WARN_ON(fq->flags & QMAN_FQ_STATE_ORL);
  216. }
  217. empty_fq:
  218. if (fq->flags & QMAN_FQ_STATE_NE) {
  219. ret = empty_retired_fq(qidev, fq);
  220. if (ret) {
  221. dev_err(qidev, "empty_retired_fq fail for FQ: %u\n",
  222. fq->fqid);
  223. return ret;
  224. }
  225. }
  226. ret = qman_oos_fq(fq);
  227. if (ret)
  228. dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid);
  229. qman_destroy_fq(fq);
  230. kfree(fq);
  231. return ret;
  232. }
  233. static int empty_caam_fq(struct qman_fq *fq, struct caam_drv_ctx *drv_ctx)
  234. {
  235. int ret;
  236. int retries = 10;
  237. struct qm_mcr_queryfq_np np;
  238. /* Wait till the older CAAM FQ get empty */
  239. do {
  240. ret = qman_query_fq_np(fq, &np);
  241. if (ret)
  242. return ret;
  243. if (!qm_mcr_np_get(&np, frm_cnt))
  244. break;
  245. msleep(20);
  246. } while (1);
  247. /* Wait until pending jobs from this FQ are processed by CAAM */
  248. do {
  249. if (refcount_read(&drv_ctx->refcnt) == 1)
  250. break;
  251. msleep(20);
  252. } while (--retries);
  253. if (!retries)
  254. dev_warn_once(drv_ctx->qidev, "%d frames from FQID %u still pending in CAAM\n",
  255. refcount_read(&drv_ctx->refcnt), fq->fqid);
  256. return 0;
  257. }
  258. int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc)
  259. {
  260. int ret;
  261. u32 num_words;
  262. struct qman_fq *new_fq, *old_fq;
  263. struct device *qidev = drv_ctx->qidev;
  264. num_words = desc_len(sh_desc);
  265. if (num_words > MAX_SDLEN) {
  266. dev_err(qidev, "Invalid descriptor len: %d words\n", num_words);
  267. return -EINVAL;
  268. }
  269. /* Note down older req FQ */
  270. old_fq = drv_ctx->req_fq;
  271. /* Create a new req FQ in parked state */
  272. new_fq = create_caam_req_fq(drv_ctx->qidev, drv_ctx->rsp_fq,
  273. drv_ctx->context_a, 0);
  274. if (IS_ERR(new_fq)) {
  275. dev_err(qidev, "FQ allocation for shdesc update failed\n");
  276. return PTR_ERR(new_fq);
  277. }
  278. /* Hook up new FQ to context so that new requests keep queuing */
  279. drv_ctx->req_fq = new_fq;
  280. /* Empty and remove the older FQ */
  281. ret = empty_caam_fq(old_fq, drv_ctx);
  282. if (ret) {
  283. dev_err(qidev, "Old CAAM FQ empty failed: %d\n", ret);
  284. /* We can revert to older FQ */
  285. drv_ctx->req_fq = old_fq;
  286. if (kill_fq(qidev, new_fq))
  287. dev_warn(qidev, "New CAAM FQ kill failed\n");
  288. return ret;
  289. }
  290. /*
  291. * Re-initialise pre-header. Set RSLS and SDLEN.
  292. * Update the shared descriptor for driver context.
  293. */
  294. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  295. num_words);
  296. drv_ctx->prehdr[1] = cpu_to_caam32(PREHDR_ABS);
  297. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  298. dma_sync_single_for_device(qidev, drv_ctx->context_a,
  299. sizeof(drv_ctx->sh_desc) +
  300. sizeof(drv_ctx->prehdr),
  301. DMA_BIDIRECTIONAL);
  302. /* Put the new FQ in scheduled state */
  303. ret = qman_schedule_fq(new_fq);
  304. if (ret) {
  305. dev_err(qidev, "Fail to sched new CAAM FQ, ecode = %d\n", ret);
  306. /*
  307. * We can kill new FQ and revert to old FQ.
  308. * Since the desc is already modified, it is success case
  309. */
  310. drv_ctx->req_fq = old_fq;
  311. if (kill_fq(qidev, new_fq))
  312. dev_warn(qidev, "New CAAM FQ kill failed\n");
  313. } else if (kill_fq(qidev, old_fq)) {
  314. dev_warn(qidev, "Old CAAM FQ kill failed\n");
  315. }
  316. return 0;
  317. }
  318. EXPORT_SYMBOL(caam_drv_ctx_update);
  319. struct caam_drv_ctx *caam_drv_ctx_init(struct device *qidev,
  320. int *cpu,
  321. u32 *sh_desc)
  322. {
  323. size_t size;
  324. u32 num_words;
  325. dma_addr_t hwdesc;
  326. struct caam_drv_ctx *drv_ctx;
  327. const cpumask_t *cpus = qman_affine_cpus();
  328. num_words = desc_len(sh_desc);
  329. if (num_words > MAX_SDLEN) {
  330. dev_err(qidev, "Invalid descriptor len: %d words\n",
  331. num_words);
  332. return ERR_PTR(-EINVAL);
  333. }
  334. drv_ctx = kzalloc(sizeof(*drv_ctx), GFP_ATOMIC);
  335. if (!drv_ctx)
  336. return ERR_PTR(-ENOMEM);
  337. /*
  338. * Initialise pre-header - set RSLS and SDLEN - and shared descriptor
  339. * and dma-map them.
  340. */
  341. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  342. num_words);
  343. drv_ctx->prehdr[1] = cpu_to_caam32(PREHDR_ABS);
  344. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  345. size = sizeof(drv_ctx->prehdr) + sizeof(drv_ctx->sh_desc);
  346. hwdesc = dma_map_single(qidev, drv_ctx->prehdr, size,
  347. DMA_BIDIRECTIONAL);
  348. if (dma_mapping_error(qidev, hwdesc)) {
  349. dev_err(qidev, "DMA map error for preheader + shdesc\n");
  350. kfree(drv_ctx);
  351. return ERR_PTR(-ENOMEM);
  352. }
  353. drv_ctx->context_a = hwdesc;
  354. /* If given CPU does not own the portal, choose another one that does */
  355. if (!cpumask_test_cpu(*cpu, cpus)) {
  356. int *pcpu = &get_cpu_var(last_cpu);
  357. *pcpu = cpumask_next(*pcpu, cpus);
  358. if (*pcpu >= nr_cpu_ids)
  359. *pcpu = cpumask_first(cpus);
  360. *cpu = *pcpu;
  361. put_cpu_var(last_cpu);
  362. }
  363. drv_ctx->cpu = *cpu;
  364. /* Find response FQ hooked with this CPU */
  365. drv_ctx->rsp_fq = per_cpu(pcpu_qipriv.rsp_fq, drv_ctx->cpu);
  366. /* Attach request FQ */
  367. drv_ctx->req_fq = create_caam_req_fq(qidev, drv_ctx->rsp_fq, hwdesc,
  368. QMAN_INITFQ_FLAG_SCHED);
  369. if (IS_ERR(drv_ctx->req_fq)) {
  370. dev_err(qidev, "create_caam_req_fq failed\n");
  371. dma_unmap_single(qidev, hwdesc, size, DMA_BIDIRECTIONAL);
  372. kfree(drv_ctx);
  373. return ERR_PTR(-ENOMEM);
  374. }
  375. /* init reference counter used to track references to request FQ */
  376. refcount_set(&drv_ctx->refcnt, 1);
  377. drv_ctx->qidev = qidev;
  378. return drv_ctx;
  379. }
  380. EXPORT_SYMBOL(caam_drv_ctx_init);
  381. void *qi_cache_alloc(gfp_t flags)
  382. {
  383. return kmem_cache_alloc(qi_cache, flags);
  384. }
  385. EXPORT_SYMBOL(qi_cache_alloc);
  386. void qi_cache_free(void *obj)
  387. {
  388. kmem_cache_free(qi_cache, obj);
  389. }
  390. EXPORT_SYMBOL(qi_cache_free);
  391. static int caam_qi_poll(struct napi_struct *napi, int budget)
  392. {
  393. struct caam_napi *np = container_of(napi, struct caam_napi, irqtask);
  394. int cleaned = qman_p_poll_dqrr(np->p, budget);
  395. if (cleaned < budget) {
  396. napi_complete(napi);
  397. qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
  398. }
  399. return cleaned;
  400. }
  401. void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx)
  402. {
  403. if (IS_ERR_OR_NULL(drv_ctx))
  404. return;
  405. /* Remove request FQ */
  406. if (kill_fq(drv_ctx->qidev, drv_ctx->req_fq))
  407. dev_err(drv_ctx->qidev, "Crypto session req FQ kill failed\n");
  408. dma_unmap_single(drv_ctx->qidev, drv_ctx->context_a,
  409. sizeof(drv_ctx->sh_desc) + sizeof(drv_ctx->prehdr),
  410. DMA_BIDIRECTIONAL);
  411. kfree(drv_ctx);
  412. }
  413. EXPORT_SYMBOL(caam_drv_ctx_rel);
  414. static void caam_qi_shutdown(void *data)
  415. {
  416. int i;
  417. struct device *qidev = data;
  418. struct caam_qi_priv *priv = &qipriv;
  419. const cpumask_t *cpus = qman_affine_cpus();
  420. for_each_cpu(i, cpus) {
  421. struct napi_struct *irqtask;
  422. irqtask = &per_cpu_ptr(&pcpu_qipriv.caam_napi, i)->irqtask;
  423. napi_disable(irqtask);
  424. netif_napi_del(irqtask);
  425. if (kill_fq(qidev, per_cpu(pcpu_qipriv.rsp_fq, i)))
  426. dev_err(qidev, "Rsp FQ kill failed, cpu: %d\n", i);
  427. }
  428. qman_delete_cgr_safe(&priv->cgr);
  429. qman_release_cgrid(priv->cgr.cgrid);
  430. kmem_cache_destroy(qi_cache);
  431. }
  432. static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)
  433. {
  434. caam_congested = congested;
  435. if (congested) {
  436. caam_debugfs_qi_congested();
  437. pr_debug_ratelimited("CAAM entered congestion\n");
  438. } else {
  439. pr_debug_ratelimited("CAAM exited congestion\n");
  440. }
  441. }
  442. static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np,
  443. bool sched_napi)
  444. {
  445. if (sched_napi) {
  446. /* Disable QMan IRQ source and invoke NAPI */
  447. qman_p_irqsource_remove(p, QM_PIRQ_DQRI);
  448. np->p = p;
  449. napi_schedule(&np->irqtask);
  450. return 1;
  451. }
  452. return 0;
  453. }
  454. static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p,
  455. struct qman_fq *rsp_fq,
  456. const struct qm_dqrr_entry *dqrr,
  457. bool sched_napi)
  458. {
  459. struct caam_napi *caam_napi = raw_cpu_ptr(&pcpu_qipriv.caam_napi);
  460. struct caam_drv_req *drv_req;
  461. const struct qm_fd *fd;
  462. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  463. struct caam_drv_private *priv = dev_get_drvdata(qidev);
  464. u32 status;
  465. if (caam_qi_napi_schedule(p, caam_napi, sched_napi))
  466. return qman_cb_dqrr_stop;
  467. fd = &dqrr->fd;
  468. drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd));
  469. if (unlikely(!drv_req)) {
  470. dev_err(qidev,
  471. "Can't find original request for caam response\n");
  472. return qman_cb_dqrr_consume;
  473. }
  474. refcount_dec(&drv_req->drv_ctx->refcnt);
  475. status = be32_to_cpu(fd->status);
  476. if (unlikely(status)) {
  477. u32 ssrc = status & JRSTA_SSRC_MASK;
  478. u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
  479. if (ssrc != JRSTA_SSRC_CCB_ERROR ||
  480. err_id != JRSTA_CCBERR_ERRID_ICVCHK)
  481. dev_err_ratelimited(qidev,
  482. "Error: %#x in CAAM response FD\n",
  483. status);
  484. }
  485. if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) {
  486. dev_err(qidev, "Non-compound FD from CAAM\n");
  487. return qman_cb_dqrr_consume;
  488. }
  489. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  490. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  491. drv_req->cbk(drv_req, status);
  492. return qman_cb_dqrr_consume;
  493. }
  494. static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu)
  495. {
  496. struct qm_mcc_initfq opts;
  497. struct qman_fq *fq;
  498. int ret;
  499. fq = kzalloc(sizeof(*fq), GFP_KERNEL | GFP_DMA);
  500. if (!fq)
  501. return -ENOMEM;
  502. fq->cb.dqrr = caam_rsp_fq_dqrr_cb;
  503. ret = qman_create_fq(0, QMAN_FQ_FLAG_NO_ENQUEUE |
  504. QMAN_FQ_FLAG_DYNAMIC_FQID, fq);
  505. if (ret) {
  506. dev_err(qidev, "Rsp FQ create failed\n");
  507. kfree(fq);
  508. return -ENODEV;
  509. }
  510. memset(&opts, 0, sizeof(opts));
  511. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  512. QM_INITFQ_WE_CONTEXTB |
  513. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  514. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING |
  515. QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  516. qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3);
  517. opts.fqd.cgid = qipriv.cgr.cgrid;
  518. opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX |
  519. QM_STASHING_EXCL_DATA;
  520. qm_fqd_set_stashing(&opts.fqd, 0, 1, 1);
  521. ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
  522. if (ret) {
  523. dev_err(qidev, "Rsp FQ init failed\n");
  524. kfree(fq);
  525. return -ENODEV;
  526. }
  527. per_cpu(pcpu_qipriv.rsp_fq, cpu) = fq;
  528. dev_dbg(qidev, "Allocated response FQ %u for CPU %u", fq->fqid, cpu);
  529. return 0;
  530. }
  531. static int init_cgr(struct device *qidev)
  532. {
  533. int ret;
  534. struct qm_mcc_initcgr opts;
  535. const u64 val = (u64)cpumask_weight(qman_affine_cpus()) *
  536. MAX_RSP_FQ_BACKLOG_PER_CPU;
  537. ret = qman_alloc_cgrid(&qipriv.cgr.cgrid);
  538. if (ret) {
  539. dev_err(qidev, "CGR alloc failed for rsp FQs: %d\n", ret);
  540. return ret;
  541. }
  542. qipriv.cgr.cb = cgr_cb;
  543. memset(&opts, 0, sizeof(opts));
  544. opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES |
  545. QM_CGR_WE_MODE);
  546. opts.cgr.cscn_en = QM_CGR_EN;
  547. opts.cgr.mode = QMAN_CGR_MODE_FRAME;
  548. qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1);
  549. ret = qman_create_cgr(&qipriv.cgr, QMAN_CGR_FLAG_USE_INIT, &opts);
  550. if (ret) {
  551. dev_err(qidev, "Error %d creating CAAM CGRID: %u\n", ret,
  552. qipriv.cgr.cgrid);
  553. return ret;
  554. }
  555. dev_dbg(qidev, "Congestion threshold set to %llu\n", val);
  556. return 0;
  557. }
  558. static int alloc_rsp_fqs(struct device *qidev)
  559. {
  560. int ret, i;
  561. const cpumask_t *cpus = qman_affine_cpus();
  562. /*Now create response FQs*/
  563. for_each_cpu(i, cpus) {
  564. ret = alloc_rsp_fq_cpu(qidev, i);
  565. if (ret) {
  566. dev_err(qidev, "CAAM rsp FQ alloc failed, cpu: %u", i);
  567. return ret;
  568. }
  569. }
  570. return 0;
  571. }
  572. static void free_rsp_fqs(void)
  573. {
  574. int i;
  575. const cpumask_t *cpus = qman_affine_cpus();
  576. for_each_cpu(i, cpus)
  577. kfree(per_cpu(pcpu_qipriv.rsp_fq, i));
  578. }
  579. int caam_qi_init(struct platform_device *caam_pdev)
  580. {
  581. int err, i;
  582. struct device *ctrldev = &caam_pdev->dev, *qidev;
  583. struct caam_drv_private *ctrlpriv;
  584. const cpumask_t *cpus = qman_affine_cpus();
  585. ctrlpriv = dev_get_drvdata(ctrldev);
  586. qidev = ctrldev;
  587. /* Initialize the congestion detection */
  588. err = init_cgr(qidev);
  589. if (err) {
  590. dev_err(qidev, "CGR initialization failed: %d\n", err);
  591. return err;
  592. }
  593. /* Initialise response FQs */
  594. err = alloc_rsp_fqs(qidev);
  595. if (err) {
  596. dev_err(qidev, "Can't allocate CAAM response FQs: %d\n", err);
  597. free_rsp_fqs();
  598. return err;
  599. }
  600. /*
  601. * Enable the NAPI contexts on each of the core which has an affine
  602. * portal.
  603. */
  604. for_each_cpu(i, cpus) {
  605. struct caam_qi_pcpu_priv *priv = per_cpu_ptr(&pcpu_qipriv, i);
  606. struct caam_napi *caam_napi = &priv->caam_napi;
  607. struct napi_struct *irqtask = &caam_napi->irqtask;
  608. struct net_device *net_dev = &priv->net_dev;
  609. net_dev->dev = *qidev;
  610. INIT_LIST_HEAD(&net_dev->napi_list);
  611. netif_napi_add_tx_weight(net_dev, irqtask, caam_qi_poll,
  612. CAAM_NAPI_WEIGHT);
  613. napi_enable(irqtask);
  614. }
  615. qi_cache = kmem_cache_create("caamqicache", CAAM_QI_MEMCACHE_SIZE, 0,
  616. SLAB_CACHE_DMA, NULL);
  617. if (!qi_cache) {
  618. dev_err(qidev, "Can't allocate CAAM cache\n");
  619. free_rsp_fqs();
  620. return -ENOMEM;
  621. }
  622. caam_debugfs_qi_init(ctrlpriv);
  623. err = devm_add_action_or_reset(qidev, caam_qi_shutdown, ctrlpriv);
  624. if (err)
  625. return err;
  626. dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n");
  627. return 0;
  628. }