aspeed-hace-crypto.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2021 Aspeed Technology Inc.
  4. */
  5. #include "aspeed-hace.h"
  6. #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO_DEBUG
  7. #define CIPHER_DBG(h, fmt, ...) \
  8. dev_info((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
  9. #else
  10. #define CIPHER_DBG(h, fmt, ...) \
  11. dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
  12. #endif
  13. static int aspeed_crypto_do_fallback(struct skcipher_request *areq)
  14. {
  15. struct aspeed_cipher_reqctx *rctx = skcipher_request_ctx(areq);
  16. struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
  17. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
  18. int err;
  19. skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  20. skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags,
  21. areq->base.complete, areq->base.data);
  22. skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst,
  23. areq->cryptlen, areq->iv);
  24. if (rctx->enc_cmd & HACE_CMD_ENCRYPT)
  25. err = crypto_skcipher_encrypt(&rctx->fallback_req);
  26. else
  27. err = crypto_skcipher_decrypt(&rctx->fallback_req);
  28. return err;
  29. }
  30. static bool aspeed_crypto_need_fallback(struct skcipher_request *areq)
  31. {
  32. struct aspeed_cipher_reqctx *rctx = skcipher_request_ctx(areq);
  33. if (areq->cryptlen == 0)
  34. return true;
  35. if ((rctx->enc_cmd & HACE_CMD_DES_SELECT) &&
  36. !IS_ALIGNED(areq->cryptlen, DES_BLOCK_SIZE))
  37. return true;
  38. if ((!(rctx->enc_cmd & HACE_CMD_DES_SELECT)) &&
  39. !IS_ALIGNED(areq->cryptlen, AES_BLOCK_SIZE))
  40. return true;
  41. return false;
  42. }
  43. static int aspeed_hace_crypto_handle_queue(struct aspeed_hace_dev *hace_dev,
  44. struct skcipher_request *req)
  45. {
  46. if (hace_dev->version == AST2500_VERSION &&
  47. aspeed_crypto_need_fallback(req)) {
  48. CIPHER_DBG(hace_dev, "SW fallback\n");
  49. return aspeed_crypto_do_fallback(req);
  50. }
  51. return crypto_transfer_skcipher_request_to_engine(
  52. hace_dev->crypt_engine_crypto, req);
  53. }
  54. static int aspeed_crypto_do_request(struct crypto_engine *engine, void *areq)
  55. {
  56. struct skcipher_request *req = skcipher_request_cast(areq);
  57. struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req);
  58. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
  59. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  60. struct aspeed_engine_crypto *crypto_engine;
  61. int rc;
  62. crypto_engine = &hace_dev->crypto_engine;
  63. crypto_engine->req = req;
  64. crypto_engine->flags |= CRYPTO_FLAGS_BUSY;
  65. rc = ctx->start(hace_dev);
  66. if (rc != -EINPROGRESS)
  67. return -EIO;
  68. return 0;
  69. }
  70. static int aspeed_sk_complete(struct aspeed_hace_dev *hace_dev, int err)
  71. {
  72. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  73. struct aspeed_cipher_reqctx *rctx;
  74. struct skcipher_request *req;
  75. CIPHER_DBG(hace_dev, "\n");
  76. req = crypto_engine->req;
  77. rctx = skcipher_request_ctx(req);
  78. if (rctx->enc_cmd & HACE_CMD_IV_REQUIRE) {
  79. if (rctx->enc_cmd & HACE_CMD_DES_SELECT)
  80. memcpy(req->iv, crypto_engine->cipher_ctx +
  81. DES_KEY_SIZE, DES_KEY_SIZE);
  82. else
  83. memcpy(req->iv, crypto_engine->cipher_ctx,
  84. AES_BLOCK_SIZE);
  85. }
  86. crypto_engine->flags &= ~CRYPTO_FLAGS_BUSY;
  87. crypto_finalize_skcipher_request(hace_dev->crypt_engine_crypto, req,
  88. err);
  89. return err;
  90. }
  91. static int aspeed_sk_transfer_sg(struct aspeed_hace_dev *hace_dev)
  92. {
  93. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  94. struct device *dev = hace_dev->dev;
  95. struct aspeed_cipher_reqctx *rctx;
  96. struct skcipher_request *req;
  97. CIPHER_DBG(hace_dev, "\n");
  98. req = crypto_engine->req;
  99. rctx = skcipher_request_ctx(req);
  100. if (req->src == req->dst) {
  101. dma_unmap_sg(dev, req->src, rctx->src_nents, DMA_BIDIRECTIONAL);
  102. } else {
  103. dma_unmap_sg(dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  104. dma_unmap_sg(dev, req->dst, rctx->dst_nents, DMA_FROM_DEVICE);
  105. }
  106. return aspeed_sk_complete(hace_dev, 0);
  107. }
  108. static int aspeed_sk_transfer(struct aspeed_hace_dev *hace_dev)
  109. {
  110. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  111. struct aspeed_cipher_reqctx *rctx;
  112. struct skcipher_request *req;
  113. struct scatterlist *out_sg;
  114. int nbytes = 0;
  115. int rc = 0;
  116. req = crypto_engine->req;
  117. rctx = skcipher_request_ctx(req);
  118. out_sg = req->dst;
  119. /* Copy output buffer to dst scatter-gather lists */
  120. nbytes = sg_copy_from_buffer(out_sg, rctx->dst_nents,
  121. crypto_engine->cipher_addr, req->cryptlen);
  122. if (!nbytes) {
  123. dev_warn(hace_dev->dev, "invalid sg copy, %s:0x%x, %s:0x%x\n",
  124. "nbytes", nbytes, "cryptlen", req->cryptlen);
  125. rc = -EINVAL;
  126. }
  127. CIPHER_DBG(hace_dev, "%s:%d, %s:%d, %s:%d, %s:%p\n",
  128. "nbytes", nbytes, "req->cryptlen", req->cryptlen,
  129. "nb_out_sg", rctx->dst_nents,
  130. "cipher addr", crypto_engine->cipher_addr);
  131. return aspeed_sk_complete(hace_dev, rc);
  132. }
  133. static int aspeed_sk_start(struct aspeed_hace_dev *hace_dev)
  134. {
  135. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  136. struct aspeed_cipher_reqctx *rctx;
  137. struct skcipher_request *req;
  138. struct scatterlist *in_sg;
  139. int nbytes;
  140. req = crypto_engine->req;
  141. rctx = skcipher_request_ctx(req);
  142. in_sg = req->src;
  143. nbytes = sg_copy_to_buffer(in_sg, rctx->src_nents,
  144. crypto_engine->cipher_addr, req->cryptlen);
  145. CIPHER_DBG(hace_dev, "%s:%d, %s:%d, %s:%d, %s:%p\n",
  146. "nbytes", nbytes, "req->cryptlen", req->cryptlen,
  147. "nb_in_sg", rctx->src_nents,
  148. "cipher addr", crypto_engine->cipher_addr);
  149. if (!nbytes) {
  150. dev_warn(hace_dev->dev, "invalid sg copy, %s:0x%x, %s:0x%x\n",
  151. "nbytes", nbytes, "cryptlen", req->cryptlen);
  152. return -EINVAL;
  153. }
  154. crypto_engine->resume = aspeed_sk_transfer;
  155. /* Trigger engines */
  156. ast_hace_write(hace_dev, crypto_engine->cipher_dma_addr,
  157. ASPEED_HACE_SRC);
  158. ast_hace_write(hace_dev, crypto_engine->cipher_dma_addr,
  159. ASPEED_HACE_DEST);
  160. ast_hace_write(hace_dev, req->cryptlen, ASPEED_HACE_DATA_LEN);
  161. ast_hace_write(hace_dev, rctx->enc_cmd, ASPEED_HACE_CMD);
  162. return -EINPROGRESS;
  163. }
  164. static int aspeed_sk_start_sg(struct aspeed_hace_dev *hace_dev)
  165. {
  166. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  167. struct aspeed_sg_list *src_list, *dst_list;
  168. dma_addr_t src_dma_addr, dst_dma_addr;
  169. struct aspeed_cipher_reqctx *rctx;
  170. struct skcipher_request *req;
  171. struct scatterlist *s;
  172. int src_sg_len;
  173. int dst_sg_len;
  174. int total, i;
  175. int rc;
  176. CIPHER_DBG(hace_dev, "\n");
  177. req = crypto_engine->req;
  178. rctx = skcipher_request_ctx(req);
  179. rctx->enc_cmd |= HACE_CMD_DES_SG_CTRL | HACE_CMD_SRC_SG_CTRL |
  180. HACE_CMD_AES_KEY_HW_EXP | HACE_CMD_MBUS_REQ_SYNC_EN;
  181. /* BIDIRECTIONAL */
  182. if (req->dst == req->src) {
  183. src_sg_len = dma_map_sg(hace_dev->dev, req->src,
  184. rctx->src_nents, DMA_BIDIRECTIONAL);
  185. dst_sg_len = src_sg_len;
  186. if (!src_sg_len) {
  187. dev_warn(hace_dev->dev, "dma_map_sg() src error\n");
  188. return -EINVAL;
  189. }
  190. } else {
  191. src_sg_len = dma_map_sg(hace_dev->dev, req->src,
  192. rctx->src_nents, DMA_TO_DEVICE);
  193. if (!src_sg_len) {
  194. dev_warn(hace_dev->dev, "dma_map_sg() src error\n");
  195. return -EINVAL;
  196. }
  197. dst_sg_len = dma_map_sg(hace_dev->dev, req->dst,
  198. rctx->dst_nents, DMA_FROM_DEVICE);
  199. if (!dst_sg_len) {
  200. dev_warn(hace_dev->dev, "dma_map_sg() dst error\n");
  201. rc = -EINVAL;
  202. goto free_req_src;
  203. }
  204. }
  205. src_list = (struct aspeed_sg_list *)crypto_engine->cipher_addr;
  206. src_dma_addr = crypto_engine->cipher_dma_addr;
  207. total = req->cryptlen;
  208. for_each_sg(req->src, s, src_sg_len, i) {
  209. u32 phy_addr = sg_dma_address(s);
  210. u32 len = sg_dma_len(s);
  211. if (total > len)
  212. total -= len;
  213. else {
  214. /* last sg list */
  215. len = total;
  216. len |= BIT(31);
  217. total = 0;
  218. }
  219. src_list[i].phy_addr = cpu_to_le32(phy_addr);
  220. src_list[i].len = cpu_to_le32(len);
  221. }
  222. if (total != 0) {
  223. rc = -EINVAL;
  224. goto free_req;
  225. }
  226. if (req->dst == req->src) {
  227. dst_list = src_list;
  228. dst_dma_addr = src_dma_addr;
  229. } else {
  230. dst_list = (struct aspeed_sg_list *)crypto_engine->dst_sg_addr;
  231. dst_dma_addr = crypto_engine->dst_sg_dma_addr;
  232. total = req->cryptlen;
  233. for_each_sg(req->dst, s, dst_sg_len, i) {
  234. u32 phy_addr = sg_dma_address(s);
  235. u32 len = sg_dma_len(s);
  236. if (total > len)
  237. total -= len;
  238. else {
  239. /* last sg list */
  240. len = total;
  241. len |= BIT(31);
  242. total = 0;
  243. }
  244. dst_list[i].phy_addr = cpu_to_le32(phy_addr);
  245. dst_list[i].len = cpu_to_le32(len);
  246. }
  247. dst_list[dst_sg_len].phy_addr = 0;
  248. dst_list[dst_sg_len].len = 0;
  249. }
  250. if (total != 0) {
  251. rc = -EINVAL;
  252. goto free_req;
  253. }
  254. crypto_engine->resume = aspeed_sk_transfer_sg;
  255. /* Memory barrier to ensure all data setup before engine starts */
  256. mb();
  257. /* Trigger engines */
  258. ast_hace_write(hace_dev, src_dma_addr, ASPEED_HACE_SRC);
  259. ast_hace_write(hace_dev, dst_dma_addr, ASPEED_HACE_DEST);
  260. ast_hace_write(hace_dev, req->cryptlen, ASPEED_HACE_DATA_LEN);
  261. ast_hace_write(hace_dev, rctx->enc_cmd, ASPEED_HACE_CMD);
  262. return -EINPROGRESS;
  263. free_req:
  264. if (req->dst == req->src) {
  265. dma_unmap_sg(hace_dev->dev, req->src, rctx->src_nents,
  266. DMA_BIDIRECTIONAL);
  267. } else {
  268. dma_unmap_sg(hace_dev->dev, req->dst, rctx->dst_nents,
  269. DMA_TO_DEVICE);
  270. dma_unmap_sg(hace_dev->dev, req->src, rctx->src_nents,
  271. DMA_TO_DEVICE);
  272. }
  273. return rc;
  274. free_req_src:
  275. dma_unmap_sg(hace_dev->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  276. return rc;
  277. }
  278. static int aspeed_hace_skcipher_trigger(struct aspeed_hace_dev *hace_dev)
  279. {
  280. struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
  281. struct aspeed_cipher_reqctx *rctx;
  282. struct crypto_skcipher *cipher;
  283. struct aspeed_cipher_ctx *ctx;
  284. struct skcipher_request *req;
  285. CIPHER_DBG(hace_dev, "\n");
  286. req = crypto_engine->req;
  287. rctx = skcipher_request_ctx(req);
  288. cipher = crypto_skcipher_reqtfm(req);
  289. ctx = crypto_skcipher_ctx(cipher);
  290. /* enable interrupt */
  291. rctx->enc_cmd |= HACE_CMD_ISR_EN;
  292. rctx->dst_nents = sg_nents(req->dst);
  293. rctx->src_nents = sg_nents(req->src);
  294. ast_hace_write(hace_dev, crypto_engine->cipher_ctx_dma,
  295. ASPEED_HACE_CONTEXT);
  296. if (rctx->enc_cmd & HACE_CMD_IV_REQUIRE) {
  297. if (rctx->enc_cmd & HACE_CMD_DES_SELECT)
  298. memcpy(crypto_engine->cipher_ctx + DES_BLOCK_SIZE,
  299. req->iv, DES_BLOCK_SIZE);
  300. else
  301. memcpy(crypto_engine->cipher_ctx, req->iv,
  302. AES_BLOCK_SIZE);
  303. }
  304. if (hace_dev->version == AST2600_VERSION) {
  305. memcpy(crypto_engine->cipher_ctx + 16, ctx->key, ctx->key_len);
  306. return aspeed_sk_start_sg(hace_dev);
  307. }
  308. memcpy(crypto_engine->cipher_ctx + 16, ctx->key, AES_MAX_KEYLENGTH);
  309. return aspeed_sk_start(hace_dev);
  310. }
  311. static int aspeed_des_crypt(struct skcipher_request *req, u32 cmd)
  312. {
  313. struct aspeed_cipher_reqctx *rctx = skcipher_request_ctx(req);
  314. struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req);
  315. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
  316. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  317. u32 crypto_alg = cmd & HACE_CMD_OP_MODE_MASK;
  318. CIPHER_DBG(hace_dev, "\n");
  319. if (crypto_alg == HACE_CMD_CBC || crypto_alg == HACE_CMD_ECB) {
  320. if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
  321. return -EINVAL;
  322. }
  323. rctx->enc_cmd = cmd | HACE_CMD_DES_SELECT | HACE_CMD_RI_WO_DATA_ENABLE |
  324. HACE_CMD_DES | HACE_CMD_CONTEXT_LOAD_ENABLE |
  325. HACE_CMD_CONTEXT_SAVE_ENABLE;
  326. return aspeed_hace_crypto_handle_queue(hace_dev, req);
  327. }
  328. static int aspeed_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
  329. unsigned int keylen)
  330. {
  331. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
  332. struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
  333. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  334. int rc;
  335. CIPHER_DBG(hace_dev, "keylen: %d bits\n", keylen);
  336. if (keylen != DES_KEY_SIZE && keylen != DES3_EDE_KEY_SIZE) {
  337. dev_warn(hace_dev->dev, "invalid keylen: %d bits\n", keylen);
  338. return -EINVAL;
  339. }
  340. if (keylen == DES_KEY_SIZE) {
  341. rc = crypto_des_verify_key(tfm, key);
  342. if (rc)
  343. return rc;
  344. } else if (keylen == DES3_EDE_KEY_SIZE) {
  345. rc = crypto_des3_ede_verify_key(tfm, key);
  346. if (rc)
  347. return rc;
  348. }
  349. memcpy(ctx->key, key, keylen);
  350. ctx->key_len = keylen;
  351. crypto_skcipher_clear_flags(ctx->fallback_tfm, CRYPTO_TFM_REQ_MASK);
  352. crypto_skcipher_set_flags(ctx->fallback_tfm, cipher->base.crt_flags &
  353. CRYPTO_TFM_REQ_MASK);
  354. return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
  355. }
  356. static int aspeed_tdes_ctr_decrypt(struct skcipher_request *req)
  357. {
  358. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CTR |
  359. HACE_CMD_TRIPLE_DES);
  360. }
  361. static int aspeed_tdes_ctr_encrypt(struct skcipher_request *req)
  362. {
  363. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CTR |
  364. HACE_CMD_TRIPLE_DES);
  365. }
  366. static int aspeed_tdes_ofb_decrypt(struct skcipher_request *req)
  367. {
  368. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB |
  369. HACE_CMD_TRIPLE_DES);
  370. }
  371. static int aspeed_tdes_ofb_encrypt(struct skcipher_request *req)
  372. {
  373. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB |
  374. HACE_CMD_TRIPLE_DES);
  375. }
  376. static int aspeed_tdes_cfb_decrypt(struct skcipher_request *req)
  377. {
  378. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB |
  379. HACE_CMD_TRIPLE_DES);
  380. }
  381. static int aspeed_tdes_cfb_encrypt(struct skcipher_request *req)
  382. {
  383. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB |
  384. HACE_CMD_TRIPLE_DES);
  385. }
  386. static int aspeed_tdes_cbc_decrypt(struct skcipher_request *req)
  387. {
  388. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC |
  389. HACE_CMD_TRIPLE_DES);
  390. }
  391. static int aspeed_tdes_cbc_encrypt(struct skcipher_request *req)
  392. {
  393. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CBC |
  394. HACE_CMD_TRIPLE_DES);
  395. }
  396. static int aspeed_tdes_ecb_decrypt(struct skcipher_request *req)
  397. {
  398. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_ECB |
  399. HACE_CMD_TRIPLE_DES);
  400. }
  401. static int aspeed_tdes_ecb_encrypt(struct skcipher_request *req)
  402. {
  403. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_ECB |
  404. HACE_CMD_TRIPLE_DES);
  405. }
  406. static int aspeed_des_ctr_decrypt(struct skcipher_request *req)
  407. {
  408. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CTR |
  409. HACE_CMD_SINGLE_DES);
  410. }
  411. static int aspeed_des_ctr_encrypt(struct skcipher_request *req)
  412. {
  413. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CTR |
  414. HACE_CMD_SINGLE_DES);
  415. }
  416. static int aspeed_des_ofb_decrypt(struct skcipher_request *req)
  417. {
  418. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB |
  419. HACE_CMD_SINGLE_DES);
  420. }
  421. static int aspeed_des_ofb_encrypt(struct skcipher_request *req)
  422. {
  423. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB |
  424. HACE_CMD_SINGLE_DES);
  425. }
  426. static int aspeed_des_cfb_decrypt(struct skcipher_request *req)
  427. {
  428. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB |
  429. HACE_CMD_SINGLE_DES);
  430. }
  431. static int aspeed_des_cfb_encrypt(struct skcipher_request *req)
  432. {
  433. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB |
  434. HACE_CMD_SINGLE_DES);
  435. }
  436. static int aspeed_des_cbc_decrypt(struct skcipher_request *req)
  437. {
  438. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC |
  439. HACE_CMD_SINGLE_DES);
  440. }
  441. static int aspeed_des_cbc_encrypt(struct skcipher_request *req)
  442. {
  443. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CBC |
  444. HACE_CMD_SINGLE_DES);
  445. }
  446. static int aspeed_des_ecb_decrypt(struct skcipher_request *req)
  447. {
  448. return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_ECB |
  449. HACE_CMD_SINGLE_DES);
  450. }
  451. static int aspeed_des_ecb_encrypt(struct skcipher_request *req)
  452. {
  453. return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_ECB |
  454. HACE_CMD_SINGLE_DES);
  455. }
  456. static int aspeed_aes_crypt(struct skcipher_request *req, u32 cmd)
  457. {
  458. struct aspeed_cipher_reqctx *rctx = skcipher_request_ctx(req);
  459. struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req);
  460. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
  461. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  462. u32 crypto_alg = cmd & HACE_CMD_OP_MODE_MASK;
  463. if (crypto_alg == HACE_CMD_CBC || crypto_alg == HACE_CMD_ECB) {
  464. if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE))
  465. return -EINVAL;
  466. }
  467. CIPHER_DBG(hace_dev, "%s\n",
  468. (cmd & HACE_CMD_ENCRYPT) ? "encrypt" : "decrypt");
  469. cmd |= HACE_CMD_AES_SELECT | HACE_CMD_RI_WO_DATA_ENABLE |
  470. HACE_CMD_CONTEXT_LOAD_ENABLE | HACE_CMD_CONTEXT_SAVE_ENABLE;
  471. switch (ctx->key_len) {
  472. case AES_KEYSIZE_128:
  473. cmd |= HACE_CMD_AES128;
  474. break;
  475. case AES_KEYSIZE_192:
  476. cmd |= HACE_CMD_AES192;
  477. break;
  478. case AES_KEYSIZE_256:
  479. cmd |= HACE_CMD_AES256;
  480. break;
  481. default:
  482. return -EINVAL;
  483. }
  484. rctx->enc_cmd = cmd;
  485. return aspeed_hace_crypto_handle_queue(hace_dev, req);
  486. }
  487. static int aspeed_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
  488. unsigned int keylen)
  489. {
  490. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
  491. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  492. struct crypto_aes_ctx gen_aes_key;
  493. CIPHER_DBG(hace_dev, "keylen: %d bits\n", (keylen * 8));
  494. if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
  495. keylen != AES_KEYSIZE_256)
  496. return -EINVAL;
  497. if (ctx->hace_dev->version == AST2500_VERSION) {
  498. aes_expandkey(&gen_aes_key, key, keylen);
  499. memcpy(ctx->key, gen_aes_key.key_enc, AES_MAX_KEYLENGTH);
  500. } else {
  501. memcpy(ctx->key, key, keylen);
  502. }
  503. ctx->key_len = keylen;
  504. crypto_skcipher_clear_flags(ctx->fallback_tfm, CRYPTO_TFM_REQ_MASK);
  505. crypto_skcipher_set_flags(ctx->fallback_tfm, cipher->base.crt_flags &
  506. CRYPTO_TFM_REQ_MASK);
  507. return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
  508. }
  509. static int aspeed_aes_ctr_decrypt(struct skcipher_request *req)
  510. {
  511. return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CTR);
  512. }
  513. static int aspeed_aes_ctr_encrypt(struct skcipher_request *req)
  514. {
  515. return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CTR);
  516. }
  517. static int aspeed_aes_ofb_decrypt(struct skcipher_request *req)
  518. {
  519. return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB);
  520. }
  521. static int aspeed_aes_ofb_encrypt(struct skcipher_request *req)
  522. {
  523. return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB);
  524. }
  525. static int aspeed_aes_cfb_decrypt(struct skcipher_request *req)
  526. {
  527. return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB);
  528. }
  529. static int aspeed_aes_cfb_encrypt(struct skcipher_request *req)
  530. {
  531. return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB);
  532. }
  533. static int aspeed_aes_cbc_decrypt(struct skcipher_request *req)
  534. {
  535. return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC);
  536. }
  537. static int aspeed_aes_cbc_encrypt(struct skcipher_request *req)
  538. {
  539. return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CBC);
  540. }
  541. static int aspeed_aes_ecb_decrypt(struct skcipher_request *req)
  542. {
  543. return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_ECB);
  544. }
  545. static int aspeed_aes_ecb_encrypt(struct skcipher_request *req)
  546. {
  547. return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_ECB);
  548. }
  549. static int aspeed_crypto_cra_init(struct crypto_skcipher *tfm)
  550. {
  551. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
  552. struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
  553. const char *name = crypto_tfm_alg_name(&tfm->base);
  554. struct aspeed_hace_alg *crypto_alg;
  555. crypto_alg = container_of(alg, struct aspeed_hace_alg, alg.skcipher);
  556. ctx->hace_dev = crypto_alg->hace_dev;
  557. ctx->start = aspeed_hace_skcipher_trigger;
  558. CIPHER_DBG(ctx->hace_dev, "%s\n", name);
  559. ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_ASYNC |
  560. CRYPTO_ALG_NEED_FALLBACK);
  561. if (IS_ERR(ctx->fallback_tfm)) {
  562. dev_err(ctx->hace_dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
  563. name, PTR_ERR(ctx->fallback_tfm));
  564. return PTR_ERR(ctx->fallback_tfm);
  565. }
  566. crypto_skcipher_set_reqsize(tfm, sizeof(struct aspeed_cipher_reqctx) +
  567. crypto_skcipher_reqsize(ctx->fallback_tfm));
  568. ctx->enginectx.op.do_one_request = aspeed_crypto_do_request;
  569. ctx->enginectx.op.prepare_request = NULL;
  570. ctx->enginectx.op.unprepare_request = NULL;
  571. return 0;
  572. }
  573. static void aspeed_crypto_cra_exit(struct crypto_skcipher *tfm)
  574. {
  575. struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
  576. struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
  577. CIPHER_DBG(hace_dev, "%s\n", crypto_tfm_alg_name(&tfm->base));
  578. crypto_free_skcipher(ctx->fallback_tfm);
  579. }
  580. static struct aspeed_hace_alg aspeed_crypto_algs[] = {
  581. {
  582. .alg.skcipher = {
  583. .min_keysize = AES_MIN_KEY_SIZE,
  584. .max_keysize = AES_MAX_KEY_SIZE,
  585. .setkey = aspeed_aes_setkey,
  586. .encrypt = aspeed_aes_ecb_encrypt,
  587. .decrypt = aspeed_aes_ecb_decrypt,
  588. .init = aspeed_crypto_cra_init,
  589. .exit = aspeed_crypto_cra_exit,
  590. .base = {
  591. .cra_name = "ecb(aes)",
  592. .cra_driver_name = "aspeed-ecb-aes",
  593. .cra_priority = 300,
  594. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  595. CRYPTO_ALG_ASYNC |
  596. CRYPTO_ALG_NEED_FALLBACK,
  597. .cra_blocksize = AES_BLOCK_SIZE,
  598. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  599. .cra_alignmask = 0x0f,
  600. .cra_module = THIS_MODULE,
  601. }
  602. }
  603. },
  604. {
  605. .alg.skcipher = {
  606. .ivsize = AES_BLOCK_SIZE,
  607. .min_keysize = AES_MIN_KEY_SIZE,
  608. .max_keysize = AES_MAX_KEY_SIZE,
  609. .setkey = aspeed_aes_setkey,
  610. .encrypt = aspeed_aes_cbc_encrypt,
  611. .decrypt = aspeed_aes_cbc_decrypt,
  612. .init = aspeed_crypto_cra_init,
  613. .exit = aspeed_crypto_cra_exit,
  614. .base = {
  615. .cra_name = "cbc(aes)",
  616. .cra_driver_name = "aspeed-cbc-aes",
  617. .cra_priority = 300,
  618. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  619. CRYPTO_ALG_ASYNC |
  620. CRYPTO_ALG_NEED_FALLBACK,
  621. .cra_blocksize = AES_BLOCK_SIZE,
  622. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  623. .cra_alignmask = 0x0f,
  624. .cra_module = THIS_MODULE,
  625. }
  626. }
  627. },
  628. {
  629. .alg.skcipher = {
  630. .ivsize = AES_BLOCK_SIZE,
  631. .min_keysize = AES_MIN_KEY_SIZE,
  632. .max_keysize = AES_MAX_KEY_SIZE,
  633. .setkey = aspeed_aes_setkey,
  634. .encrypt = aspeed_aes_cfb_encrypt,
  635. .decrypt = aspeed_aes_cfb_decrypt,
  636. .init = aspeed_crypto_cra_init,
  637. .exit = aspeed_crypto_cra_exit,
  638. .base = {
  639. .cra_name = "cfb(aes)",
  640. .cra_driver_name = "aspeed-cfb-aes",
  641. .cra_priority = 300,
  642. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  643. CRYPTO_ALG_ASYNC |
  644. CRYPTO_ALG_NEED_FALLBACK,
  645. .cra_blocksize = 1,
  646. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  647. .cra_alignmask = 0x0f,
  648. .cra_module = THIS_MODULE,
  649. }
  650. }
  651. },
  652. {
  653. .alg.skcipher = {
  654. .ivsize = AES_BLOCK_SIZE,
  655. .min_keysize = AES_MIN_KEY_SIZE,
  656. .max_keysize = AES_MAX_KEY_SIZE,
  657. .setkey = aspeed_aes_setkey,
  658. .encrypt = aspeed_aes_ofb_encrypt,
  659. .decrypt = aspeed_aes_ofb_decrypt,
  660. .init = aspeed_crypto_cra_init,
  661. .exit = aspeed_crypto_cra_exit,
  662. .base = {
  663. .cra_name = "ofb(aes)",
  664. .cra_driver_name = "aspeed-ofb-aes",
  665. .cra_priority = 300,
  666. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  667. CRYPTO_ALG_ASYNC |
  668. CRYPTO_ALG_NEED_FALLBACK,
  669. .cra_blocksize = 1,
  670. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  671. .cra_alignmask = 0x0f,
  672. .cra_module = THIS_MODULE,
  673. }
  674. }
  675. },
  676. {
  677. .alg.skcipher = {
  678. .min_keysize = DES_KEY_SIZE,
  679. .max_keysize = DES_KEY_SIZE,
  680. .setkey = aspeed_des_setkey,
  681. .encrypt = aspeed_des_ecb_encrypt,
  682. .decrypt = aspeed_des_ecb_decrypt,
  683. .init = aspeed_crypto_cra_init,
  684. .exit = aspeed_crypto_cra_exit,
  685. .base = {
  686. .cra_name = "ecb(des)",
  687. .cra_driver_name = "aspeed-ecb-des",
  688. .cra_priority = 300,
  689. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  690. CRYPTO_ALG_ASYNC |
  691. CRYPTO_ALG_NEED_FALLBACK,
  692. .cra_blocksize = DES_BLOCK_SIZE,
  693. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  694. .cra_alignmask = 0x0f,
  695. .cra_module = THIS_MODULE,
  696. }
  697. }
  698. },
  699. {
  700. .alg.skcipher = {
  701. .ivsize = DES_BLOCK_SIZE,
  702. .min_keysize = DES_KEY_SIZE,
  703. .max_keysize = DES_KEY_SIZE,
  704. .setkey = aspeed_des_setkey,
  705. .encrypt = aspeed_des_cbc_encrypt,
  706. .decrypt = aspeed_des_cbc_decrypt,
  707. .init = aspeed_crypto_cra_init,
  708. .exit = aspeed_crypto_cra_exit,
  709. .base = {
  710. .cra_name = "cbc(des)",
  711. .cra_driver_name = "aspeed-cbc-des",
  712. .cra_priority = 300,
  713. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  714. CRYPTO_ALG_ASYNC |
  715. CRYPTO_ALG_NEED_FALLBACK,
  716. .cra_blocksize = DES_BLOCK_SIZE,
  717. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  718. .cra_alignmask = 0x0f,
  719. .cra_module = THIS_MODULE,
  720. }
  721. }
  722. },
  723. {
  724. .alg.skcipher = {
  725. .ivsize = DES_BLOCK_SIZE,
  726. .min_keysize = DES_KEY_SIZE,
  727. .max_keysize = DES_KEY_SIZE,
  728. .setkey = aspeed_des_setkey,
  729. .encrypt = aspeed_des_cfb_encrypt,
  730. .decrypt = aspeed_des_cfb_decrypt,
  731. .init = aspeed_crypto_cra_init,
  732. .exit = aspeed_crypto_cra_exit,
  733. .base = {
  734. .cra_name = "cfb(des)",
  735. .cra_driver_name = "aspeed-cfb-des",
  736. .cra_priority = 300,
  737. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  738. CRYPTO_ALG_ASYNC |
  739. CRYPTO_ALG_NEED_FALLBACK,
  740. .cra_blocksize = DES_BLOCK_SIZE,
  741. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  742. .cra_alignmask = 0x0f,
  743. .cra_module = THIS_MODULE,
  744. }
  745. }
  746. },
  747. {
  748. .alg.skcipher = {
  749. .ivsize = DES_BLOCK_SIZE,
  750. .min_keysize = DES_KEY_SIZE,
  751. .max_keysize = DES_KEY_SIZE,
  752. .setkey = aspeed_des_setkey,
  753. .encrypt = aspeed_des_ofb_encrypt,
  754. .decrypt = aspeed_des_ofb_decrypt,
  755. .init = aspeed_crypto_cra_init,
  756. .exit = aspeed_crypto_cra_exit,
  757. .base = {
  758. .cra_name = "ofb(des)",
  759. .cra_driver_name = "aspeed-ofb-des",
  760. .cra_priority = 300,
  761. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  762. CRYPTO_ALG_ASYNC |
  763. CRYPTO_ALG_NEED_FALLBACK,
  764. .cra_blocksize = DES_BLOCK_SIZE,
  765. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  766. .cra_alignmask = 0x0f,
  767. .cra_module = THIS_MODULE,
  768. }
  769. }
  770. },
  771. {
  772. .alg.skcipher = {
  773. .min_keysize = DES3_EDE_KEY_SIZE,
  774. .max_keysize = DES3_EDE_KEY_SIZE,
  775. .setkey = aspeed_des_setkey,
  776. .encrypt = aspeed_tdes_ecb_encrypt,
  777. .decrypt = aspeed_tdes_ecb_decrypt,
  778. .init = aspeed_crypto_cra_init,
  779. .exit = aspeed_crypto_cra_exit,
  780. .base = {
  781. .cra_name = "ecb(des3_ede)",
  782. .cra_driver_name = "aspeed-ecb-tdes",
  783. .cra_priority = 300,
  784. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  785. CRYPTO_ALG_ASYNC |
  786. CRYPTO_ALG_NEED_FALLBACK,
  787. .cra_blocksize = DES_BLOCK_SIZE,
  788. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  789. .cra_alignmask = 0x0f,
  790. .cra_module = THIS_MODULE,
  791. }
  792. }
  793. },
  794. {
  795. .alg.skcipher = {
  796. .ivsize = DES_BLOCK_SIZE,
  797. .min_keysize = DES3_EDE_KEY_SIZE,
  798. .max_keysize = DES3_EDE_KEY_SIZE,
  799. .setkey = aspeed_des_setkey,
  800. .encrypt = aspeed_tdes_cbc_encrypt,
  801. .decrypt = aspeed_tdes_cbc_decrypt,
  802. .init = aspeed_crypto_cra_init,
  803. .exit = aspeed_crypto_cra_exit,
  804. .base = {
  805. .cra_name = "cbc(des3_ede)",
  806. .cra_driver_name = "aspeed-cbc-tdes",
  807. .cra_priority = 300,
  808. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  809. CRYPTO_ALG_ASYNC |
  810. CRYPTO_ALG_NEED_FALLBACK,
  811. .cra_blocksize = DES_BLOCK_SIZE,
  812. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  813. .cra_alignmask = 0x0f,
  814. .cra_module = THIS_MODULE,
  815. }
  816. }
  817. },
  818. {
  819. .alg.skcipher = {
  820. .ivsize = DES_BLOCK_SIZE,
  821. .min_keysize = DES3_EDE_KEY_SIZE,
  822. .max_keysize = DES3_EDE_KEY_SIZE,
  823. .setkey = aspeed_des_setkey,
  824. .encrypt = aspeed_tdes_cfb_encrypt,
  825. .decrypt = aspeed_tdes_cfb_decrypt,
  826. .init = aspeed_crypto_cra_init,
  827. .exit = aspeed_crypto_cra_exit,
  828. .base = {
  829. .cra_name = "cfb(des3_ede)",
  830. .cra_driver_name = "aspeed-cfb-tdes",
  831. .cra_priority = 300,
  832. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  833. CRYPTO_ALG_ASYNC |
  834. CRYPTO_ALG_NEED_FALLBACK,
  835. .cra_blocksize = DES_BLOCK_SIZE,
  836. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  837. .cra_alignmask = 0x0f,
  838. .cra_module = THIS_MODULE,
  839. }
  840. }
  841. },
  842. {
  843. .alg.skcipher = {
  844. .ivsize = DES_BLOCK_SIZE,
  845. .min_keysize = DES3_EDE_KEY_SIZE,
  846. .max_keysize = DES3_EDE_KEY_SIZE,
  847. .setkey = aspeed_des_setkey,
  848. .encrypt = aspeed_tdes_ofb_encrypt,
  849. .decrypt = aspeed_tdes_ofb_decrypt,
  850. .init = aspeed_crypto_cra_init,
  851. .exit = aspeed_crypto_cra_exit,
  852. .base = {
  853. .cra_name = "ofb(des3_ede)",
  854. .cra_driver_name = "aspeed-ofb-tdes",
  855. .cra_priority = 300,
  856. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  857. CRYPTO_ALG_ASYNC |
  858. CRYPTO_ALG_NEED_FALLBACK,
  859. .cra_blocksize = DES_BLOCK_SIZE,
  860. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  861. .cra_alignmask = 0x0f,
  862. .cra_module = THIS_MODULE,
  863. }
  864. }
  865. },
  866. };
  867. static struct aspeed_hace_alg aspeed_crypto_algs_g6[] = {
  868. {
  869. .alg.skcipher = {
  870. .ivsize = AES_BLOCK_SIZE,
  871. .min_keysize = AES_MIN_KEY_SIZE,
  872. .max_keysize = AES_MAX_KEY_SIZE,
  873. .setkey = aspeed_aes_setkey,
  874. .encrypt = aspeed_aes_ctr_encrypt,
  875. .decrypt = aspeed_aes_ctr_decrypt,
  876. .init = aspeed_crypto_cra_init,
  877. .exit = aspeed_crypto_cra_exit,
  878. .base = {
  879. .cra_name = "ctr(aes)",
  880. .cra_driver_name = "aspeed-ctr-aes",
  881. .cra_priority = 300,
  882. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  883. CRYPTO_ALG_ASYNC,
  884. .cra_blocksize = 1,
  885. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  886. .cra_alignmask = 0x0f,
  887. .cra_module = THIS_MODULE,
  888. }
  889. }
  890. },
  891. {
  892. .alg.skcipher = {
  893. .ivsize = DES_BLOCK_SIZE,
  894. .min_keysize = DES_KEY_SIZE,
  895. .max_keysize = DES_KEY_SIZE,
  896. .setkey = aspeed_des_setkey,
  897. .encrypt = aspeed_des_ctr_encrypt,
  898. .decrypt = aspeed_des_ctr_decrypt,
  899. .init = aspeed_crypto_cra_init,
  900. .exit = aspeed_crypto_cra_exit,
  901. .base = {
  902. .cra_name = "ctr(des)",
  903. .cra_driver_name = "aspeed-ctr-des",
  904. .cra_priority = 300,
  905. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  906. CRYPTO_ALG_ASYNC,
  907. .cra_blocksize = 1,
  908. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  909. .cra_alignmask = 0x0f,
  910. .cra_module = THIS_MODULE,
  911. }
  912. }
  913. },
  914. {
  915. .alg.skcipher = {
  916. .ivsize = DES_BLOCK_SIZE,
  917. .min_keysize = DES3_EDE_KEY_SIZE,
  918. .max_keysize = DES3_EDE_KEY_SIZE,
  919. .setkey = aspeed_des_setkey,
  920. .encrypt = aspeed_tdes_ctr_encrypt,
  921. .decrypt = aspeed_tdes_ctr_decrypt,
  922. .init = aspeed_crypto_cra_init,
  923. .exit = aspeed_crypto_cra_exit,
  924. .base = {
  925. .cra_name = "ctr(des3_ede)",
  926. .cra_driver_name = "aspeed-ctr-tdes",
  927. .cra_priority = 300,
  928. .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
  929. CRYPTO_ALG_ASYNC,
  930. .cra_blocksize = 1,
  931. .cra_ctxsize = sizeof(struct aspeed_cipher_ctx),
  932. .cra_alignmask = 0x0f,
  933. .cra_module = THIS_MODULE,
  934. }
  935. }
  936. },
  937. };
  938. void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev)
  939. {
  940. int i;
  941. for (i = 0; i < ARRAY_SIZE(aspeed_crypto_algs); i++)
  942. crypto_unregister_skcipher(&aspeed_crypto_algs[i].alg.skcipher);
  943. if (hace_dev->version != AST2600_VERSION)
  944. return;
  945. for (i = 0; i < ARRAY_SIZE(aspeed_crypto_algs_g6); i++)
  946. crypto_unregister_skcipher(&aspeed_crypto_algs_g6[i].alg.skcipher);
  947. }
  948. void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev)
  949. {
  950. int rc, i;
  951. CIPHER_DBG(hace_dev, "\n");
  952. for (i = 0; i < ARRAY_SIZE(aspeed_crypto_algs); i++) {
  953. aspeed_crypto_algs[i].hace_dev = hace_dev;
  954. rc = crypto_register_skcipher(&aspeed_crypto_algs[i].alg.skcipher);
  955. if (rc) {
  956. CIPHER_DBG(hace_dev, "Failed to register %s\n",
  957. aspeed_crypto_algs[i].alg.skcipher.base.cra_name);
  958. }
  959. }
  960. if (hace_dev->version != AST2600_VERSION)
  961. return;
  962. for (i = 0; i < ARRAY_SIZE(aspeed_crypto_algs_g6); i++) {
  963. aspeed_crypto_algs_g6[i].hace_dev = hace_dev;
  964. rc = crypto_register_skcipher(&aspeed_crypto_algs_g6[i].alg.skcipher);
  965. if (rc) {
  966. CIPHER_DBG(hace_dev, "Failed to register %s\n",
  967. aspeed_crypto_algs_g6[i].alg.skcipher.base.cra_name);
  968. }
  969. }
  970. }