clk-uniphier-gate.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <[email protected]>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/device.h>
  8. #include <linux/regmap.h>
  9. #include "clk-uniphier.h"
  10. struct uniphier_clk_gate {
  11. struct clk_hw hw;
  12. struct regmap *regmap;
  13. unsigned int reg;
  14. unsigned int bit;
  15. };
  16. #define to_uniphier_clk_gate(_hw) \
  17. container_of(_hw, struct uniphier_clk_gate, hw)
  18. static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
  19. {
  20. struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
  21. return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
  22. enable ? BIT(gate->bit) : 0);
  23. }
  24. static int uniphier_clk_gate_enable(struct clk_hw *hw)
  25. {
  26. return uniphier_clk_gate_endisable(hw, 1);
  27. }
  28. static void uniphier_clk_gate_disable(struct clk_hw *hw)
  29. {
  30. if (uniphier_clk_gate_endisable(hw, 0) < 0)
  31. pr_warn("failed to disable clk\n");
  32. }
  33. static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
  34. {
  35. struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
  36. unsigned int val;
  37. if (regmap_read(gate->regmap, gate->reg, &val) < 0)
  38. pr_warn("is_enabled() may return wrong result\n");
  39. return !!(val & BIT(gate->bit));
  40. }
  41. static const struct clk_ops uniphier_clk_gate_ops = {
  42. .enable = uniphier_clk_gate_enable,
  43. .disable = uniphier_clk_gate_disable,
  44. .is_enabled = uniphier_clk_gate_is_enabled,
  45. };
  46. struct clk_hw *uniphier_clk_register_gate(struct device *dev,
  47. struct regmap *regmap,
  48. const char *name,
  49. const struct uniphier_clk_gate_data *data)
  50. {
  51. struct uniphier_clk_gate *gate;
  52. struct clk_init_data init;
  53. int ret;
  54. gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
  55. if (!gate)
  56. return ERR_PTR(-ENOMEM);
  57. init.name = name;
  58. init.ops = &uniphier_clk_gate_ops;
  59. init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
  60. init.parent_names = data->parent_name ? &data->parent_name : NULL;
  61. init.num_parents = data->parent_name ? 1 : 0;
  62. gate->regmap = regmap;
  63. gate->reg = data->reg;
  64. gate->bit = data->bit;
  65. gate->hw.init = &init;
  66. ret = devm_clk_hw_register(dev, &gate->hw);
  67. if (ret)
  68. return ERR_PTR(ret);
  69. return &gate->hw;
  70. }