ccu_mp.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 Maxime Ripard
  4. * Maxime Ripard <[email protected]>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include "ccu_gate.h"
  9. #include "ccu_mp.h"
  10. static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
  11. unsigned int max_m, unsigned int max_p,
  12. unsigned int *m, unsigned int *p)
  13. {
  14. unsigned long best_rate = 0;
  15. unsigned int best_m = 0, best_p = 0;
  16. unsigned int _m, _p;
  17. for (_p = 1; _p <= max_p; _p <<= 1) {
  18. for (_m = 1; _m <= max_m; _m++) {
  19. unsigned long tmp_rate = parent / _p / _m;
  20. if (tmp_rate > rate)
  21. continue;
  22. if ((rate - tmp_rate) < (rate - best_rate)) {
  23. best_rate = tmp_rate;
  24. best_m = _m;
  25. best_p = _p;
  26. }
  27. }
  28. }
  29. *m = best_m;
  30. *p = best_p;
  31. }
  32. static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
  33. unsigned long *parent,
  34. unsigned long rate,
  35. unsigned int max_m,
  36. unsigned int max_p)
  37. {
  38. unsigned long parent_rate_saved;
  39. unsigned long parent_rate, now;
  40. unsigned long best_rate = 0;
  41. unsigned int _m, _p, div;
  42. unsigned long maxdiv;
  43. parent_rate_saved = *parent;
  44. /*
  45. * The maximum divider we can use without overflowing
  46. * unsigned long in rate * m * p below
  47. */
  48. maxdiv = max_m * max_p;
  49. maxdiv = min(ULONG_MAX / rate, maxdiv);
  50. for (_p = 1; _p <= max_p; _p <<= 1) {
  51. for (_m = 1; _m <= max_m; _m++) {
  52. div = _m * _p;
  53. if (div > maxdiv)
  54. break;
  55. if (rate * div == parent_rate_saved) {
  56. /*
  57. * It's the most ideal case if the requested
  58. * rate can be divided from parent clock without
  59. * needing to change parent rate, so return the
  60. * divider immediately.
  61. */
  62. *parent = parent_rate_saved;
  63. return rate;
  64. }
  65. parent_rate = clk_hw_round_rate(hw, rate * div);
  66. now = parent_rate / div;
  67. if (now <= rate && now > best_rate) {
  68. best_rate = now;
  69. *parent = parent_rate;
  70. if (now == rate)
  71. return rate;
  72. }
  73. }
  74. }
  75. return best_rate;
  76. }
  77. static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
  78. struct clk_hw *hw,
  79. unsigned long *parent_rate,
  80. unsigned long rate,
  81. void *data)
  82. {
  83. struct ccu_mp *cmp = data;
  84. unsigned int max_m, max_p;
  85. unsigned int m, p;
  86. if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
  87. rate *= cmp->fixed_post_div;
  88. max_m = cmp->m.max ?: 1 << cmp->m.width;
  89. max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
  90. if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
  91. ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
  92. rate = *parent_rate / p / m;
  93. } else {
  94. rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
  95. max_m, max_p);
  96. }
  97. if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
  98. rate /= cmp->fixed_post_div;
  99. return rate;
  100. }
  101. static void ccu_mp_disable(struct clk_hw *hw)
  102. {
  103. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  104. return ccu_gate_helper_disable(&cmp->common, cmp->enable);
  105. }
  106. static int ccu_mp_enable(struct clk_hw *hw)
  107. {
  108. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  109. return ccu_gate_helper_enable(&cmp->common, cmp->enable);
  110. }
  111. static int ccu_mp_is_enabled(struct clk_hw *hw)
  112. {
  113. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  114. return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
  115. }
  116. static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
  117. unsigned long parent_rate)
  118. {
  119. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  120. unsigned long rate;
  121. unsigned int m, p;
  122. u32 reg;
  123. /* Adjust parent_rate according to pre-dividers */
  124. parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
  125. parent_rate);
  126. reg = readl(cmp->common.base + cmp->common.reg);
  127. m = reg >> cmp->m.shift;
  128. m &= (1 << cmp->m.width) - 1;
  129. m += cmp->m.offset;
  130. if (!m)
  131. m++;
  132. p = reg >> cmp->p.shift;
  133. p &= (1 << cmp->p.width) - 1;
  134. rate = (parent_rate >> p) / m;
  135. if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
  136. rate /= cmp->fixed_post_div;
  137. return rate;
  138. }
  139. static int ccu_mp_determine_rate(struct clk_hw *hw,
  140. struct clk_rate_request *req)
  141. {
  142. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  143. return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
  144. req, ccu_mp_round_rate, cmp);
  145. }
  146. static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
  147. unsigned long parent_rate)
  148. {
  149. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  150. unsigned long flags;
  151. unsigned int max_m, max_p;
  152. unsigned int m, p;
  153. u32 reg;
  154. /* Adjust parent_rate according to pre-dividers */
  155. parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
  156. parent_rate);
  157. max_m = cmp->m.max ?: 1 << cmp->m.width;
  158. max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
  159. /* Adjust target rate according to post-dividers */
  160. if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
  161. rate = rate * cmp->fixed_post_div;
  162. ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
  163. spin_lock_irqsave(cmp->common.lock, flags);
  164. reg = readl(cmp->common.base + cmp->common.reg);
  165. reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
  166. reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
  167. reg |= (m - cmp->m.offset) << cmp->m.shift;
  168. reg |= ilog2(p) << cmp->p.shift;
  169. writel(reg, cmp->common.base + cmp->common.reg);
  170. spin_unlock_irqrestore(cmp->common.lock, flags);
  171. return 0;
  172. }
  173. static u8 ccu_mp_get_parent(struct clk_hw *hw)
  174. {
  175. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  176. return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
  177. }
  178. static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
  179. {
  180. struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  181. return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
  182. }
  183. const struct clk_ops ccu_mp_ops = {
  184. .disable = ccu_mp_disable,
  185. .enable = ccu_mp_enable,
  186. .is_enabled = ccu_mp_is_enabled,
  187. .get_parent = ccu_mp_get_parent,
  188. .set_parent = ccu_mp_set_parent,
  189. .determine_rate = ccu_mp_determine_rate,
  190. .recalc_rate = ccu_mp_recalc_rate,
  191. .set_rate = ccu_mp_set_rate,
  192. };
  193. EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, SUNXI_CCU);
  194. /*
  195. * Support for MMC timing mode switching
  196. *
  197. * The MMC clocks on some SoCs support switching between old and
  198. * new timing modes. A platform specific API is provided to query
  199. * and set the timing mode on supported SoCs.
  200. *
  201. * In addition, a special class of ccu_mp_ops is provided, which
  202. * takes in to account the timing mode switch. When the new timing
  203. * mode is active, the clock output rate is halved. This new class
  204. * is a wrapper around the generic ccu_mp_ops. When clock rates
  205. * are passed through to ccu_mp_ops callbacks, they are doubled
  206. * if the new timing mode bit is set, to account for the post
  207. * divider. Conversely, when clock rates are passed back, they
  208. * are halved if the mode bit is set.
  209. */
  210. static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw,
  211. unsigned long parent_rate)
  212. {
  213. unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);
  214. struct ccu_common *cm = hw_to_ccu_common(hw);
  215. u32 val = readl(cm->base + cm->reg);
  216. if (val & CCU_MMC_NEW_TIMING_MODE)
  217. return rate / 2;
  218. return rate;
  219. }
  220. static int ccu_mp_mmc_determine_rate(struct clk_hw *hw,
  221. struct clk_rate_request *req)
  222. {
  223. struct ccu_common *cm = hw_to_ccu_common(hw);
  224. u32 val = readl(cm->base + cm->reg);
  225. int ret;
  226. /* adjust the requested clock rate */
  227. if (val & CCU_MMC_NEW_TIMING_MODE) {
  228. req->rate *= 2;
  229. req->min_rate *= 2;
  230. req->max_rate *= 2;
  231. }
  232. ret = ccu_mp_determine_rate(hw, req);
  233. /* re-adjust the requested clock rate back */
  234. if (val & CCU_MMC_NEW_TIMING_MODE) {
  235. req->rate /= 2;
  236. req->min_rate /= 2;
  237. req->max_rate /= 2;
  238. }
  239. return ret;
  240. }
  241. static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
  242. unsigned long parent_rate)
  243. {
  244. struct ccu_common *cm = hw_to_ccu_common(hw);
  245. u32 val = readl(cm->base + cm->reg);
  246. if (val & CCU_MMC_NEW_TIMING_MODE)
  247. rate *= 2;
  248. return ccu_mp_set_rate(hw, rate, parent_rate);
  249. }
  250. const struct clk_ops ccu_mp_mmc_ops = {
  251. .disable = ccu_mp_disable,
  252. .enable = ccu_mp_enable,
  253. .is_enabled = ccu_mp_is_enabled,
  254. .get_parent = ccu_mp_get_parent,
  255. .set_parent = ccu_mp_set_parent,
  256. .determine_rate = ccu_mp_mmc_determine_rate,
  257. .recalc_rate = ccu_mp_mmc_recalc_rate,
  258. .set_rate = ccu_mp_mmc_set_rate,
  259. };
  260. EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, SUNXI_CCU);