ccu-suniv-f1c100s.h 748 B

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 Icenowy Zheng <[email protected]>
  4. *
  5. */
  6. #ifndef _CCU_SUNIV_F1C100S_H_
  7. #define _CCU_SUNIV_F1C100S_H_
  8. #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
  9. #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
  10. #define CLK_PLL_CPU 0
  11. #define CLK_PLL_AUDIO_BASE 1
  12. #define CLK_PLL_AUDIO 2
  13. #define CLK_PLL_AUDIO_2X 3
  14. #define CLK_PLL_AUDIO_4X 4
  15. #define CLK_PLL_AUDIO_8X 5
  16. #define CLK_PLL_VIDEO 6
  17. #define CLK_PLL_VIDEO_2X 7
  18. #define CLK_PLL_VE 8
  19. #define CLK_PLL_DDR0 9
  20. #define CLK_PLL_PERIPH 10
  21. /* CPU clock is exported */
  22. #define CLK_AHB 12
  23. #define CLK_APB 13
  24. /* All bus gates, DRAM gates and mod clocks are exported */
  25. #define CLK_NUMBER (CLK_AVS + 1)
  26. #endif /* _CCU_SUNIV_F1C100S_H_ */