ccu-sun9i-a80.h 1008 B

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2016 Chen-Yu Tsai
  4. *
  5. * Chen-Yu Tsai <[email protected]>
  6. */
  7. #ifndef _CCU_SUN9I_A80_H_
  8. #define _CCU_SUN9I_A80_H_
  9. #include <dt-bindings/clock/sun9i-a80-ccu.h>
  10. #include <dt-bindings/reset/sun9i-a80-ccu.h>
  11. #define CLK_PLL_C0CPUX 0
  12. #define CLK_PLL_C1CPUX 1
  13. /* pll-audio and pll-periph0 are exported to the PRCM block */
  14. #define CLK_PLL_VE 4
  15. #define CLK_PLL_DDR 5
  16. #define CLK_PLL_VIDEO0 6
  17. #define CLK_PLL_VIDEO1 7
  18. #define CLK_PLL_GPU 8
  19. #define CLK_PLL_DE 9
  20. #define CLK_PLL_ISP 10
  21. #define CLK_PLL_PERIPH1 11
  22. /* The CPUX clocks are exported */
  23. #define CLK_ATB0 14
  24. #define CLK_AXI0 15
  25. #define CLK_ATB1 16
  26. #define CLK_AXI1 17
  27. #define CLK_GTBUS 18
  28. #define CLK_AHB0 19
  29. #define CLK_AHB1 20
  30. #define CLK_AHB2 21
  31. #define CLK_APB0 22
  32. #define CLK_APB1 23
  33. #define CLK_CCI400 24
  34. #define CLK_ATS 25
  35. #define CLK_TRACE 26
  36. /* module clocks and bus gates exported */
  37. #define CLK_NUMBER (CLK_BUS_UART5 + 1)
  38. #endif /* _CCU_SUN9I_A80_H_ */