ccu-sun9i-a80-usb.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include "ccu_common.h"
  10. #include "ccu_gate.h"
  11. #include "ccu_reset.h"
  12. #include "ccu-sun9i-a80-usb.h"
  13. static const struct clk_parent_data clk_parent_hosc[] = {
  14. { .fw_name = "hosc" },
  15. };
  16. static const struct clk_parent_data clk_parent_bus[] = {
  17. { .fw_name = "bus" },
  18. };
  19. static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
  20. static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
  21. static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
  22. static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
  23. static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
  24. static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
  25. static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0);
  26. static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0);
  27. static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0);
  28. static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0);
  29. static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0);
  30. static struct ccu_common *sun9i_a80_usb_clks[] = {
  31. &bus_hci0_clk.common,
  32. &usb_ohci0_clk.common,
  33. &bus_hci1_clk.common,
  34. &bus_hci2_clk.common,
  35. &usb_ohci2_clk.common,
  36. &usb0_phy_clk.common,
  37. &usb1_hsic_clk.common,
  38. &usb1_phy_clk.common,
  39. &usb2_hsic_clk.common,
  40. &usb2_phy_clk.common,
  41. &usb_hsic_clk.common,
  42. };
  43. static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
  44. .hws = {
  45. [CLK_BUS_HCI0] = &bus_hci0_clk.common.hw,
  46. [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
  47. [CLK_BUS_HCI1] = &bus_hci1_clk.common.hw,
  48. [CLK_BUS_HCI2] = &bus_hci2_clk.common.hw,
  49. [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
  50. [CLK_USB0_PHY] = &usb0_phy_clk.common.hw,
  51. [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
  52. [CLK_USB1_PHY] = &usb1_phy_clk.common.hw,
  53. [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
  54. [CLK_USB2_PHY] = &usb2_phy_clk.common.hw,
  55. [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
  56. },
  57. .num = CLK_NUMBER,
  58. };
  59. static struct ccu_reset_map sun9i_a80_usb_resets[] = {
  60. [RST_USB0_HCI] = { 0x0, BIT(17) },
  61. [RST_USB1_HCI] = { 0x0, BIT(18) },
  62. [RST_USB2_HCI] = { 0x0, BIT(19) },
  63. [RST_USB0_PHY] = { 0x4, BIT(17) },
  64. [RST_USB1_HSIC] = { 0x4, BIT(18) },
  65. [RST_USB1_PHY] = { 0x4, BIT(19) },
  66. [RST_USB2_HSIC] = { 0x4, BIT(20) },
  67. [RST_USB2_PHY] = { 0x4, BIT(21) },
  68. };
  69. static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
  70. .ccu_clks = sun9i_a80_usb_clks,
  71. .num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks),
  72. .hw_clks = &sun9i_a80_usb_hw_clks,
  73. .resets = sun9i_a80_usb_resets,
  74. .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets),
  75. };
  76. static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
  77. {
  78. struct clk *bus_clk;
  79. void __iomem *reg;
  80. int ret;
  81. reg = devm_platform_ioremap_resource(pdev, 0);
  82. if (IS_ERR(reg))
  83. return PTR_ERR(reg);
  84. bus_clk = devm_clk_get(&pdev->dev, "bus");
  85. if (IS_ERR(bus_clk))
  86. return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
  87. "Couldn't get bus clk\n");
  88. /* The bus clock needs to be enabled for us to access the registers */
  89. ret = clk_prepare_enable(bus_clk);
  90. if (ret) {
  91. dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
  92. return ret;
  93. }
  94. ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_usb_clk_desc);
  95. if (ret)
  96. goto err_disable_clk;
  97. return 0;
  98. err_disable_clk:
  99. clk_disable_unprepare(bus_clk);
  100. return ret;
  101. }
  102. static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
  103. { .compatible = "allwinner,sun9i-a80-usb-clks" },
  104. { }
  105. };
  106. static struct platform_driver sun9i_a80_usb_clk_driver = {
  107. .probe = sun9i_a80_usb_clk_probe,
  108. .driver = {
  109. .name = "sun9i-a80-usb-clks",
  110. .of_match_table = sun9i_a80_usb_clk_ids,
  111. },
  112. };
  113. module_platform_driver(sun9i_a80_usb_clk_driver);
  114. MODULE_IMPORT_NS(SUNXI_CCU);
  115. MODULE_LICENSE("GPL");