ccu-sun50i-a64.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2016 Maxime Ripard
  4. *
  5. * Maxime Ripard <[email protected]>
  6. */
  7. #ifndef _CCU_SUN50I_A64_H_
  8. #define _CCU_SUN50I_A64_H_
  9. #include <dt-bindings/clock/sun50i-a64-ccu.h>
  10. #include <dt-bindings/reset/sun50i-a64-ccu.h>
  11. #define CLK_OSC_12M 0
  12. #define CLK_PLL_CPUX 1
  13. #define CLK_PLL_AUDIO_BASE 2
  14. #define CLK_PLL_AUDIO 3
  15. #define CLK_PLL_AUDIO_2X 4
  16. #define CLK_PLL_AUDIO_4X 5
  17. #define CLK_PLL_AUDIO_8X 6
  18. /* PLL_VIDEO0 exported for HDMI PHY */
  19. #define CLK_PLL_VIDEO0_2X 8
  20. #define CLK_PLL_VE 9
  21. #define CLK_PLL_DDR0 10
  22. /* PLL_PERIPH0 exported for PRCM */
  23. #define CLK_PLL_PERIPH0_2X 12
  24. #define CLK_PLL_PERIPH1 13
  25. #define CLK_PLL_PERIPH1_2X 14
  26. #define CLK_PLL_VIDEO1 15
  27. #define CLK_PLL_GPU 16
  28. #define CLK_PLL_MIPI 17
  29. #define CLK_PLL_HSIC 18
  30. #define CLK_PLL_DE 19
  31. #define CLK_PLL_DDR1 20
  32. #define CLK_AXI 22
  33. #define CLK_APB 23
  34. #define CLK_AHB1 24
  35. #define CLK_APB1 25
  36. #define CLK_APB2 26
  37. #define CLK_AHB2 27
  38. /* All the bus gates are exported */
  39. /* The first bunch of module clocks are exported */
  40. #define CLK_USB_OHCI0_12M 90
  41. #define CLK_USB_OHCI1_12M 92
  42. /* All the DRAM gates are exported */
  43. /* And the DSI and GPU module clock is exported */
  44. #define CLK_NUMBER (CLK_GPU + 1)
  45. #endif /* _CCU_SUN50I_A64_H_ */