clk-px30.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
  4. * Author: Elaine Zhang<[email protected]>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/syscore_ops.h>
  11. #include <dt-bindings/clock/px30-cru.h>
  12. #include "clk.h"
  13. #define PX30_GRF_SOC_STATUS0 0x480
  14. enum px30_plls {
  15. apll, dpll, cpll, npll, apll_b_h, apll_b_l,
  16. };
  17. enum px30_pmu_plls {
  18. gpll,
  19. };
  20. static struct rockchip_pll_rate_table px30_pll_rates[] = {
  21. /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  22. RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  23. RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  24. RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  25. RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  26. RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  27. RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  28. RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  29. RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  30. RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  31. RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  32. RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  33. RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  34. RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  35. RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  36. RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  37. RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  38. RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  39. RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  40. RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  41. RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  42. RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  43. RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  44. RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
  45. RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
  46. RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
  47. RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
  48. RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
  49. RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
  50. RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
  51. RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
  52. RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  53. RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
  54. RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
  55. RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
  56. RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
  57. RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
  58. RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
  59. RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
  60. RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
  61. RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
  62. RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
  63. RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
  64. RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
  65. { /* sentinel */ },
  66. };
  67. #define PX30_DIV_ACLKM_MASK 0x7
  68. #define PX30_DIV_ACLKM_SHIFT 12
  69. #define PX30_DIV_PCLK_DBG_MASK 0xf
  70. #define PX30_DIV_PCLK_DBG_SHIFT 8
  71. #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \
  72. { \
  73. .reg = PX30_CLKSEL_CON(0), \
  74. .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
  75. PX30_DIV_ACLKM_SHIFT) | \
  76. HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
  77. PX30_DIV_PCLK_DBG_SHIFT), \
  78. }
  79. #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
  80. { \
  81. .prate = _prate, \
  82. .divs = { \
  83. PX30_CLKSEL0(_aclk_core, _pclk_dbg), \
  84. }, \
  85. }
  86. static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
  87. PX30_CPUCLK_RATE(1608000000, 1, 7),
  88. PX30_CPUCLK_RATE(1584000000, 1, 7),
  89. PX30_CPUCLK_RATE(1560000000, 1, 7),
  90. PX30_CPUCLK_RATE(1536000000, 1, 7),
  91. PX30_CPUCLK_RATE(1512000000, 1, 7),
  92. PX30_CPUCLK_RATE(1488000000, 1, 5),
  93. PX30_CPUCLK_RATE(1464000000, 1, 5),
  94. PX30_CPUCLK_RATE(1440000000, 1, 5),
  95. PX30_CPUCLK_RATE(1416000000, 1, 5),
  96. PX30_CPUCLK_RATE(1392000000, 1, 5),
  97. PX30_CPUCLK_RATE(1368000000, 1, 5),
  98. PX30_CPUCLK_RATE(1344000000, 1, 5),
  99. PX30_CPUCLK_RATE(1320000000, 1, 5),
  100. PX30_CPUCLK_RATE(1296000000, 1, 5),
  101. PX30_CPUCLK_RATE(1272000000, 1, 5),
  102. PX30_CPUCLK_RATE(1248000000, 1, 5),
  103. PX30_CPUCLK_RATE(1224000000, 1, 5),
  104. PX30_CPUCLK_RATE(1200000000, 1, 5),
  105. PX30_CPUCLK_RATE(1104000000, 1, 5),
  106. PX30_CPUCLK_RATE(1008000000, 1, 5),
  107. PX30_CPUCLK_RATE(912000000, 1, 5),
  108. PX30_CPUCLK_RATE(816000000, 1, 3),
  109. PX30_CPUCLK_RATE(696000000, 1, 3),
  110. PX30_CPUCLK_RATE(600000000, 1, 3),
  111. PX30_CPUCLK_RATE(408000000, 1, 1),
  112. PX30_CPUCLK_RATE(312000000, 1, 1),
  113. PX30_CPUCLK_RATE(216000000, 1, 1),
  114. PX30_CPUCLK_RATE(96000000, 1, 1),
  115. };
  116. static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
  117. .core_reg[0] = PX30_CLKSEL_CON(0),
  118. .div_core_shift[0] = 0,
  119. .div_core_mask[0] = 0xf,
  120. .num_cores = 1,
  121. .mux_core_alt = 1,
  122. .mux_core_main = 0,
  123. .mux_core_shift = 7,
  124. .mux_core_mask = 0x1,
  125. };
  126. PNAME(mux_pll_p) = { "xin24m"};
  127. PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
  128. PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
  129. PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
  130. PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
  131. PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
  132. PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
  133. PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
  134. PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
  135. PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
  136. PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
  137. PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
  138. PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
  139. PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
  140. PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
  141. PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
  142. PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
  143. PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
  144. PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
  145. PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
  146. PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
  147. PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"};
  148. PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"};
  149. PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
  150. PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
  151. PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
  152. PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
  153. PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
  154. PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
  155. PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
  156. PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
  157. PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
  158. PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
  159. PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
  160. PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
  161. PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
  162. PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
  163. PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
  164. PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
  165. PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
  166. PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
  167. PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
  168. PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
  169. PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
  170. PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
  171. PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" };
  172. static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
  173. [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
  174. 0, PX30_PLL_CON(0),
  175. PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
  176. [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
  177. 0, PX30_PLL_CON(8),
  178. PX30_MODE_CON, 4, 1, 0, NULL),
  179. [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
  180. 0, PX30_PLL_CON(16),
  181. PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
  182. [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
  183. 0, PX30_PLL_CON(24),
  184. PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
  185. };
  186. static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
  187. [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
  188. PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
  189. };
  190. #define MFLAGS CLK_MUX_HIWORD_MASK
  191. #define DFLAGS CLK_DIVIDER_HIWORD_MASK
  192. #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
  193. static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
  194. MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
  195. PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
  196. static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
  197. MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
  198. PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
  199. static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
  200. MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
  201. PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
  202. static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
  203. MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
  204. PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
  205. static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
  206. MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
  207. PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
  208. static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
  209. MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
  210. PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
  211. static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
  212. MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
  213. PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
  214. static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
  215. MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
  216. PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
  217. static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
  218. MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
  219. PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
  220. static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
  221. MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
  222. PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
  223. static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
  224. MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
  225. PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
  226. static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
  227. MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
  228. PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
  229. static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
  230. MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
  231. PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
  232. static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
  233. MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
  234. PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
  235. static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
  236. /*
  237. * Clock-Architecture Diagram 1
  238. */
  239. MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
  240. PX30_MODE_CON, 8, 2, MFLAGS),
  241. FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
  242. /*
  243. * Clock-Architecture Diagram 3
  244. */
  245. /* PD_CORE */
  246. GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
  247. PX30_CLKGATE_CON(0), 0, GFLAGS),
  248. GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
  249. PX30_CLKGATE_CON(0), 0, GFLAGS),
  250. COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
  251. PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
  252. PX30_CLKGATE_CON(0), 2, GFLAGS),
  253. COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
  254. PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
  255. PX30_CLKGATE_CON(0), 1, GFLAGS),
  256. GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
  257. PX30_CLKGATE_CON(0), 4, GFLAGS),
  258. GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
  259. PX30_CLKGATE_CON(17), 5, GFLAGS),
  260. GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
  261. PX30_CLKGATE_CON(0), 5, GFLAGS),
  262. GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
  263. PX30_CLKGATE_CON(0), 6, GFLAGS),
  264. GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
  265. PX30_CLKGATE_CON(17), 6, GFLAGS),
  266. GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
  267. PX30_CLKGATE_CON(0), 3, GFLAGS),
  268. GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
  269. PX30_CLKGATE_CON(17), 4, GFLAGS),
  270. /* PD_GPU */
  271. COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0,
  272. PX30_CLKSEL_CON(1), 6, 2, MFLAGS,
  273. PX30_CLKGATE_CON(0), 8, GFLAGS),
  274. COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0,
  275. PX30_CLKSEL_CON(1), 0, 4, DFLAGS,
  276. PX30_CLKGATE_CON(0), 12, GFLAGS),
  277. COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0,
  278. PX30_CLKSEL_CON(1), 8, 4, DFLAGS,
  279. PX30_CLKGATE_CON(0), 9, GFLAGS),
  280. COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT,
  281. PX30_CLKSEL_CON(1), 15, 1, MFLAGS,
  282. PX30_CLKGATE_CON(0), 10, GFLAGS),
  283. COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
  284. PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
  285. PX30_CLKGATE_CON(17), 10, GFLAGS),
  286. GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
  287. PX30_CLKGATE_CON(0), 11, GFLAGS),
  288. GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
  289. PX30_CLKGATE_CON(17), 8, GFLAGS),
  290. GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
  291. PX30_CLKGATE_CON(17), 9, GFLAGS),
  292. /*
  293. * Clock-Architecture Diagram 4
  294. */
  295. /* PD_DDR */
  296. GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
  297. PX30_CLKGATE_CON(0), 7, GFLAGS),
  298. GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
  299. PX30_CLKGATE_CON(0), 13, GFLAGS),
  300. COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED,
  301. PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
  302. COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
  303. PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
  304. FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
  305. PX30_CLKGATE_CON(0), 14, GFLAGS),
  306. FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
  307. PX30_CLKGATE_CON(1), 0, GFLAGS),
  308. COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
  309. PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
  310. PX30_CLKGATE_CON(1), 13, GFLAGS),
  311. GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  312. PX30_CLKGATE_CON(1), 15, GFLAGS),
  313. GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  314. PX30_CLKGATE_CON(1), 8, GFLAGS),
  315. GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  316. PX30_CLKGATE_CON(1), 5, GFLAGS),
  317. GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  318. PX30_CLKGATE_CON(1), 6, GFLAGS),
  319. GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  320. PX30_CLKGATE_CON(1), 6, GFLAGS),
  321. GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
  322. PX30_CLKGATE_CON(1), 11, GFLAGS),
  323. GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
  324. PX30_CLKGATE_CON(0), 15, GFLAGS),
  325. COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
  326. PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
  327. PX30_CLKGATE_CON(1), 1, GFLAGS),
  328. GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
  329. PX30_CLKGATE_CON(1), 10, GFLAGS),
  330. GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
  331. PX30_CLKGATE_CON(1), 7, GFLAGS),
  332. GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
  333. PX30_CLKGATE_CON(1), 9, GFLAGS),
  334. GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
  335. PX30_CLKGATE_CON(1), 12, GFLAGS),
  336. GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
  337. PX30_CLKGATE_CON(1), 14, GFLAGS),
  338. GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
  339. PX30_CLKGATE_CON(1), 3, GFLAGS),
  340. /*
  341. * Clock-Architecture Diagram 5
  342. */
  343. /* PD_VI */
  344. COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
  345. PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
  346. PX30_CLKGATE_CON(4), 8, GFLAGS),
  347. COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
  348. PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
  349. PX30_CLKGATE_CON(4), 12, GFLAGS),
  350. COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
  351. PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
  352. PX30_CLKGATE_CON(4), 9, GFLAGS),
  353. COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
  354. PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
  355. PX30_CLKGATE_CON(4), 11, GFLAGS),
  356. GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
  357. PX30_CLKGATE_CON(4), 13, GFLAGS),
  358. GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
  359. PX30_CLKGATE_CON(4), 14, GFLAGS),
  360. /*
  361. * Clock-Architecture Diagram 6
  362. */
  363. /* PD_VO */
  364. COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
  365. PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
  366. PX30_CLKGATE_CON(2), 0, GFLAGS),
  367. COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
  368. PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
  369. PX30_CLKGATE_CON(2), 12, GFLAGS),
  370. COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
  371. PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
  372. PX30_CLKGATE_CON(2), 13, GFLAGS),
  373. COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
  374. PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
  375. PX30_CLKGATE_CON(2), 1, GFLAGS),
  376. COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
  377. PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
  378. PX30_CLKGATE_CON(2), 5, GFLAGS),
  379. COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  380. PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
  381. PX30_CLKGATE_CON(2), 2, GFLAGS),
  382. COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
  383. PX30_CLKSEL_CON(6), 0,
  384. PX30_CLKGATE_CON(2), 3, GFLAGS,
  385. &px30_dclk_vopb_fracmux),
  386. GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
  387. PX30_CLKGATE_CON(2), 4, GFLAGS),
  388. COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
  389. PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
  390. PX30_CLKGATE_CON(2), 6, GFLAGS),
  391. COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
  392. PX30_CLKSEL_CON(9), 0,
  393. PX30_CLKGATE_CON(2), 7, GFLAGS,
  394. &px30_dclk_vopl_fracmux),
  395. GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
  396. PX30_CLKGATE_CON(2), 8, GFLAGS),
  397. /* PD_VPU */
  398. COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
  399. PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
  400. PX30_CLKGATE_CON(4), 0, GFLAGS),
  401. COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
  402. PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
  403. PX30_CLKGATE_CON(4), 2, GFLAGS),
  404. COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
  405. PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
  406. PX30_CLKGATE_CON(4), 1, GFLAGS),
  407. /*
  408. * Clock-Architecture Diagram 7
  409. */
  410. COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
  411. PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
  412. PX30_CLKGATE_CON(5), 7, GFLAGS),
  413. COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
  414. PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
  415. PX30_CLKGATE_CON(5), 8, GFLAGS),
  416. DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
  417. PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
  418. /* PD_MMC_NAND */
  419. GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
  420. PX30_CLKGATE_CON(6), 0, GFLAGS),
  421. COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
  422. PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
  423. PX30_CLKGATE_CON(5), 11, GFLAGS),
  424. COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
  425. PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
  426. PX30_CLKGATE_CON(5), 12, GFLAGS),
  427. COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
  428. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  429. PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
  430. PX30_CLKGATE_CON(5), 13, GFLAGS),
  431. COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
  432. PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
  433. PX30_CLKGATE_CON(6), 1, GFLAGS),
  434. COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
  435. mux_gpll_cpll_npll_xin24m_p, 0,
  436. PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
  437. PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
  438. PX30_CLKGATE_CON(6), 2, GFLAGS),
  439. COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
  440. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  441. PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
  442. PX30_CLKGATE_CON(6), 3, GFLAGS),
  443. COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
  444. PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
  445. PX30_CLKGATE_CON(6), 4, GFLAGS),
  446. COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
  447. PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
  448. PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
  449. PX30_CLKGATE_CON(6), 5, GFLAGS),
  450. COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
  451. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  452. PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
  453. PX30_CLKGATE_CON(6), 6, GFLAGS),
  454. COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
  455. PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
  456. PX30_CLKGATE_CON(6), 7, GFLAGS),
  457. MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
  458. PX30_SDMMC_CON0, 1),
  459. MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
  460. PX30_SDMMC_CON1, 1),
  461. MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
  462. PX30_SDIO_CON0, 1),
  463. MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
  464. PX30_SDIO_CON1, 1),
  465. MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
  466. PX30_EMMC_CON0, 1),
  467. MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
  468. PX30_EMMC_CON1, 1),
  469. /* PD_SDCARD */
  470. GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
  471. PX30_CLKGATE_CON(6), 12, GFLAGS),
  472. COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
  473. PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
  474. PX30_CLKGATE_CON(6), 13, GFLAGS),
  475. COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
  476. PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
  477. PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
  478. PX30_CLKGATE_CON(6), 14, GFLAGS),
  479. COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
  480. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  481. PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
  482. PX30_CLKGATE_CON(6), 15, GFLAGS),
  483. /* PD_USB */
  484. GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0,
  485. PX30_CLKGATE_CON(7), 2, GFLAGS),
  486. GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
  487. PX30_CLKGATE_CON(7), 3, GFLAGS),
  488. /* PD_GMAC */
  489. COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
  490. PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
  491. PX30_CLKGATE_CON(7), 11, GFLAGS),
  492. MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT,
  493. PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
  494. GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
  495. PX30_CLKGATE_CON(7), 15, GFLAGS),
  496. GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
  497. PX30_CLKGATE_CON(7), 13, GFLAGS),
  498. FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
  499. FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
  500. MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,
  501. PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
  502. GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
  503. PX30_CLKGATE_CON(7), 10, GFLAGS),
  504. COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
  505. PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
  506. PX30_CLKGATE_CON(7), 12, GFLAGS),
  507. COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
  508. PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
  509. PX30_CLKGATE_CON(8), 5, GFLAGS),
  510. /*
  511. * Clock-Architecture Diagram 8
  512. */
  513. /* PD_BUS */
  514. COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
  515. PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
  516. PX30_CLKGATE_CON(8), 6, GFLAGS),
  517. COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
  518. PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
  519. PX30_CLKGATE_CON(8), 8, GFLAGS),
  520. COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
  521. PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
  522. PX30_CLKGATE_CON(8), 7, GFLAGS),
  523. COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED,
  524. PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
  525. PX30_CLKGATE_CON(8), 9, GFLAGS),
  526. GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
  527. PX30_CLKGATE_CON(8), 10, GFLAGS),
  528. COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
  529. PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
  530. PX30_CLKGATE_CON(9), 9, GFLAGS),
  531. COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
  532. PX30_CLKSEL_CON(27), 0,
  533. PX30_CLKGATE_CON(9), 10, GFLAGS,
  534. &px30_pdm_fracmux),
  535. GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
  536. PX30_CLKGATE_CON(9), 11, GFLAGS),
  537. COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
  538. PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
  539. PX30_CLKGATE_CON(9), 12, GFLAGS),
  540. COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
  541. PX30_CLKSEL_CON(29), 0,
  542. PX30_CLKGATE_CON(9), 13, GFLAGS,
  543. &px30_i2s0_tx_fracmux),
  544. COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
  545. PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
  546. PX30_CLKGATE_CON(9), 14, GFLAGS),
  547. COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
  548. PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
  549. PX30_CLKGATE_CON(9), 15, GFLAGS),
  550. GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
  551. PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
  552. COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
  553. PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
  554. PX30_CLKGATE_CON(17), 0, GFLAGS),
  555. COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
  556. PX30_CLKSEL_CON(59), 0,
  557. PX30_CLKGATE_CON(17), 1, GFLAGS,
  558. &px30_i2s0_rx_fracmux),
  559. COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
  560. PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
  561. PX30_CLKGATE_CON(17), 2, GFLAGS),
  562. COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
  563. PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
  564. PX30_CLKGATE_CON(17), 3, GFLAGS),
  565. GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
  566. PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
  567. COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
  568. PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
  569. PX30_CLKGATE_CON(10), 0, GFLAGS),
  570. COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
  571. PX30_CLKSEL_CON(31), 0,
  572. PX30_CLKGATE_CON(10), 1, GFLAGS,
  573. &px30_i2s1_fracmux),
  574. GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
  575. PX30_CLKGATE_CON(10), 2, GFLAGS),
  576. COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
  577. PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
  578. PX30_CLKGATE_CON(10), 3, GFLAGS),
  579. GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
  580. PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
  581. COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
  582. PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
  583. PX30_CLKGATE_CON(10), 4, GFLAGS),
  584. COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
  585. PX30_CLKSEL_CON(33), 0,
  586. PX30_CLKGATE_CON(10), 5, GFLAGS,
  587. &px30_i2s2_fracmux),
  588. GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
  589. PX30_CLKGATE_CON(10), 6, GFLAGS),
  590. COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
  591. PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
  592. PX30_CLKGATE_CON(10), 7, GFLAGS),
  593. GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
  594. PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
  595. COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
  596. PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
  597. PX30_CLKGATE_CON(10), 12, GFLAGS),
  598. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
  599. PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
  600. PX30_CLKGATE_CON(10), 13, GFLAGS),
  601. COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
  602. PX30_CLKSEL_CON(36), 0,
  603. PX30_CLKGATE_CON(10), 14, GFLAGS,
  604. &px30_uart1_fracmux),
  605. GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
  606. PX30_CLKGATE_CON(10), 15, GFLAGS),
  607. COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
  608. PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
  609. PX30_CLKGATE_CON(11), 0, GFLAGS),
  610. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
  611. PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
  612. PX30_CLKGATE_CON(11), 1, GFLAGS),
  613. COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
  614. PX30_CLKSEL_CON(39), 0,
  615. PX30_CLKGATE_CON(11), 2, GFLAGS,
  616. &px30_uart2_fracmux),
  617. GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
  618. PX30_CLKGATE_CON(11), 3, GFLAGS),
  619. COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
  620. PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
  621. PX30_CLKGATE_CON(11), 4, GFLAGS),
  622. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
  623. PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
  624. PX30_CLKGATE_CON(11), 5, GFLAGS),
  625. COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
  626. PX30_CLKSEL_CON(42), 0,
  627. PX30_CLKGATE_CON(11), 6, GFLAGS,
  628. &px30_uart3_fracmux),
  629. GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
  630. PX30_CLKGATE_CON(11), 7, GFLAGS),
  631. COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
  632. PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
  633. PX30_CLKGATE_CON(11), 8, GFLAGS),
  634. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
  635. PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
  636. PX30_CLKGATE_CON(11), 9, GFLAGS),
  637. COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
  638. PX30_CLKSEL_CON(45), 0,
  639. PX30_CLKGATE_CON(11), 10, GFLAGS,
  640. &px30_uart4_fracmux),
  641. GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
  642. PX30_CLKGATE_CON(11), 11, GFLAGS),
  643. COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
  644. PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
  645. PX30_CLKGATE_CON(11), 12, GFLAGS),
  646. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
  647. PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
  648. PX30_CLKGATE_CON(11), 13, GFLAGS),
  649. COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
  650. PX30_CLKSEL_CON(48), 0,
  651. PX30_CLKGATE_CON(11), 14, GFLAGS,
  652. &px30_uart5_fracmux),
  653. GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
  654. PX30_CLKGATE_CON(11), 15, GFLAGS),
  655. COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
  656. PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
  657. PX30_CLKGATE_CON(12), 0, GFLAGS),
  658. COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
  659. PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
  660. PX30_CLKGATE_CON(12), 1, GFLAGS),
  661. COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
  662. PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
  663. PX30_CLKGATE_CON(12), 2, GFLAGS),
  664. COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
  665. PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
  666. PX30_CLKGATE_CON(12), 3, GFLAGS),
  667. COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
  668. PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
  669. PX30_CLKGATE_CON(12), 5, GFLAGS),
  670. COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
  671. PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
  672. PX30_CLKGATE_CON(12), 6, GFLAGS),
  673. COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
  674. PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
  675. PX30_CLKGATE_CON(12), 7, GFLAGS),
  676. COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
  677. PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
  678. PX30_CLKGATE_CON(12), 8, GFLAGS),
  679. GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
  680. PX30_CLKGATE_CON(13), 0, GFLAGS),
  681. GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
  682. PX30_CLKGATE_CON(13), 1, GFLAGS),
  683. GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
  684. PX30_CLKGATE_CON(13), 2, GFLAGS),
  685. GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
  686. PX30_CLKGATE_CON(13), 3, GFLAGS),
  687. GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
  688. PX30_CLKGATE_CON(13), 4, GFLAGS),
  689. GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
  690. PX30_CLKGATE_CON(13), 5, GFLAGS),
  691. COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
  692. PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
  693. PX30_CLKGATE_CON(12), 9, GFLAGS),
  694. COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
  695. PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
  696. PX30_CLKGATE_CON(12), 10, GFLAGS),
  697. COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
  698. PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
  699. PX30_CLKGATE_CON(12), 11, GFLAGS),
  700. COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
  701. PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
  702. PX30_CLKGATE_CON(13), 6, GFLAGS),
  703. GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
  704. PX30_CLKGATE_CON(12), 12, GFLAGS),
  705. /* PD_CRYPTO */
  706. GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
  707. PX30_CLKGATE_CON(8), 12, GFLAGS),
  708. GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
  709. PX30_CLKGATE_CON(8), 13, GFLAGS),
  710. COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
  711. PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
  712. PX30_CLKGATE_CON(8), 14, GFLAGS),
  713. COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
  714. PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
  715. PX30_CLKGATE_CON(8), 15, GFLAGS),
  716. /*
  717. * Clock-Architecture Diagram 9
  718. */
  719. /* PD_BUS_TOP */
  720. GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
  721. GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
  722. GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
  723. GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
  724. GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
  725. GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
  726. GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS),
  727. GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
  728. /* PD_VI */
  729. GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS),
  730. GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
  731. GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
  732. GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS),
  733. GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
  734. GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
  735. /* PD_VO */
  736. GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS),
  737. GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
  738. GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
  739. GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
  740. GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS),
  741. GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
  742. GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
  743. GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
  744. GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS),
  745. GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
  746. /* PD_BUS */
  747. GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
  748. GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
  749. GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
  750. GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
  751. /* aclk_dmac is controlled by sgrf_soc_con1[11]. */
  752. SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
  753. GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
  754. GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
  755. GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
  756. GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
  757. GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
  758. GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
  759. GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
  760. GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
  761. GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
  762. GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
  763. GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
  764. GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
  765. GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
  766. GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
  767. GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
  768. GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
  769. GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
  770. GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
  771. GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
  772. GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
  773. GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
  774. GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
  775. GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
  776. GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
  777. GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
  778. GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
  779. GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
  780. GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
  781. GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
  782. GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
  783. GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
  784. GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
  785. /* PD_VPU */
  786. GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
  787. GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
  788. GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
  789. GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
  790. /* PD_CRYPTO */
  791. GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
  792. GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
  793. GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
  794. GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
  795. /* PD_SDCARD */
  796. GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
  797. GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
  798. /* PD_PERI */
  799. GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS),
  800. /* PD_MMC_NAND */
  801. GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
  802. GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
  803. GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
  804. GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
  805. GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
  806. /* PD_USB */
  807. GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
  808. GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
  809. GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
  810. GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
  811. /* PD_GMAC */
  812. GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
  813. PX30_CLKGATE_CON(8), 0, GFLAGS),
  814. GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
  815. PX30_CLKGATE_CON(8), 2, GFLAGS),
  816. GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
  817. PX30_CLKGATE_CON(8), 1, GFLAGS),
  818. GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
  819. PX30_CLKGATE_CON(8), 3, GFLAGS),
  820. };
  821. static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
  822. /*
  823. * Clock-Architecture Diagram 2
  824. */
  825. COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
  826. PX30_PMU_CLKSEL_CON(1), 0,
  827. PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
  828. &px30_rtc32k_pmu_fracmux),
  829. COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
  830. PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
  831. PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
  832. COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
  833. PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
  834. PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
  835. COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
  836. PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
  837. PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
  838. COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
  839. PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
  840. PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
  841. COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
  842. PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
  843. PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
  844. COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
  845. PX30_PMU_CLKSEL_CON(5), 0,
  846. PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
  847. &px30_uart0_pmu_fracmux),
  848. GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
  849. PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
  850. GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
  851. PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
  852. COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
  853. PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
  854. PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
  855. COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
  856. PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
  857. PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
  858. COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
  859. PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
  860. PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
  861. COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
  862. PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
  863. PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
  864. /*
  865. * Clock-Architecture Diagram 9
  866. */
  867. /* PD_PMU */
  868. GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
  869. GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
  870. GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
  871. GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
  872. GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
  873. GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
  874. GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
  875. GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
  876. };
  877. static const char *const px30_cru_critical_clocks[] __initconst = {
  878. "aclk_bus_pre",
  879. "pclk_bus_pre",
  880. "hclk_bus_pre",
  881. "aclk_peri_pre",
  882. "hclk_peri_pre",
  883. "aclk_gpu_niu",
  884. "pclk_top_pre",
  885. "pclk_pmu_pre",
  886. "hclk_usb_niu",
  887. "pclk_vo_niu",
  888. "aclk_vo_niu",
  889. "hclk_vo_niu",
  890. "aclk_vi_niu",
  891. "hclk_vi_niu",
  892. "pll_npll",
  893. "usb480m",
  894. "clk_uart2",
  895. "pclk_uart2",
  896. "pclk_usb_grf",
  897. };
  898. static void __init px30_clk_init(struct device_node *np)
  899. {
  900. struct rockchip_clk_provider *ctx;
  901. void __iomem *reg_base;
  902. reg_base = of_iomap(np, 0);
  903. if (!reg_base) {
  904. pr_err("%s: could not map cru region\n", __func__);
  905. return;
  906. }
  907. ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
  908. if (IS_ERR(ctx)) {
  909. pr_err("%s: rockchip clk init failed\n", __func__);
  910. iounmap(reg_base);
  911. return;
  912. }
  913. rockchip_clk_register_plls(ctx, px30_pll_clks,
  914. ARRAY_SIZE(px30_pll_clks),
  915. PX30_GRF_SOC_STATUS0);
  916. rockchip_clk_register_branches(ctx, px30_clk_branches,
  917. ARRAY_SIZE(px30_clk_branches));
  918. rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
  919. mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
  920. &px30_cpuclk_data, px30_cpuclk_rates,
  921. ARRAY_SIZE(px30_cpuclk_rates));
  922. rockchip_clk_protect_critical(px30_cru_critical_clocks,
  923. ARRAY_SIZE(px30_cru_critical_clocks));
  924. rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
  925. ROCKCHIP_SOFTRST_HIWORD_MASK);
  926. rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
  927. rockchip_clk_of_add_provider(np, ctx);
  928. }
  929. CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
  930. static void __init px30_pmu_clk_init(struct device_node *np)
  931. {
  932. struct rockchip_clk_provider *ctx;
  933. void __iomem *reg_base;
  934. reg_base = of_iomap(np, 0);
  935. if (!reg_base) {
  936. pr_err("%s: could not map cru pmu region\n", __func__);
  937. return;
  938. }
  939. ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
  940. if (IS_ERR(ctx)) {
  941. pr_err("%s: rockchip pmu clk init failed\n", __func__);
  942. return;
  943. }
  944. rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
  945. ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
  946. rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
  947. ARRAY_SIZE(px30_clk_pmu_branches));
  948. rockchip_clk_of_add_provider(np, ctx);
  949. }
  950. CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);