reset.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022 MediaTek Inc.
  4. */
  5. #ifndef __DRV_CLK_MTK_RESET_H
  6. #define __DRV_CLK_MTK_RESET_H
  7. #include <linux/reset-controller.h>
  8. #include <linux/types.h>
  9. #define RST_NR_PER_BANK 32
  10. /* Infra global controller reset set register */
  11. #define INFRA_RST0_SET_OFFSET 0x120
  12. #define INFRA_RST1_SET_OFFSET 0x130
  13. #define INFRA_RST2_SET_OFFSET 0x140
  14. #define INFRA_RST3_SET_OFFSET 0x150
  15. #define INFRA_RST4_SET_OFFSET 0x730
  16. /**
  17. * enum mtk_reset_version - Version of MediaTek clock reset controller.
  18. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
  19. * @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
  20. * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
  21. */
  22. enum mtk_reset_version {
  23. MTK_RST_SIMPLE = 0,
  24. MTK_RST_SET_CLR,
  25. MTK_RST_MAX,
  26. };
  27. /**
  28. * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
  29. * @version: Reset version which is defined in enum mtk_reset_version.
  30. * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
  31. * @rst_bank_nr: Quantity of reset bank.
  32. * @rst_idx_map:Pointer to an array containing ids if input argument is index.
  33. * This array is not necessary if our input argument does not mean index.
  34. * @rst_idx_map_nr: Quantity of reset index map.
  35. */
  36. struct mtk_clk_rst_desc {
  37. enum mtk_reset_version version;
  38. u16 *rst_bank_ofs;
  39. u32 rst_bank_nr;
  40. u16 *rst_idx_map;
  41. u32 rst_idx_map_nr;
  42. };
  43. /**
  44. * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
  45. * @regmap: Pointer to base address of reset register address.
  46. * @rcdev: Reset controller device.
  47. * @desc: Pointer to description of the reset controller.
  48. */
  49. struct mtk_clk_rst_data {
  50. struct regmap *regmap;
  51. struct reset_controller_dev rcdev;
  52. const struct mtk_clk_rst_desc *desc;
  53. };
  54. /**
  55. * mtk_register_reset_controller - Register MediaTek clock reset controller
  56. * @np: Pointer to device node.
  57. * @desc: Constant pointer to description of clock reset.
  58. *
  59. * Return: 0 on success and errorno otherwise.
  60. */
  61. int mtk_register_reset_controller(struct device_node *np,
  62. const struct mtk_clk_rst_desc *desc);
  63. /**
  64. * mtk_register_reset_controller - Register mediatek clock reset controller with device
  65. * @np: Pointer to device.
  66. * @desc: Constant pointer to description of clock reset.
  67. *
  68. * Return: 0 on success and errorno otherwise.
  69. */
  70. int mtk_register_reset_controller_with_dev(struct device *dev,
  71. const struct mtk_clk_rst_desc *desc);
  72. #endif /* __DRV_CLK_MTK_RESET_H */