clk-pll.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: James Liao <[email protected]>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/container_of.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/slab.h>
  14. #include "clk-pll.h"
  15. #define MHZ (1000 * 1000)
  16. #define REG_CON0 0
  17. #define REG_CON1 4
  18. #define CON0_BASE_EN BIT(0)
  19. #define CON0_PWR_ON BIT(0)
  20. #define CON0_ISO_EN BIT(1)
  21. #define PCW_CHG_MASK BIT(31)
  22. #define AUDPLL_TUNER_EN BIT(31)
  23. #define POSTDIV_MASK 0x7
  24. /* default 7 bits integer, can be overridden with pcwibits. */
  25. #define INTEGER_BITS 7
  26. /*
  27. * MediaTek PLLs are configured through their pcw value. The pcw value describes
  28. * a divider in the PLL feedback loop which consists of 7 bits for the integer
  29. * part and the remaining bits (if present) for the fractional part. Also they
  30. * have a 3 bit power-of-two post divider.
  31. */
  32. struct mtk_clk_pll {
  33. struct clk_hw hw;
  34. void __iomem *base_addr;
  35. void __iomem *pd_addr;
  36. void __iomem *pwr_addr;
  37. void __iomem *tuner_addr;
  38. void __iomem *tuner_en_addr;
  39. void __iomem *pcw_addr;
  40. void __iomem *pcw_chg_addr;
  41. void __iomem *en_addr;
  42. const struct mtk_pll_data *data;
  43. };
  44. static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
  45. {
  46. return container_of(hw, struct mtk_clk_pll, hw);
  47. }
  48. static int mtk_pll_is_prepared(struct clk_hw *hw)
  49. {
  50. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  51. return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
  52. }
  53. static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
  54. u32 pcw, int postdiv)
  55. {
  56. int pcwbits = pll->data->pcwbits;
  57. int pcwfbits = 0;
  58. int ibits;
  59. u64 vco;
  60. u8 c = 0;
  61. /* The fractional part of the PLL divider. */
  62. ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
  63. if (pcwbits > ibits)
  64. pcwfbits = pcwbits - ibits;
  65. vco = (u64)fin * pcw;
  66. if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
  67. c = 1;
  68. vco >>= pcwfbits;
  69. if (c)
  70. vco++;
  71. return ((unsigned long)vco + postdiv - 1) / postdiv;
  72. }
  73. static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
  74. {
  75. u32 r;
  76. if (pll->tuner_en_addr) {
  77. r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
  78. writel(r, pll->tuner_en_addr);
  79. } else if (pll->tuner_addr) {
  80. r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
  81. writel(r, pll->tuner_addr);
  82. }
  83. }
  84. static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
  85. {
  86. u32 r;
  87. if (pll->tuner_en_addr) {
  88. r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
  89. writel(r, pll->tuner_en_addr);
  90. } else if (pll->tuner_addr) {
  91. r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
  92. writel(r, pll->tuner_addr);
  93. }
  94. }
  95. static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
  96. int postdiv)
  97. {
  98. u32 chg, val;
  99. /* disable tuner */
  100. __mtk_pll_tuner_disable(pll);
  101. /* set postdiv */
  102. val = readl(pll->pd_addr);
  103. val &= ~(POSTDIV_MASK << pll->data->pd_shift);
  104. val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
  105. /* postdiv and pcw need to set at the same time if on same register */
  106. if (pll->pd_addr != pll->pcw_addr) {
  107. writel(val, pll->pd_addr);
  108. val = readl(pll->pcw_addr);
  109. }
  110. /* set pcw */
  111. val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
  112. pll->data->pcw_shift);
  113. val |= pcw << pll->data->pcw_shift;
  114. writel(val, pll->pcw_addr);
  115. chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
  116. writel(chg, pll->pcw_chg_addr);
  117. if (pll->tuner_addr)
  118. writel(val + 1, pll->tuner_addr);
  119. /* restore tuner_en */
  120. __mtk_pll_tuner_enable(pll);
  121. udelay(20);
  122. }
  123. /*
  124. * mtk_pll_calc_values - calculate good values for a given input frequency.
  125. * @pll: The pll
  126. * @pcw: The pcw value (output)
  127. * @postdiv: The post divider (output)
  128. * @freq: The desired target frequency
  129. * @fin: The input frequency
  130. *
  131. */
  132. static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
  133. u32 freq, u32 fin)
  134. {
  135. unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
  136. const struct mtk_pll_div_table *div_table = pll->data->div_table;
  137. u64 _pcw;
  138. int ibits;
  139. u32 val;
  140. if (freq > pll->data->fmax)
  141. freq = pll->data->fmax;
  142. if (div_table) {
  143. if (freq > div_table[0].freq)
  144. freq = div_table[0].freq;
  145. for (val = 0; div_table[val + 1].freq != 0; val++) {
  146. if (freq > div_table[val + 1].freq)
  147. break;
  148. }
  149. *postdiv = 1 << val;
  150. } else {
  151. for (val = 0; val < 5; val++) {
  152. *postdiv = 1 << val;
  153. if ((u64)freq * *postdiv >= fmin)
  154. break;
  155. }
  156. }
  157. /* _pcw = freq * postdiv / fin * 2^pcwfbits */
  158. ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
  159. _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
  160. do_div(_pcw, fin);
  161. *pcw = (u32)_pcw;
  162. }
  163. static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  164. unsigned long parent_rate)
  165. {
  166. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  167. u32 pcw = 0;
  168. u32 postdiv;
  169. mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
  170. mtk_pll_set_rate_regs(pll, pcw, postdiv);
  171. return 0;
  172. }
  173. static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
  174. unsigned long parent_rate)
  175. {
  176. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  177. u32 postdiv;
  178. u32 pcw;
  179. postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
  180. postdiv = 1 << postdiv;
  181. pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
  182. pcw &= GENMASK(pll->data->pcwbits - 1, 0);
  183. return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
  184. }
  185. static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  186. unsigned long *prate)
  187. {
  188. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  189. u32 pcw = 0;
  190. int postdiv;
  191. mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
  192. return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
  193. }
  194. static int mtk_pll_prepare(struct clk_hw *hw)
  195. {
  196. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  197. u32 r;
  198. r = readl(pll->pwr_addr) | CON0_PWR_ON;
  199. writel(r, pll->pwr_addr);
  200. udelay(1);
  201. r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
  202. writel(r, pll->pwr_addr);
  203. udelay(1);
  204. r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
  205. writel(r, pll->en_addr);
  206. if (pll->data->en_mask) {
  207. r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
  208. writel(r, pll->base_addr + REG_CON0);
  209. }
  210. __mtk_pll_tuner_enable(pll);
  211. udelay(20);
  212. if (pll->data->flags & HAVE_RST_BAR) {
  213. r = readl(pll->base_addr + REG_CON0);
  214. r |= pll->data->rst_bar_mask;
  215. writel(r, pll->base_addr + REG_CON0);
  216. }
  217. return 0;
  218. }
  219. static void mtk_pll_unprepare(struct clk_hw *hw)
  220. {
  221. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  222. u32 r;
  223. if (pll->data->flags & HAVE_RST_BAR) {
  224. r = readl(pll->base_addr + REG_CON0);
  225. r &= ~pll->data->rst_bar_mask;
  226. writel(r, pll->base_addr + REG_CON0);
  227. }
  228. __mtk_pll_tuner_disable(pll);
  229. if (pll->data->en_mask) {
  230. r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
  231. writel(r, pll->base_addr + REG_CON0);
  232. }
  233. r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
  234. writel(r, pll->en_addr);
  235. r = readl(pll->pwr_addr) | CON0_ISO_EN;
  236. writel(r, pll->pwr_addr);
  237. r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
  238. writel(r, pll->pwr_addr);
  239. }
  240. static const struct clk_ops mtk_pll_ops = {
  241. .is_prepared = mtk_pll_is_prepared,
  242. .prepare = mtk_pll_prepare,
  243. .unprepare = mtk_pll_unprepare,
  244. .recalc_rate = mtk_pll_recalc_rate,
  245. .round_rate = mtk_pll_round_rate,
  246. .set_rate = mtk_pll_set_rate,
  247. };
  248. static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
  249. void __iomem *base)
  250. {
  251. struct mtk_clk_pll *pll;
  252. struct clk_init_data init = {};
  253. int ret;
  254. const char *parent_name = "clk26m";
  255. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  256. if (!pll)
  257. return ERR_PTR(-ENOMEM);
  258. pll->base_addr = base + data->reg;
  259. pll->pwr_addr = base + data->pwr_reg;
  260. pll->pd_addr = base + data->pd_reg;
  261. pll->pcw_addr = base + data->pcw_reg;
  262. if (data->pcw_chg_reg)
  263. pll->pcw_chg_addr = base + data->pcw_chg_reg;
  264. else
  265. pll->pcw_chg_addr = pll->base_addr + REG_CON1;
  266. if (data->tuner_reg)
  267. pll->tuner_addr = base + data->tuner_reg;
  268. if (data->tuner_en_reg || data->tuner_en_bit)
  269. pll->tuner_en_addr = base + data->tuner_en_reg;
  270. if (data->en_reg)
  271. pll->en_addr = base + data->en_reg;
  272. else
  273. pll->en_addr = pll->base_addr + REG_CON0;
  274. pll->hw.init = &init;
  275. pll->data = data;
  276. init.name = data->name;
  277. init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
  278. init.ops = &mtk_pll_ops;
  279. if (data->parent_name)
  280. init.parent_names = &data->parent_name;
  281. else
  282. init.parent_names = &parent_name;
  283. init.num_parents = 1;
  284. ret = clk_hw_register(NULL, &pll->hw);
  285. if (ret) {
  286. kfree(pll);
  287. return ERR_PTR(ret);
  288. }
  289. return &pll->hw;
  290. }
  291. static void mtk_clk_unregister_pll(struct clk_hw *hw)
  292. {
  293. struct mtk_clk_pll *pll;
  294. if (!hw)
  295. return;
  296. pll = to_mtk_clk_pll(hw);
  297. clk_hw_unregister(hw);
  298. kfree(pll);
  299. }
  300. int mtk_clk_register_plls(struct device_node *node,
  301. const struct mtk_pll_data *plls, int num_plls,
  302. struct clk_hw_onecell_data *clk_data)
  303. {
  304. void __iomem *base;
  305. int i;
  306. struct clk_hw *hw;
  307. base = of_iomap(node, 0);
  308. if (!base) {
  309. pr_err("%s(): ioremap failed\n", __func__);
  310. return -EINVAL;
  311. }
  312. for (i = 0; i < num_plls; i++) {
  313. const struct mtk_pll_data *pll = &plls[i];
  314. if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
  315. pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
  316. node, pll->id);
  317. continue;
  318. }
  319. hw = mtk_clk_register_pll(pll, base);
  320. if (IS_ERR(hw)) {
  321. pr_err("Failed to register clk %s: %pe\n", pll->name,
  322. hw);
  323. goto err;
  324. }
  325. clk_data->hws[pll->id] = hw;
  326. }
  327. return 0;
  328. err:
  329. while (--i >= 0) {
  330. const struct mtk_pll_data *pll = &plls[i];
  331. mtk_clk_unregister_pll(clk_data->hws[pll->id]);
  332. clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
  333. }
  334. iounmap(base);
  335. return PTR_ERR(hw);
  336. }
  337. EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
  338. static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
  339. const struct mtk_pll_data *data)
  340. {
  341. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  342. return pll->base_addr - data->reg;
  343. }
  344. void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
  345. struct clk_hw_onecell_data *clk_data)
  346. {
  347. __iomem void *base = NULL;
  348. int i;
  349. if (!clk_data)
  350. return;
  351. for (i = num_plls; i > 0; i--) {
  352. const struct mtk_pll_data *pll = &plls[i - 1];
  353. if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
  354. continue;
  355. /*
  356. * This is quite ugly but unfortunately the clks don't have
  357. * any device tied to them, so there's no place to store the
  358. * pointer to the I/O region base address. We have to fetch
  359. * it from one of the registered clks.
  360. */
  361. base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
  362. mtk_clk_unregister_pll(clk_data->hws[pll->id]);
  363. clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
  364. }
  365. iounmap(base);
  366. }
  367. EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);
  368. MODULE_LICENSE("GPL");