clk-mt8365-mfg.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2022 MediaTek Inc.
  4. */
  5. #include <dt-bindings/clock/mediatek,mt8365-clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-gate.h"
  9. #include "clk-mtk.h"
  10. static const struct mtk_gate_regs mfg0_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. static const struct mtk_gate_regs mfg1_cg_regs = {
  16. .set_ofs = 0x280,
  17. .clr_ofs = 0x280,
  18. .sta_ofs = 0x280,
  19. };
  20. #define GATE_MFG0(_id, _name, _parent, _shift) \
  21. GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \
  22. &mtk_clk_gate_ops_setclr)
  23. #define GATE_MFG1(_id, _name, _parent, _shift) \
  24. GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \
  25. &mtk_clk_gate_ops_no_setclr)
  26. static const struct mtk_gate mfg_clks[] = {
  27. /* MFG0 */
  28. GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
  29. /* MFG1 */
  30. GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24),
  31. };
  32. static const struct mtk_clk_desc mfg_desc = {
  33. .clks = mfg_clks,
  34. .num_clks = ARRAY_SIZE(mfg_clks),
  35. };
  36. static const struct of_device_id of_match_clk_mt8365_mfg[] = {
  37. {
  38. .compatible = "mediatek,mt8365-mfgcfg",
  39. .data = &mfg_desc,
  40. }, {
  41. /* sentinel */
  42. }
  43. };
  44. static struct platform_driver clk_mt8365_mfg_drv = {
  45. .probe = mtk_clk_simple_probe,
  46. .remove = mtk_clk_simple_remove,
  47. .driver = {
  48. .name = "clk-mt8365-mfg",
  49. .of_match_table = of_match_clk_mt8365_mfg,
  50. },
  51. };
  52. builtin_platform_driver(clk_mt8365_mfg_drv);
  53. MODULE_LICENSE("GPL");