clk-mt8365-apu.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2022 MediaTek Inc.
  4. */
  5. #include <dt-bindings/clock/mediatek,mt8365-clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-gate.h"
  9. #include "clk-mtk.h"
  10. static const struct mtk_gate_regs apu_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. #define GATE_APU(_id, _name, _parent, _shift) \
  16. GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \
  17. &mtk_clk_gate_ops_setclr)
  18. static const struct mtk_gate apu_clks[] = {
  19. GATE_APU(CLK_APU_AHB, "apu_ahb", "ifr_apu_axi", 5),
  20. GATE_APU(CLK_APU_EDMA, "apu_edma", "apu_sel", 4),
  21. GATE_APU(CLK_APU_IF_CK, "apu_if_ck", "apu_if_sel", 3),
  22. GATE_APU(CLK_APU_JTAG, "apu_jtag", "clk26m", 2),
  23. GATE_APU(CLK_APU_AXI, "apu_axi", "apu_sel", 1),
  24. GATE_APU(CLK_APU_IPU_CK, "apu_ck", "apu_sel", 0),
  25. };
  26. static const struct mtk_clk_desc apu_desc = {
  27. .clks = apu_clks,
  28. .num_clks = ARRAY_SIZE(apu_clks),
  29. };
  30. static const struct of_device_id of_match_clk_mt8365_apu[] = {
  31. {
  32. .compatible = "mediatek,mt8365-apu",
  33. .data = &apu_desc,
  34. }, {
  35. /* sentinel */
  36. }
  37. };
  38. static struct platform_driver clk_mt8365_apu_drv = {
  39. .probe = mtk_clk_simple_probe,
  40. .remove = mtk_clk_simple_remove,
  41. .driver = {
  42. .name = "clk-mt8365-apu",
  43. .of_match_table = of_match_clk_mt8365_apu,
  44. },
  45. };
  46. builtin_platform_driver(clk_mt8365_apu_drv);
  47. MODULE_LICENSE("GPL");