clk-mt8192-ipe.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright (c) 2021 MediaTek Inc.
  4. // Author: Chun-Jie Chen <[email protected]>
  5. #include <linux/clk-provider.h>
  6. #include <linux/of_device.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt8192-clk.h>
  11. static const struct mtk_gate_regs ipe_cg_regs = {
  12. .set_ofs = 0x4,
  13. .clr_ofs = 0x8,
  14. .sta_ofs = 0x0,
  15. };
  16. #define GATE_IPE(_id, _name, _parent, _shift) \
  17. GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  18. static const struct mtk_gate ipe_clks[] = {
  19. GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),
  20. GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),
  21. GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
  22. GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
  23. GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
  24. GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
  25. GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
  26. GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),
  27. };
  28. static const struct mtk_clk_desc ipe_desc = {
  29. .clks = ipe_clks,
  30. .num_clks = ARRAY_SIZE(ipe_clks),
  31. };
  32. static const struct of_device_id of_match_clk_mt8192_ipe[] = {
  33. {
  34. .compatible = "mediatek,mt8192-ipesys",
  35. .data = &ipe_desc,
  36. }, {
  37. /* sentinel */
  38. }
  39. };
  40. static struct platform_driver clk_mt8192_ipe_drv = {
  41. .probe = mtk_clk_simple_probe,
  42. .remove = mtk_clk_simple_remove,
  43. .driver = {
  44. .name = "clk-mt8192-ipe",
  45. .of_match_table = of_match_clk_mt8192_ipe,
  46. },
  47. };
  48. builtin_platform_driver(clk_mt8192_ipe_drv);