clk-gate.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: James Liao <[email protected]>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/mfd/syscon.h>
  8. #include <linux/module.h>
  9. #include <linux/printk.h>
  10. #include <linux/regmap.h>
  11. #include <linux/slab.h>
  12. #include <linux/types.h>
  13. #include "clk-gate.h"
  14. struct mtk_clk_gate {
  15. struct clk_hw hw;
  16. struct regmap *regmap;
  17. int set_ofs;
  18. int clr_ofs;
  19. int sta_ofs;
  20. u8 bit;
  21. };
  22. static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
  23. {
  24. return container_of(hw, struct mtk_clk_gate, hw);
  25. }
  26. static u32 mtk_get_clockgating(struct clk_hw *hw)
  27. {
  28. struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
  29. u32 val;
  30. regmap_read(cg->regmap, cg->sta_ofs, &val);
  31. return val & BIT(cg->bit);
  32. }
  33. static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
  34. {
  35. return mtk_get_clockgating(hw) == 0;
  36. }
  37. static int mtk_cg_bit_is_set(struct clk_hw *hw)
  38. {
  39. return mtk_get_clockgating(hw) != 0;
  40. }
  41. static void mtk_cg_set_bit(struct clk_hw *hw)
  42. {
  43. struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
  44. regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
  45. }
  46. static void mtk_cg_clr_bit(struct clk_hw *hw)
  47. {
  48. struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
  49. regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
  50. }
  51. static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
  52. {
  53. struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
  54. regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
  55. }
  56. static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
  57. {
  58. struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
  59. regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
  60. }
  61. static int mtk_cg_enable(struct clk_hw *hw)
  62. {
  63. mtk_cg_clr_bit(hw);
  64. return 0;
  65. }
  66. static void mtk_cg_disable(struct clk_hw *hw)
  67. {
  68. mtk_cg_set_bit(hw);
  69. }
  70. static int mtk_cg_enable_inv(struct clk_hw *hw)
  71. {
  72. mtk_cg_set_bit(hw);
  73. return 0;
  74. }
  75. static void mtk_cg_disable_inv(struct clk_hw *hw)
  76. {
  77. mtk_cg_clr_bit(hw);
  78. }
  79. static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
  80. {
  81. mtk_cg_clr_bit_no_setclr(hw);
  82. return 0;
  83. }
  84. static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
  85. {
  86. mtk_cg_set_bit_no_setclr(hw);
  87. }
  88. static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
  89. {
  90. mtk_cg_set_bit_no_setclr(hw);
  91. return 0;
  92. }
  93. static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
  94. {
  95. mtk_cg_clr_bit_no_setclr(hw);
  96. }
  97. const struct clk_ops mtk_clk_gate_ops_setclr = {
  98. .is_enabled = mtk_cg_bit_is_cleared,
  99. .enable = mtk_cg_enable,
  100. .disable = mtk_cg_disable,
  101. };
  102. EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
  103. const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
  104. .is_enabled = mtk_cg_bit_is_set,
  105. .enable = mtk_cg_enable_inv,
  106. .disable = mtk_cg_disable_inv,
  107. };
  108. EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
  109. const struct clk_ops mtk_clk_gate_ops_no_setclr = {
  110. .is_enabled = mtk_cg_bit_is_cleared,
  111. .enable = mtk_cg_enable_no_setclr,
  112. .disable = mtk_cg_disable_no_setclr,
  113. };
  114. EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
  115. const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
  116. .is_enabled = mtk_cg_bit_is_set,
  117. .enable = mtk_cg_enable_inv_no_setclr,
  118. .disable = mtk_cg_disable_inv_no_setclr,
  119. };
  120. EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
  121. static struct clk_hw *mtk_clk_register_gate(const char *name,
  122. const char *parent_name,
  123. struct regmap *regmap, int set_ofs,
  124. int clr_ofs, int sta_ofs, u8 bit,
  125. const struct clk_ops *ops,
  126. unsigned long flags, struct device *dev)
  127. {
  128. struct mtk_clk_gate *cg;
  129. int ret;
  130. struct clk_init_data init = {};
  131. cg = kzalloc(sizeof(*cg), GFP_KERNEL);
  132. if (!cg)
  133. return ERR_PTR(-ENOMEM);
  134. init.name = name;
  135. init.flags = flags | CLK_SET_RATE_PARENT;
  136. init.parent_names = parent_name ? &parent_name : NULL;
  137. init.num_parents = parent_name ? 1 : 0;
  138. init.ops = ops;
  139. cg->regmap = regmap;
  140. cg->set_ofs = set_ofs;
  141. cg->clr_ofs = clr_ofs;
  142. cg->sta_ofs = sta_ofs;
  143. cg->bit = bit;
  144. cg->hw.init = &init;
  145. ret = clk_hw_register(dev, &cg->hw);
  146. if (ret) {
  147. kfree(cg);
  148. return ERR_PTR(ret);
  149. }
  150. return &cg->hw;
  151. }
  152. static void mtk_clk_unregister_gate(struct clk_hw *hw)
  153. {
  154. struct mtk_clk_gate *cg;
  155. if (!hw)
  156. return;
  157. cg = to_mtk_clk_gate(hw);
  158. clk_hw_unregister(hw);
  159. kfree(cg);
  160. }
  161. int mtk_clk_register_gates_with_dev(struct device_node *node,
  162. const struct mtk_gate *clks, int num,
  163. struct clk_hw_onecell_data *clk_data,
  164. struct device *dev)
  165. {
  166. int i;
  167. struct clk_hw *hw;
  168. struct regmap *regmap;
  169. if (!clk_data)
  170. return -ENOMEM;
  171. regmap = device_node_to_regmap(node);
  172. if (IS_ERR(regmap)) {
  173. pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
  174. return PTR_ERR(regmap);
  175. }
  176. for (i = 0; i < num; i++) {
  177. const struct mtk_gate *gate = &clks[i];
  178. if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
  179. pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
  180. node, gate->id);
  181. continue;
  182. }
  183. hw = mtk_clk_register_gate(gate->name, gate->parent_name,
  184. regmap,
  185. gate->regs->set_ofs,
  186. gate->regs->clr_ofs,
  187. gate->regs->sta_ofs,
  188. gate->shift, gate->ops,
  189. gate->flags, dev);
  190. if (IS_ERR(hw)) {
  191. pr_err("Failed to register clk %s: %pe\n", gate->name,
  192. hw);
  193. goto err;
  194. }
  195. clk_data->hws[gate->id] = hw;
  196. }
  197. return 0;
  198. err:
  199. while (--i >= 0) {
  200. const struct mtk_gate *gate = &clks[i];
  201. if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
  202. continue;
  203. mtk_clk_unregister_gate(clk_data->hws[gate->id]);
  204. clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
  205. }
  206. return PTR_ERR(hw);
  207. }
  208. EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
  209. int mtk_clk_register_gates(struct device_node *node,
  210. const struct mtk_gate *clks, int num,
  211. struct clk_hw_onecell_data *clk_data)
  212. {
  213. return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
  214. }
  215. EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
  216. void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
  217. struct clk_hw_onecell_data *clk_data)
  218. {
  219. int i;
  220. if (!clk_data)
  221. return;
  222. for (i = num; i > 0; i--) {
  223. const struct mtk_gate *gate = &clks[i - 1];
  224. if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
  225. continue;
  226. mtk_clk_unregister_gate(clk_data->hws[gate->id]);
  227. clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
  228. }
  229. }
  230. EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);
  231. MODULE_LICENSE("GPL");