clk-clps711x.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Cirrus Logic CLPS711X CLK driver
  4. *
  5. * Copyright (C) 2014 Alexander Shiyan <[email protected]>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clkdev.h>
  9. #include <linux/io.h>
  10. #include <linux/ioport.h>
  11. #include <linux/of_address.h>
  12. #include <linux/slab.h>
  13. #include <linux/mfd/syscon/clps711x.h>
  14. #include <dt-bindings/clock/clps711x-clock.h>
  15. #define CLPS711X_SYSCON1 (0x0100)
  16. #define CLPS711X_SYSCON2 (0x1100)
  17. #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
  18. #define CLPS711X_PLLR (0xa5a8)
  19. #define CLPS711X_EXT_FREQ (13000000)
  20. #define CLPS711X_OSC_FREQ (3686400)
  21. static const struct clk_div_table spi_div_table[] = {
  22. { .val = 0, .div = 32, },
  23. { .val = 1, .div = 8, },
  24. { .val = 2, .div = 2, },
  25. { .val = 3, .div = 1, },
  26. { /* sentinel */ }
  27. };
  28. static const struct clk_div_table timer_div_table[] = {
  29. { .val = 0, .div = 256, },
  30. { .val = 1, .div = 1, },
  31. { /* sentinel */ }
  32. };
  33. struct clps711x_clk {
  34. spinlock_t lock;
  35. struct clk_hw_onecell_data clk_data;
  36. };
  37. static void __init clps711x_clk_init_dt(struct device_node *np)
  38. {
  39. u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
  40. struct clps711x_clk *clps711x_clk;
  41. void __iomem *base;
  42. WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
  43. base = of_iomap(np, 0);
  44. BUG_ON(!base);
  45. clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
  46. CLPS711X_CLK_MAX),
  47. GFP_KERNEL);
  48. BUG_ON(!clps711x_clk);
  49. spin_lock_init(&clps711x_clk->lock);
  50. /* Read PLL multiplier value and sanity check */
  51. tmp = readl(base + CLPS711X_PLLR) >> 24;
  52. if (((tmp >= 10) && (tmp <= 50)) || !fref)
  53. f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
  54. else
  55. f_pll = fref;
  56. tmp = readl(base + CLPS711X_SYSFLG2);
  57. if (tmp & SYSFLG2_CKMODE) {
  58. f_cpu = CLPS711X_EXT_FREQ;
  59. f_bus = CLPS711X_EXT_FREQ;
  60. f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
  61. f_pll = 0;
  62. f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
  63. } else {
  64. f_cpu = f_pll;
  65. if (f_cpu > 36864000)
  66. f_bus = DIV_ROUND_UP(f_cpu, 2);
  67. else
  68. f_bus = 36864000 / 2;
  69. f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
  70. f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
  71. }
  72. if (tmp & SYSFLG2_CKMODE) {
  73. if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
  74. f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
  75. else
  76. f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
  77. } else
  78. f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
  79. tmp = readl(base + CLPS711X_SYSCON1);
  80. /* Timer1 in free running mode.
  81. * Counter will wrap around to 0xffff when it underflows
  82. * and will continue to count down.
  83. */
  84. tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
  85. /* Timer2 in prescale mode.
  86. * Value writen is automatically re-loaded when
  87. * the counter underflows.
  88. */
  89. tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
  90. writel(tmp, base + CLPS711X_SYSCON1);
  91. clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
  92. clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
  93. clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
  94. clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
  95. clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
  96. clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
  97. clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
  98. clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
  99. clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
  100. clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
  101. clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
  102. clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
  103. base + CLPS711X_SYSCON1, 5, 1, 0,
  104. timer_div_table, &clps711x_clk->lock);
  105. clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
  106. clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
  107. base + CLPS711X_SYSCON1, 7, 1, 0,
  108. timer_div_table, &clps711x_clk->lock);
  109. clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
  110. clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
  111. clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
  112. clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
  113. clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
  114. clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
  115. base + CLPS711X_SYSCON1, 16, 2, 0,
  116. spi_div_table, &clps711x_clk->lock);
  117. clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
  118. clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
  119. clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
  120. clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
  121. for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
  122. if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
  123. pr_err("clk %i: register failed with %ld\n",
  124. tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
  125. clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
  126. of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
  127. &clps711x_clk->clk_data);
  128. }
  129. CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);