clk-utmi.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 Boris BREZILLON <[email protected]>
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/clkdev.h>
  7. #include <linux/clk/at91_pmc.h>
  8. #include <linux/of.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/regmap.h>
  11. #include <soc/at91/atmel-sfr.h>
  12. #include "pmc.h"
  13. /*
  14. * The purpose of this clock is to generate a 480 MHz signal. A different
  15. * rate can't be configured.
  16. */
  17. #define UTMI_RATE 480000000
  18. struct clk_utmi {
  19. struct clk_hw hw;
  20. struct regmap *regmap_pmc;
  21. struct regmap *regmap_sfr;
  22. struct at91_clk_pms pms;
  23. };
  24. #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
  25. static inline bool clk_utmi_ready(struct regmap *regmap)
  26. {
  27. unsigned int status;
  28. regmap_read(regmap, AT91_PMC_SR, &status);
  29. return status & AT91_PMC_LOCKU;
  30. }
  31. static int clk_utmi_prepare(struct clk_hw *hw)
  32. {
  33. struct clk_hw *hw_parent;
  34. struct clk_utmi *utmi = to_clk_utmi(hw);
  35. unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
  36. AT91_PMC_BIASEN;
  37. unsigned int utmi_ref_clk_freq;
  38. unsigned long parent_rate;
  39. /*
  40. * If mainck rate is different from 12 MHz, we have to configure the
  41. * FREQ field of the SFR_UTMICKTRIM register to generate properly
  42. * the utmi clock.
  43. */
  44. hw_parent = clk_hw_get_parent(hw);
  45. parent_rate = clk_hw_get_rate(hw_parent);
  46. switch (parent_rate) {
  47. case 12000000:
  48. utmi_ref_clk_freq = 0;
  49. break;
  50. case 16000000:
  51. utmi_ref_clk_freq = 1;
  52. break;
  53. case 24000000:
  54. utmi_ref_clk_freq = 2;
  55. break;
  56. /*
  57. * Not supported on SAMA5D2 but it's not an issue since MAINCK
  58. * maximum value is 24 MHz.
  59. */
  60. case 48000000:
  61. utmi_ref_clk_freq = 3;
  62. break;
  63. default:
  64. pr_err("UTMICK: unsupported mainck rate\n");
  65. return -EINVAL;
  66. }
  67. if (utmi->regmap_sfr) {
  68. regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
  69. AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
  70. } else if (utmi_ref_clk_freq) {
  71. pr_err("UTMICK: sfr node required\n");
  72. return -EINVAL;
  73. }
  74. regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
  75. while (!clk_utmi_ready(utmi->regmap_pmc))
  76. cpu_relax();
  77. return 0;
  78. }
  79. static int clk_utmi_is_prepared(struct clk_hw *hw)
  80. {
  81. struct clk_utmi *utmi = to_clk_utmi(hw);
  82. return clk_utmi_ready(utmi->regmap_pmc);
  83. }
  84. static void clk_utmi_unprepare(struct clk_hw *hw)
  85. {
  86. struct clk_utmi *utmi = to_clk_utmi(hw);
  87. regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
  88. AT91_PMC_UPLLEN, 0);
  89. }
  90. static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
  91. unsigned long parent_rate)
  92. {
  93. /* UTMI clk rate is fixed. */
  94. return UTMI_RATE;
  95. }
  96. static int clk_utmi_save_context(struct clk_hw *hw)
  97. {
  98. struct clk_utmi *utmi = to_clk_utmi(hw);
  99. utmi->pms.status = clk_utmi_is_prepared(hw);
  100. return 0;
  101. }
  102. static void clk_utmi_restore_context(struct clk_hw *hw)
  103. {
  104. struct clk_utmi *utmi = to_clk_utmi(hw);
  105. if (utmi->pms.status)
  106. clk_utmi_prepare(hw);
  107. }
  108. static const struct clk_ops utmi_ops = {
  109. .prepare = clk_utmi_prepare,
  110. .unprepare = clk_utmi_unprepare,
  111. .is_prepared = clk_utmi_is_prepared,
  112. .recalc_rate = clk_utmi_recalc_rate,
  113. .save_context = clk_utmi_save_context,
  114. .restore_context = clk_utmi_restore_context,
  115. };
  116. static struct clk_hw * __init
  117. at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
  118. struct regmap *regmap_sfr,
  119. const char *name, const char *parent_name,
  120. const struct clk_ops *ops, unsigned long flags)
  121. {
  122. struct clk_utmi *utmi;
  123. struct clk_hw *hw;
  124. struct clk_init_data init;
  125. int ret;
  126. utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
  127. if (!utmi)
  128. return ERR_PTR(-ENOMEM);
  129. init.name = name;
  130. init.ops = ops;
  131. init.parent_names = parent_name ? &parent_name : NULL;
  132. init.num_parents = parent_name ? 1 : 0;
  133. init.flags = flags;
  134. utmi->hw.init = &init;
  135. utmi->regmap_pmc = regmap_pmc;
  136. utmi->regmap_sfr = regmap_sfr;
  137. hw = &utmi->hw;
  138. ret = clk_hw_register(NULL, &utmi->hw);
  139. if (ret) {
  140. kfree(utmi);
  141. hw = ERR_PTR(ret);
  142. }
  143. return hw;
  144. }
  145. struct clk_hw * __init
  146. at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
  147. const char *name, const char *parent_name)
  148. {
  149. return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
  150. parent_name, &utmi_ops, CLK_SET_RATE_GATE);
  151. }
  152. static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
  153. {
  154. struct clk_utmi *utmi = to_clk_utmi(hw);
  155. struct clk_hw *hw_parent;
  156. unsigned long parent_rate;
  157. unsigned int val;
  158. hw_parent = clk_hw_get_parent(hw);
  159. parent_rate = clk_hw_get_rate(hw_parent);
  160. switch (parent_rate) {
  161. case 16000000:
  162. val = 0;
  163. break;
  164. case 20000000:
  165. val = 2;
  166. break;
  167. case 24000000:
  168. val = 3;
  169. break;
  170. case 32000000:
  171. val = 5;
  172. break;
  173. default:
  174. pr_err("UTMICK: unsupported main_xtal rate\n");
  175. return -EINVAL;
  176. }
  177. regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val);
  178. return 0;
  179. }
  180. static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw)
  181. {
  182. struct clk_utmi *utmi = to_clk_utmi(hw);
  183. struct clk_hw *hw_parent;
  184. unsigned long parent_rate;
  185. unsigned int val;
  186. hw_parent = clk_hw_get_parent(hw);
  187. parent_rate = clk_hw_get_rate(hw_parent);
  188. regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val);
  189. switch (val & 0x7) {
  190. case 0:
  191. if (parent_rate == 16000000)
  192. return 1;
  193. break;
  194. case 2:
  195. if (parent_rate == 20000000)
  196. return 1;
  197. break;
  198. case 3:
  199. if (parent_rate == 24000000)
  200. return 1;
  201. break;
  202. case 5:
  203. if (parent_rate == 32000000)
  204. return 1;
  205. break;
  206. default:
  207. break;
  208. }
  209. return 0;
  210. }
  211. static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
  212. {
  213. struct clk_utmi *utmi = to_clk_utmi(hw);
  214. utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
  215. return 0;
  216. }
  217. static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
  218. {
  219. struct clk_utmi *utmi = to_clk_utmi(hw);
  220. if (utmi->pms.status)
  221. clk_utmi_sama7g5_prepare(hw);
  222. }
  223. static const struct clk_ops sama7g5_utmi_ops = {
  224. .prepare = clk_utmi_sama7g5_prepare,
  225. .is_prepared = clk_utmi_sama7g5_is_prepared,
  226. .recalc_rate = clk_utmi_recalc_rate,
  227. .save_context = clk_utmi_sama7g5_save_context,
  228. .restore_context = clk_utmi_sama7g5_restore_context,
  229. };
  230. struct clk_hw * __init
  231. at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
  232. const char *parent_name)
  233. {
  234. return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
  235. parent_name, &sama7g5_utmi_ops, 0);
  236. }