brcmstb_gisb.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014-2021 Broadcom
  4. */
  5. #include <linux/init.h>
  6. #include <linux/types.h>
  7. #include <linux/module.h>
  8. #include <linux/panic_notifier.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/sysfs.h>
  12. #include <linux/io.h>
  13. #include <linux/string.h>
  14. #include <linux/device.h>
  15. #include <linux/list.h>
  16. #include <linux/of.h>
  17. #include <linux/bitops.h>
  18. #include <linux/pm.h>
  19. #include <linux/kernel.h>
  20. #include <linux/kdebug.h>
  21. #include <linux/notifier.h>
  22. #ifdef CONFIG_MIPS
  23. #include <asm/traps.h>
  24. #endif
  25. #define ARB_ERR_CAP_CLEAR (1 << 0)
  26. #define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
  27. #define ARB_ERR_CAP_STATUS_TEA (1 << 11)
  28. #define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
  29. #define ARB_ERR_CAP_STATUS_VALID (1 << 0)
  30. #define ARB_BP_CAP_CLEAR (1 << 0)
  31. #define ARB_BP_CAP_STATUS_PROT_SHIFT 14
  32. #define ARB_BP_CAP_STATUS_TYPE (1 << 13)
  33. #define ARB_BP_CAP_STATUS_RSP_SHIFT 10
  34. #define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)
  35. #define ARB_BP_CAP_STATUS_BS_SHIFT 2
  36. #define ARB_BP_CAP_STATUS_WRITE (1 << 1)
  37. #define ARB_BP_CAP_STATUS_VALID (1 << 0)
  38. enum {
  39. ARB_TIMER,
  40. ARB_BP_CAP_CLR,
  41. ARB_BP_CAP_HI_ADDR,
  42. ARB_BP_CAP_ADDR,
  43. ARB_BP_CAP_STATUS,
  44. ARB_BP_CAP_MASTER,
  45. ARB_ERR_CAP_CLR,
  46. ARB_ERR_CAP_HI_ADDR,
  47. ARB_ERR_CAP_ADDR,
  48. ARB_ERR_CAP_STATUS,
  49. ARB_ERR_CAP_MASTER,
  50. };
  51. static const int gisb_offsets_bcm7038[] = {
  52. [ARB_TIMER] = 0x00c,
  53. [ARB_BP_CAP_CLR] = 0x014,
  54. [ARB_BP_CAP_HI_ADDR] = -1,
  55. [ARB_BP_CAP_ADDR] = 0x0b8,
  56. [ARB_BP_CAP_STATUS] = 0x0c0,
  57. [ARB_BP_CAP_MASTER] = -1,
  58. [ARB_ERR_CAP_CLR] = 0x0c4,
  59. [ARB_ERR_CAP_HI_ADDR] = -1,
  60. [ARB_ERR_CAP_ADDR] = 0x0c8,
  61. [ARB_ERR_CAP_STATUS] = 0x0d0,
  62. [ARB_ERR_CAP_MASTER] = -1,
  63. };
  64. static const int gisb_offsets_bcm7278[] = {
  65. [ARB_TIMER] = 0x008,
  66. [ARB_BP_CAP_CLR] = 0x01c,
  67. [ARB_BP_CAP_HI_ADDR] = -1,
  68. [ARB_BP_CAP_ADDR] = 0x220,
  69. [ARB_BP_CAP_STATUS] = 0x230,
  70. [ARB_BP_CAP_MASTER] = 0x234,
  71. [ARB_ERR_CAP_CLR] = 0x7f8,
  72. [ARB_ERR_CAP_HI_ADDR] = -1,
  73. [ARB_ERR_CAP_ADDR] = 0x7e0,
  74. [ARB_ERR_CAP_STATUS] = 0x7f0,
  75. [ARB_ERR_CAP_MASTER] = 0x7f4,
  76. };
  77. static const int gisb_offsets_bcm7400[] = {
  78. [ARB_TIMER] = 0x00c,
  79. [ARB_BP_CAP_CLR] = 0x014,
  80. [ARB_BP_CAP_HI_ADDR] = -1,
  81. [ARB_BP_CAP_ADDR] = 0x0b8,
  82. [ARB_BP_CAP_STATUS] = 0x0c0,
  83. [ARB_BP_CAP_MASTER] = 0x0c4,
  84. [ARB_ERR_CAP_CLR] = 0x0c8,
  85. [ARB_ERR_CAP_HI_ADDR] = -1,
  86. [ARB_ERR_CAP_ADDR] = 0x0cc,
  87. [ARB_ERR_CAP_STATUS] = 0x0d4,
  88. [ARB_ERR_CAP_MASTER] = 0x0d8,
  89. };
  90. static const int gisb_offsets_bcm7435[] = {
  91. [ARB_TIMER] = 0x00c,
  92. [ARB_BP_CAP_CLR] = 0x014,
  93. [ARB_BP_CAP_HI_ADDR] = -1,
  94. [ARB_BP_CAP_ADDR] = 0x158,
  95. [ARB_BP_CAP_STATUS] = 0x160,
  96. [ARB_BP_CAP_MASTER] = 0x164,
  97. [ARB_ERR_CAP_CLR] = 0x168,
  98. [ARB_ERR_CAP_HI_ADDR] = -1,
  99. [ARB_ERR_CAP_ADDR] = 0x16c,
  100. [ARB_ERR_CAP_STATUS] = 0x174,
  101. [ARB_ERR_CAP_MASTER] = 0x178,
  102. };
  103. static const int gisb_offsets_bcm7445[] = {
  104. [ARB_TIMER] = 0x008,
  105. [ARB_BP_CAP_CLR] = 0x010,
  106. [ARB_BP_CAP_HI_ADDR] = -1,
  107. [ARB_BP_CAP_ADDR] = 0x1d8,
  108. [ARB_BP_CAP_STATUS] = 0x1e0,
  109. [ARB_BP_CAP_MASTER] = 0x1e4,
  110. [ARB_ERR_CAP_CLR] = 0x7e4,
  111. [ARB_ERR_CAP_HI_ADDR] = 0x7e8,
  112. [ARB_ERR_CAP_ADDR] = 0x7ec,
  113. [ARB_ERR_CAP_STATUS] = 0x7f4,
  114. [ARB_ERR_CAP_MASTER] = 0x7f8,
  115. };
  116. struct brcmstb_gisb_arb_device {
  117. void __iomem *base;
  118. const int *gisb_offsets;
  119. bool big_endian;
  120. struct mutex lock;
  121. struct list_head next;
  122. u32 valid_mask;
  123. const char *master_names[sizeof(u32) * BITS_PER_BYTE];
  124. u32 saved_timeout;
  125. };
  126. static LIST_HEAD(brcmstb_gisb_arb_device_list);
  127. static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
  128. {
  129. int offset = gdev->gisb_offsets[reg];
  130. if (offset < 0) {
  131. /* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
  132. if (reg == ARB_ERR_CAP_MASTER)
  133. return 1;
  134. else
  135. return 0;
  136. }
  137. if (gdev->big_endian)
  138. return ioread32be(gdev->base + offset);
  139. else
  140. return ioread32(gdev->base + offset);
  141. }
  142. static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
  143. {
  144. u64 value;
  145. value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
  146. value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
  147. return value;
  148. }
  149. static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
  150. {
  151. u64 value;
  152. value = gisb_read(gdev, ARB_BP_CAP_ADDR);
  153. value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
  154. return value;
  155. }
  156. static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
  157. {
  158. int offset = gdev->gisb_offsets[reg];
  159. if (offset == -1)
  160. return;
  161. if (gdev->big_endian)
  162. iowrite32be(val, gdev->base + offset);
  163. else
  164. iowrite32(val, gdev->base + offset);
  165. }
  166. static ssize_t gisb_arb_get_timeout(struct device *dev,
  167. struct device_attribute *attr,
  168. char *buf)
  169. {
  170. struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
  171. u32 timeout;
  172. mutex_lock(&gdev->lock);
  173. timeout = gisb_read(gdev, ARB_TIMER);
  174. mutex_unlock(&gdev->lock);
  175. return sprintf(buf, "%d", timeout);
  176. }
  177. static ssize_t gisb_arb_set_timeout(struct device *dev,
  178. struct device_attribute *attr,
  179. const char *buf, size_t count)
  180. {
  181. struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
  182. int val, ret;
  183. ret = kstrtoint(buf, 10, &val);
  184. if (ret < 0)
  185. return ret;
  186. if (val == 0 || val >= 0xffffffff)
  187. return -EINVAL;
  188. mutex_lock(&gdev->lock);
  189. gisb_write(gdev, val, ARB_TIMER);
  190. mutex_unlock(&gdev->lock);
  191. return count;
  192. }
  193. static const char *
  194. brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
  195. u32 masters)
  196. {
  197. u32 mask = gdev->valid_mask & masters;
  198. if (hweight_long(mask) != 1)
  199. return NULL;
  200. return gdev->master_names[ffs(mask) - 1];
  201. }
  202. static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
  203. const char *reason)
  204. {
  205. u32 cap_status;
  206. u64 arb_addr;
  207. u32 master;
  208. const char *m_name;
  209. char m_fmt[11];
  210. cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
  211. /* Invalid captured address, bail out */
  212. if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
  213. return 1;
  214. /* Read the address and master */
  215. arb_addr = gisb_read_address(gdev);
  216. master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
  217. m_name = brcmstb_gisb_master_to_str(gdev, master);
  218. if (!m_name) {
  219. snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
  220. m_name = m_fmt;
  221. }
  222. pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
  223. reason, arb_addr,
  224. cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
  225. cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
  226. m_name);
  227. /* clear the GISB error */
  228. gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
  229. return 0;
  230. }
  231. #ifdef CONFIG_MIPS
  232. static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
  233. {
  234. int ret = 0;
  235. struct brcmstb_gisb_arb_device *gdev;
  236. u32 cap_status;
  237. list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
  238. cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
  239. /* Invalid captured address, bail out */
  240. if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
  241. is_fixup = 1;
  242. goto out;
  243. }
  244. ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
  245. }
  246. out:
  247. return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  248. }
  249. #endif
  250. static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
  251. {
  252. brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
  253. return IRQ_HANDLED;
  254. }
  255. static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
  256. {
  257. brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
  258. return IRQ_HANDLED;
  259. }
  260. static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
  261. {
  262. struct brcmstb_gisb_arb_device *gdev = dev_id;
  263. const char *m_name;
  264. u32 bp_status;
  265. u64 arb_addr;
  266. u32 master;
  267. char m_fmt[11];
  268. bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
  269. /* Invalid captured address, bail out */
  270. if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
  271. return IRQ_HANDLED;
  272. /* Read the address and master */
  273. arb_addr = gisb_read_bp_address(gdev);
  274. master = gisb_read(gdev, ARB_BP_CAP_MASTER);
  275. m_name = brcmstb_gisb_master_to_str(gdev, master);
  276. if (!m_name) {
  277. snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
  278. m_name = m_fmt;
  279. }
  280. pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
  281. arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
  282. m_name);
  283. /* clear the GISB error */
  284. gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
  285. return IRQ_HANDLED;
  286. }
  287. /*
  288. * Dump out gisb errors on die or panic.
  289. */
  290. static int dump_gisb_error(struct notifier_block *self, unsigned long v,
  291. void *p);
  292. static struct notifier_block gisb_die_notifier = {
  293. .notifier_call = dump_gisb_error,
  294. };
  295. static struct notifier_block gisb_panic_notifier = {
  296. .notifier_call = dump_gisb_error,
  297. };
  298. static int dump_gisb_error(struct notifier_block *self, unsigned long v,
  299. void *p)
  300. {
  301. struct brcmstb_gisb_arb_device *gdev;
  302. const char *reason = "panic";
  303. if (self == &gisb_die_notifier)
  304. reason = "die";
  305. /* iterate over each GISB arb registered handlers */
  306. list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
  307. brcmstb_gisb_arb_decode_addr(gdev, reason);
  308. return NOTIFY_DONE;
  309. }
  310. static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
  311. gisb_arb_get_timeout, gisb_arb_set_timeout);
  312. static struct attribute *gisb_arb_sysfs_attrs[] = {
  313. &dev_attr_gisb_arb_timeout.attr,
  314. NULL,
  315. };
  316. static struct attribute_group gisb_arb_sysfs_attr_group = {
  317. .attrs = gisb_arb_sysfs_attrs,
  318. };
  319. static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
  320. { .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
  321. { .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
  322. { .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
  323. { .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
  324. { .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
  325. { .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
  326. { },
  327. };
  328. static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
  329. {
  330. struct device_node *dn = pdev->dev.of_node;
  331. struct brcmstb_gisb_arb_device *gdev;
  332. const struct of_device_id *of_id;
  333. struct resource *r;
  334. int err, timeout_irq, tea_irq, bp_irq;
  335. unsigned int num_masters, j = 0;
  336. int i, first, last;
  337. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. timeout_irq = platform_get_irq(pdev, 0);
  339. tea_irq = platform_get_irq(pdev, 1);
  340. bp_irq = platform_get_irq(pdev, 2);
  341. gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
  342. if (!gdev)
  343. return -ENOMEM;
  344. mutex_init(&gdev->lock);
  345. INIT_LIST_HEAD(&gdev->next);
  346. gdev->base = devm_ioremap_resource(&pdev->dev, r);
  347. if (IS_ERR(gdev->base))
  348. return PTR_ERR(gdev->base);
  349. of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
  350. if (!of_id) {
  351. pr_err("failed to look up compatible string\n");
  352. return -EINVAL;
  353. }
  354. gdev->gisb_offsets = of_id->data;
  355. gdev->big_endian = of_device_is_big_endian(dn);
  356. err = devm_request_irq(&pdev->dev, timeout_irq,
  357. brcmstb_gisb_timeout_handler, 0, pdev->name,
  358. gdev);
  359. if (err < 0)
  360. return err;
  361. err = devm_request_irq(&pdev->dev, tea_irq,
  362. brcmstb_gisb_tea_handler, 0, pdev->name,
  363. gdev);
  364. if (err < 0)
  365. return err;
  366. /* Interrupt is optional */
  367. if (bp_irq > 0) {
  368. err = devm_request_irq(&pdev->dev, bp_irq,
  369. brcmstb_gisb_bp_handler, 0, pdev->name,
  370. gdev);
  371. if (err < 0)
  372. return err;
  373. }
  374. /* If we do not have a valid mask, assume all masters are enabled */
  375. if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
  376. &gdev->valid_mask))
  377. gdev->valid_mask = 0xffffffff;
  378. /* Proceed with reading the litteral names if we agree on the
  379. * number of masters
  380. */
  381. num_masters = of_property_count_strings(dn,
  382. "brcm,gisb-arb-master-names");
  383. if (hweight_long(gdev->valid_mask) == num_masters) {
  384. first = ffs(gdev->valid_mask) - 1;
  385. last = fls(gdev->valid_mask) - 1;
  386. for (i = first; i < last; i++) {
  387. if (!(gdev->valid_mask & BIT(i)))
  388. continue;
  389. of_property_read_string_index(dn,
  390. "brcm,gisb-arb-master-names", j,
  391. &gdev->master_names[i]);
  392. j++;
  393. }
  394. }
  395. err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
  396. if (err)
  397. return err;
  398. platform_set_drvdata(pdev, gdev);
  399. list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
  400. #ifdef CONFIG_MIPS
  401. mips_set_be_handler(brcmstb_bus_error_handler);
  402. #endif
  403. if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
  404. register_die_notifier(&gisb_die_notifier);
  405. atomic_notifier_chain_register(&panic_notifier_list,
  406. &gisb_panic_notifier);
  407. }
  408. dev_info(&pdev->dev, "registered irqs: %d, %d\n",
  409. timeout_irq, tea_irq);
  410. return 0;
  411. }
  412. #ifdef CONFIG_PM_SLEEP
  413. static int brcmstb_gisb_arb_suspend(struct device *dev)
  414. {
  415. struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
  416. gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
  417. return 0;
  418. }
  419. /* Make sure we provide the same timeout value that was configured before, and
  420. * do this before the GISB timeout interrupt handler has any chance to run.
  421. */
  422. static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
  423. {
  424. struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
  425. gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
  426. return 0;
  427. }
  428. #else
  429. #define brcmstb_gisb_arb_suspend NULL
  430. #define brcmstb_gisb_arb_resume_noirq NULL
  431. #endif
  432. static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
  433. .suspend = brcmstb_gisb_arb_suspend,
  434. .resume_noirq = brcmstb_gisb_arb_resume_noirq,
  435. };
  436. static struct platform_driver brcmstb_gisb_arb_driver = {
  437. .driver = {
  438. .name = "brcm-gisb-arb",
  439. .of_match_table = brcmstb_gisb_arb_of_match,
  440. .pm = &brcmstb_gisb_arb_pm_ops,
  441. },
  442. };
  443. static int __init brcm_gisb_driver_init(void)
  444. {
  445. return platform_driver_probe(&brcmstb_gisb_arb_driver,
  446. brcmstb_gisb_arb_probe);
  447. }
  448. module_init(brcm_gisb_driver_init);
  449. MODULE_AUTHOR("Broadcom");
  450. MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
  451. MODULE_LICENSE("GPL v2");