pata_mpc52xx.c 25 KB

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  1. /*
  2. * drivers/ata/pata_mpc52xx.c
  3. *
  4. * libata driver for the Freescale MPC52xx on-chip IDE interface
  5. *
  6. * Copyright (C) 2006 Sylvain Munaut <[email protected]>
  7. * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
  8. *
  9. * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
  10. * Domen Puncer and Tim Yamin.
  11. *
  12. * This file is licensed under the terms of the GNU General Public License
  13. * version 2. This program is licensed "as is" without any warranty of any
  14. * kind, whether express or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/gfp.h>
  19. #include <linux/delay.h>
  20. #include <linux/libata.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/types.h>
  25. #include <asm/cacheflush.h>
  26. #include <asm/mpc52xx.h>
  27. #include <linux/fsl/bestcomm/bestcomm.h>
  28. #include <linux/fsl/bestcomm/bestcomm_priv.h>
  29. #include <linux/fsl/bestcomm/ata.h>
  30. #define DRV_NAME "mpc52xx_ata"
  31. /* Private structures used by the driver */
  32. struct mpc52xx_ata_timings {
  33. u32 pio1;
  34. u32 pio2;
  35. u32 mdma1;
  36. u32 mdma2;
  37. u32 udma1;
  38. u32 udma2;
  39. u32 udma3;
  40. u32 udma4;
  41. u32 udma5;
  42. int using_udma;
  43. };
  44. struct mpc52xx_ata_priv {
  45. unsigned int ipb_period;
  46. struct mpc52xx_ata __iomem *ata_regs;
  47. phys_addr_t ata_regs_pa;
  48. int ata_irq;
  49. struct mpc52xx_ata_timings timings[2];
  50. int csel;
  51. /* DMA */
  52. struct bcom_task *dmatsk;
  53. const struct udmaspec *udmaspec;
  54. const struct mdmaspec *mdmaspec;
  55. int mpc52xx_ata_dma_last_write;
  56. int waiting_for_dma;
  57. };
  58. /* ATAPI-4 PIO specs (in ns) */
  59. static const u16 ataspec_t0[5] = {600, 383, 240, 180, 120};
  60. static const u16 ataspec_t1[5] = { 70, 50, 30, 30, 25};
  61. static const u16 ataspec_t2_8[5] = {290, 290, 290, 80, 70};
  62. static const u16 ataspec_t2_16[5] = {165, 125, 100, 80, 70};
  63. static const u16 ataspec_t2i[5] = { 0, 0, 0, 70, 25};
  64. static const u16 ataspec_t4[5] = { 30, 20, 15, 10, 10};
  65. static const u16 ataspec_ta[5] = { 35, 35, 35, 35, 35};
  66. #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
  67. /* ======================================================================== */
  68. /* ATAPI-4 MDMA specs (in clocks) */
  69. struct mdmaspec {
  70. u8 t0M;
  71. u8 td;
  72. u8 th;
  73. u8 tj;
  74. u8 tkw;
  75. u8 tm;
  76. u8 tn;
  77. };
  78. static const struct mdmaspec mdmaspec66[3] = {
  79. { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 },
  80. { .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 },
  81. { .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 },
  82. };
  83. static const struct mdmaspec mdmaspec132[3] = {
  84. { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 },
  85. { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 },
  86. { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 },
  87. };
  88. /* ATAPI-4 UDMA specs (in clocks) */
  89. struct udmaspec {
  90. u8 tcyc;
  91. u8 t2cyc;
  92. u8 tds;
  93. u8 tdh;
  94. u8 tdvs;
  95. u8 tdvh;
  96. u8 tfs;
  97. u8 tli;
  98. u8 tmli;
  99. u8 taz;
  100. u8 tzah;
  101. u8 tenv;
  102. u8 tsr;
  103. u8 trfs;
  104. u8 trp;
  105. u8 tack;
  106. u8 tss;
  107. };
  108. static const struct udmaspec udmaspec66[6] = {
  109. { .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
  110. .tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  111. .tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4,
  112. },
  113. { .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1,
  114. .tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  115. .tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4,
  116. },
  117. { .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
  118. .tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  119. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  120. },
  121. { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1,
  122. .tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  123. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  124. },
  125. { .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  126. .tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  127. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  128. },
  129. { .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  130. .tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  131. .tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4,
  132. },
  133. };
  134. static const struct udmaspec udmaspec132[6] = {
  135. { .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1,
  136. .tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  137. .tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7,
  138. },
  139. { .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1,
  140. .tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  141. .tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7,
  142. },
  143. { .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
  144. .tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  145. .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
  146. },
  147. { .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
  148. .tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  149. .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
  150. },
  151. { .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1,
  152. .tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  153. .tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6,
  154. },
  155. { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  156. .tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  157. .tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7,
  158. },
  159. };
  160. /* ======================================================================== */
  161. /* Bit definitions inside the registers */
  162. #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
  163. #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
  164. #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
  165. #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
  166. #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
  167. #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
  168. #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
  169. #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
  170. #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
  171. #define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */
  172. #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
  173. #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
  174. #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
  175. #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
  176. #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
  177. #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
  178. #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
  179. #define MAX_DMA_BUFFERS 128
  180. #define MAX_DMA_BUFFER_SIZE 0x20000u
  181. /* Structure of the hardware registers */
  182. struct mpc52xx_ata {
  183. /* Host interface registers */
  184. u32 config; /* ATA + 0x00 Host configuration */
  185. u32 host_status; /* ATA + 0x04 Host controller status */
  186. u32 pio1; /* ATA + 0x08 PIO Timing 1 */
  187. u32 pio2; /* ATA + 0x0c PIO Timing 2 */
  188. u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
  189. u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
  190. u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
  191. u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
  192. u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
  193. u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
  194. u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
  195. u32 share_cnt; /* ATA + 0x2c ATA share counter */
  196. u32 reserved0[3];
  197. /* FIFO registers */
  198. u32 fifo_data; /* ATA + 0x3c */
  199. u8 fifo_status_frame; /* ATA + 0x40 */
  200. u8 fifo_status; /* ATA + 0x41 */
  201. u16 reserved7[1];
  202. u8 fifo_control; /* ATA + 0x44 */
  203. u8 reserved8[5];
  204. u16 fifo_alarm; /* ATA + 0x4a */
  205. u16 reserved9;
  206. u16 fifo_rdp; /* ATA + 0x4e */
  207. u16 reserved10;
  208. u16 fifo_wrp; /* ATA + 0x52 */
  209. u16 reserved11;
  210. u16 fifo_lfrdp; /* ATA + 0x56 */
  211. u16 reserved12;
  212. u16 fifo_lfwrp; /* ATA + 0x5a */
  213. /* Drive TaskFile registers */
  214. u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
  215. u8 reserved13[3];
  216. u16 tf_data; /* ATA + 0x60 TASKFILE Data */
  217. u16 reserved14;
  218. u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
  219. u8 reserved15[3];
  220. u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
  221. u8 reserved16[3];
  222. u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
  223. u8 reserved17[3];
  224. u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
  225. u8 reserved18[3];
  226. u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
  227. u8 reserved19[3];
  228. u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
  229. u8 reserved20[3];
  230. u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
  231. u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
  232. u8 reserved21[2];
  233. };
  234. /* ======================================================================== */
  235. /* Aux fns */
  236. /* ======================================================================== */
  237. /* MPC52xx low level hw control */
  238. static int
  239. mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
  240. {
  241. struct mpc52xx_ata_timings *timing = &priv->timings[dev];
  242. unsigned int ipb_period = priv->ipb_period;
  243. u32 t0, t1, t2_8, t2_16, t2i, t4, ta;
  244. if ((pio < 0) || (pio > 4))
  245. return -EINVAL;
  246. t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
  247. t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
  248. t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
  249. t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
  250. t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
  251. t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
  252. ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
  253. timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
  254. timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
  255. return 0;
  256. }
  257. static int
  258. mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
  259. int speed)
  260. {
  261. struct mpc52xx_ata_timings *t = &priv->timings[dev];
  262. const struct mdmaspec *s = &priv->mdmaspec[speed];
  263. if (speed < 0 || speed > 2)
  264. return -EINVAL;
  265. t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm;
  266. t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8);
  267. t->using_udma = 0;
  268. return 0;
  269. }
  270. static int
  271. mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
  272. int speed)
  273. {
  274. struct mpc52xx_ata_timings *t = &priv->timings[dev];
  275. const struct udmaspec *s = &priv->udmaspec[speed];
  276. if (speed < 0 || speed > 2)
  277. return -EINVAL;
  278. t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh;
  279. t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli;
  280. t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr;
  281. t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack;
  282. t->udma5 = (u32)s->tzah << 24;
  283. t->using_udma = 1;
  284. return 0;
  285. }
  286. static void
  287. mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
  288. {
  289. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  290. struct mpc52xx_ata_timings *timing = &priv->timings[device];
  291. out_be32(&regs->pio1, timing->pio1);
  292. out_be32(&regs->pio2, timing->pio2);
  293. out_be32(&regs->mdma1, timing->mdma1);
  294. out_be32(&regs->mdma2, timing->mdma2);
  295. out_be32(&regs->udma1, timing->udma1);
  296. out_be32(&regs->udma2, timing->udma2);
  297. out_be32(&regs->udma3, timing->udma3);
  298. out_be32(&regs->udma4, timing->udma4);
  299. out_be32(&regs->udma5, timing->udma5);
  300. priv->csel = device;
  301. }
  302. static int
  303. mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
  304. {
  305. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  306. int tslot;
  307. /* Clear share_cnt (all sample code do this ...) */
  308. out_be32(&regs->share_cnt, 0);
  309. /* Configure and reset host */
  310. out_be32(&regs->config,
  311. MPC52xx_ATA_HOSTCONF_IE |
  312. MPC52xx_ATA_HOSTCONF_IORDY |
  313. MPC52xx_ATA_HOSTCONF_SMR |
  314. MPC52xx_ATA_HOSTCONF_FR);
  315. udelay(10);
  316. out_be32(&regs->config,
  317. MPC52xx_ATA_HOSTCONF_IE |
  318. MPC52xx_ATA_HOSTCONF_IORDY);
  319. /* Set the time slot to 1us */
  320. tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
  321. out_be32(&regs->share_cnt, tslot << 16);
  322. /* Init timings to PIO0 */
  323. memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
  324. mpc52xx_ata_compute_pio_timings(priv, 0, 0);
  325. mpc52xx_ata_compute_pio_timings(priv, 1, 0);
  326. mpc52xx_ata_apply_timings(priv, 0);
  327. return 0;
  328. }
  329. /* ======================================================================== */
  330. /* libata driver */
  331. /* ======================================================================== */
  332. static void
  333. mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
  334. {
  335. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  336. int pio, rv;
  337. pio = adev->pio_mode - XFER_PIO_0;
  338. rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
  339. if (rv) {
  340. dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio);
  341. return;
  342. }
  343. mpc52xx_ata_apply_timings(priv, adev->devno);
  344. }
  345. static void
  346. mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  347. {
  348. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  349. int rv;
  350. if (adev->dma_mode >= XFER_UDMA_0) {
  351. int dma = adev->dma_mode - XFER_UDMA_0;
  352. rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma);
  353. } else {
  354. int dma = adev->dma_mode - XFER_MW_DMA_0;
  355. rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma);
  356. }
  357. if (rv) {
  358. dev_alert(ap->dev,
  359. "Trying to select invalid DMA mode %d\n",
  360. adev->dma_mode);
  361. return;
  362. }
  363. mpc52xx_ata_apply_timings(priv, adev->devno);
  364. }
  365. static void
  366. mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
  367. {
  368. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  369. if (device != priv->csel)
  370. mpc52xx_ata_apply_timings(priv, device);
  371. ata_sff_dev_select(ap, device);
  372. }
  373. static int
  374. mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc)
  375. {
  376. struct ata_port *ap = qc->ap;
  377. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  378. struct bcom_ata_bd *bd;
  379. unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si;
  380. struct scatterlist *sg;
  381. int count = 0;
  382. if (read)
  383. bcom_ata_rx_prepare(priv->dmatsk);
  384. else
  385. bcom_ata_tx_prepare(priv->dmatsk);
  386. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  387. dma_addr_t cur_addr = sg_dma_address(sg);
  388. u32 cur_len = sg_dma_len(sg);
  389. while (cur_len) {
  390. unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE);
  391. bd = (struct bcom_ata_bd *)
  392. bcom_prepare_next_buffer(priv->dmatsk);
  393. if (read) {
  394. bd->status = tc;
  395. bd->src_pa = (__force u32) priv->ata_regs_pa +
  396. offsetof(struct mpc52xx_ata, fifo_data);
  397. bd->dst_pa = (__force u32) cur_addr;
  398. } else {
  399. bd->status = tc;
  400. bd->src_pa = (__force u32) cur_addr;
  401. bd->dst_pa = (__force u32) priv->ata_regs_pa +
  402. offsetof(struct mpc52xx_ata, fifo_data);
  403. }
  404. bcom_submit_next_buffer(priv->dmatsk, NULL);
  405. cur_addr += tc;
  406. cur_len -= tc;
  407. count++;
  408. if (count > MAX_DMA_BUFFERS) {
  409. dev_alert(ap->dev, "dma table"
  410. "too small\n");
  411. goto use_pio_instead;
  412. }
  413. }
  414. }
  415. return 1;
  416. use_pio_instead:
  417. bcom_ata_reset_bd(priv->dmatsk);
  418. return 0;
  419. }
  420. static void
  421. mpc52xx_bmdma_setup(struct ata_queued_cmd *qc)
  422. {
  423. struct ata_port *ap = qc->ap;
  424. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  425. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  426. unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE);
  427. u8 dma_mode;
  428. if (!mpc52xx_ata_build_dmatable(qc))
  429. dev_alert(ap->dev, "%s: %i, return 1?\n",
  430. __func__, __LINE__);
  431. /* Check FIFO is OK... */
  432. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
  433. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  434. __func__, in_8(&priv->ata_regs->fifo_status));
  435. if (read) {
  436. dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ |
  437. MPC52xx_ATA_DMAMODE_FE;
  438. /* Setup FIFO if direction changed */
  439. if (priv->mpc52xx_ata_dma_last_write != 0) {
  440. priv->mpc52xx_ata_dma_last_write = 0;
  441. /* Configure FIFO with granularity to 7 */
  442. out_8(&regs->fifo_control, 7);
  443. out_be16(&regs->fifo_alarm, 128);
  444. /* Set FIFO Reset bit (FR) */
  445. out_8(&regs->dma_mode, MPC52xx_ATA_DMAMODE_FR);
  446. }
  447. } else {
  448. dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE;
  449. /* Setup FIFO if direction changed */
  450. if (priv->mpc52xx_ata_dma_last_write != 1) {
  451. priv->mpc52xx_ata_dma_last_write = 1;
  452. /* Configure FIFO with granularity to 4 */
  453. out_8(&regs->fifo_control, 4);
  454. out_be16(&regs->fifo_alarm, 128);
  455. }
  456. }
  457. if (priv->timings[qc->dev->devno].using_udma)
  458. dma_mode |= MPC52xx_ATA_DMAMODE_UDMA;
  459. out_8(&regs->dma_mode, dma_mode);
  460. priv->waiting_for_dma = ATA_DMA_ACTIVE;
  461. ata_wait_idle(ap);
  462. ap->ops->sff_exec_command(ap, &qc->tf);
  463. }
  464. static void
  465. mpc52xx_bmdma_start(struct ata_queued_cmd *qc)
  466. {
  467. struct ata_port *ap = qc->ap;
  468. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  469. bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum);
  470. bcom_enable(priv->dmatsk);
  471. }
  472. static void
  473. mpc52xx_bmdma_stop(struct ata_queued_cmd *qc)
  474. {
  475. struct ata_port *ap = qc->ap;
  476. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  477. bcom_disable(priv->dmatsk);
  478. bcom_ata_reset_bd(priv->dmatsk);
  479. priv->waiting_for_dma = 0;
  480. /* Check FIFO is OK... */
  481. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
  482. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  483. __func__, in_8(&priv->ata_regs->fifo_status));
  484. }
  485. static u8
  486. mpc52xx_bmdma_status(struct ata_port *ap)
  487. {
  488. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  489. /* Check FIFO is OK... */
  490. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) {
  491. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  492. __func__, in_8(&priv->ata_regs->fifo_status));
  493. return priv->waiting_for_dma | ATA_DMA_ERR;
  494. }
  495. return priv->waiting_for_dma;
  496. }
  497. static irqreturn_t
  498. mpc52xx_ata_task_irq(int irq, void *vpriv)
  499. {
  500. struct mpc52xx_ata_priv *priv = vpriv;
  501. while (bcom_buffer_done(priv->dmatsk))
  502. bcom_retrieve_buffer(priv->dmatsk, NULL, NULL);
  503. priv->waiting_for_dma |= ATA_DMA_INTR;
  504. return IRQ_HANDLED;
  505. }
  506. static struct scsi_host_template mpc52xx_ata_sht = {
  507. ATA_PIO_SHT(DRV_NAME),
  508. };
  509. static struct ata_port_operations mpc52xx_ata_port_ops = {
  510. .inherits = &ata_bmdma_port_ops,
  511. .sff_dev_select = mpc52xx_ata_dev_select,
  512. .set_piomode = mpc52xx_ata_set_piomode,
  513. .set_dmamode = mpc52xx_ata_set_dmamode,
  514. .bmdma_setup = mpc52xx_bmdma_setup,
  515. .bmdma_start = mpc52xx_bmdma_start,
  516. .bmdma_stop = mpc52xx_bmdma_stop,
  517. .bmdma_status = mpc52xx_bmdma_status,
  518. .qc_prep = ata_noop_qc_prep,
  519. };
  520. static int mpc52xx_ata_init_one(struct device *dev,
  521. struct mpc52xx_ata_priv *priv,
  522. unsigned long raw_ata_regs,
  523. int mwdma_mask, int udma_mask)
  524. {
  525. struct ata_host *host;
  526. struct ata_port *ap;
  527. struct ata_ioports *aio;
  528. host = ata_host_alloc(dev, 1);
  529. if (!host)
  530. return -ENOMEM;
  531. ap = host->ports[0];
  532. ap->flags |= ATA_FLAG_SLAVE_POSS;
  533. ap->pio_mask = ATA_PIO4;
  534. ap->mwdma_mask = mwdma_mask;
  535. ap->udma_mask = udma_mask;
  536. ap->ops = &mpc52xx_ata_port_ops;
  537. host->private_data = priv;
  538. aio = &ap->ioaddr;
  539. aio->cmd_addr = NULL; /* Don't have a classic reg block */
  540. aio->altstatus_addr = &priv->ata_regs->tf_control;
  541. aio->ctl_addr = &priv->ata_regs->tf_control;
  542. aio->data_addr = &priv->ata_regs->tf_data;
  543. aio->error_addr = &priv->ata_regs->tf_features;
  544. aio->feature_addr = &priv->ata_regs->tf_features;
  545. aio->nsect_addr = &priv->ata_regs->tf_sec_count;
  546. aio->lbal_addr = &priv->ata_regs->tf_sec_num;
  547. aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
  548. aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
  549. aio->device_addr = &priv->ata_regs->tf_dev_head;
  550. aio->status_addr = &priv->ata_regs->tf_command;
  551. aio->command_addr = &priv->ata_regs->tf_command;
  552. ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
  553. /* activate host */
  554. return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0,
  555. &mpc52xx_ata_sht);
  556. }
  557. /* ======================================================================== */
  558. /* OF Platform driver */
  559. /* ======================================================================== */
  560. static int mpc52xx_ata_probe(struct platform_device *op)
  561. {
  562. unsigned int ipb_freq;
  563. struct resource res_mem;
  564. int ata_irq = 0;
  565. struct mpc52xx_ata __iomem *ata_regs;
  566. struct mpc52xx_ata_priv *priv = NULL;
  567. int rv, task_irq;
  568. int mwdma_mask = 0, udma_mask = 0;
  569. const __be32 *prop;
  570. int proplen;
  571. struct bcom_task *dmatsk;
  572. /* Get ipb frequency */
  573. ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
  574. if (!ipb_freq) {
  575. dev_err(&op->dev, "could not determine IPB bus frequency\n");
  576. return -ENODEV;
  577. }
  578. /* Get device base address from device tree, request the region
  579. * and ioremap it. */
  580. rv = of_address_to_resource(op->dev.of_node, 0, &res_mem);
  581. if (rv) {
  582. dev_err(&op->dev, "could not determine device base address\n");
  583. return rv;
  584. }
  585. if (!devm_request_mem_region(&op->dev, res_mem.start,
  586. sizeof(*ata_regs), DRV_NAME)) {
  587. dev_err(&op->dev, "error requesting register region\n");
  588. return -EBUSY;
  589. }
  590. ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs));
  591. if (!ata_regs) {
  592. dev_err(&op->dev, "error mapping device registers\n");
  593. return -ENOMEM;
  594. }
  595. /*
  596. * By default, all DMA modes are disabled for the MPC5200. Some
  597. * boards don't have the required signals routed to make DMA work.
  598. * Also, the MPC5200B has a silicon bug that causes data corruption
  599. * with UDMA if it is used at the same time as the LocalPlus bus.
  600. *
  601. * Instead of trying to guess what modes are usable, check the
  602. * ATA device tree node to find out what DMA modes work on the board.
  603. * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>"
  604. * to the kernel boot parameters.
  605. *
  606. * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
  607. * UDMA modes 0, 1 and 2.
  608. */
  609. prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen);
  610. if ((prop) && (proplen >= 4))
  611. mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
  612. prop = of_get_property(op->dev.of_node, "udma-mode", &proplen);
  613. if ((prop) && (proplen >= 4))
  614. udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
  615. ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
  616. if (ata_irq == NO_IRQ) {
  617. dev_err(&op->dev, "error mapping irq\n");
  618. return -EINVAL;
  619. }
  620. /* Prepare our private structure */
  621. priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_KERNEL);
  622. if (!priv) {
  623. rv = -ENOMEM;
  624. goto err1;
  625. }
  626. priv->ipb_period = 1000000000 / (ipb_freq / 1000);
  627. priv->ata_regs = ata_regs;
  628. priv->ata_regs_pa = res_mem.start;
  629. priv->ata_irq = ata_irq;
  630. priv->csel = -1;
  631. priv->mpc52xx_ata_dma_last_write = -1;
  632. if (ipb_freq/1000000 == 66) {
  633. priv->mdmaspec = mdmaspec66;
  634. priv->udmaspec = udmaspec66;
  635. } else {
  636. priv->mdmaspec = mdmaspec132;
  637. priv->udmaspec = udmaspec132;
  638. }
  639. /* Allocate a BestComm task for DMA */
  640. dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE);
  641. if (!dmatsk) {
  642. dev_err(&op->dev, "bestcomm initialization failed\n");
  643. rv = -ENOMEM;
  644. goto err1;
  645. }
  646. task_irq = bcom_get_task_irq(dmatsk);
  647. rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0,
  648. "ATA task", priv);
  649. if (rv) {
  650. dev_err(&op->dev, "error requesting DMA IRQ\n");
  651. goto err2;
  652. }
  653. priv->dmatsk = dmatsk;
  654. /* Init the hw */
  655. rv = mpc52xx_ata_hw_init(priv);
  656. if (rv) {
  657. dev_err(&op->dev, "error initializing hardware\n");
  658. goto err2;
  659. }
  660. /* Register ourselves to libata */
  661. rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start,
  662. mwdma_mask, udma_mask);
  663. if (rv) {
  664. dev_err(&op->dev, "error registering with ATA layer\n");
  665. goto err2;
  666. }
  667. return 0;
  668. err2:
  669. irq_dispose_mapping(task_irq);
  670. bcom_ata_release(dmatsk);
  671. err1:
  672. irq_dispose_mapping(ata_irq);
  673. return rv;
  674. }
  675. static int
  676. mpc52xx_ata_remove(struct platform_device *op)
  677. {
  678. struct ata_host *host = platform_get_drvdata(op);
  679. struct mpc52xx_ata_priv *priv = host->private_data;
  680. int task_irq;
  681. /* Deregister the ATA interface */
  682. ata_platform_remove_one(op);
  683. /* Clean up DMA */
  684. task_irq = bcom_get_task_irq(priv->dmatsk);
  685. irq_dispose_mapping(task_irq);
  686. bcom_ata_release(priv->dmatsk);
  687. irq_dispose_mapping(priv->ata_irq);
  688. return 0;
  689. }
  690. #ifdef CONFIG_PM_SLEEP
  691. static int
  692. mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
  693. {
  694. struct ata_host *host = platform_get_drvdata(op);
  695. ata_host_suspend(host, state);
  696. return 0;
  697. }
  698. static int
  699. mpc52xx_ata_resume(struct platform_device *op)
  700. {
  701. struct ata_host *host = platform_get_drvdata(op);
  702. struct mpc52xx_ata_priv *priv = host->private_data;
  703. int rv;
  704. rv = mpc52xx_ata_hw_init(priv);
  705. if (rv) {
  706. dev_err(host->dev, "error initializing hardware\n");
  707. return rv;
  708. }
  709. ata_host_resume(host);
  710. return 0;
  711. }
  712. #endif
  713. static const struct of_device_id mpc52xx_ata_of_match[] = {
  714. { .compatible = "fsl,mpc5200-ata", },
  715. { .compatible = "mpc5200-ata", },
  716. { /* sentinel */ }
  717. };
  718. static struct platform_driver mpc52xx_ata_of_platform_driver = {
  719. .probe = mpc52xx_ata_probe,
  720. .remove = mpc52xx_ata_remove,
  721. #ifdef CONFIG_PM_SLEEP
  722. .suspend = mpc52xx_ata_suspend,
  723. .resume = mpc52xx_ata_resume,
  724. #endif
  725. .driver = {
  726. .name = DRV_NAME,
  727. .of_match_table = mpc52xx_ata_of_match,
  728. },
  729. };
  730. module_platform_driver(mpc52xx_ata_of_platform_driver);
  731. MODULE_AUTHOR("Sylvain Munaut <[email protected]>");
  732. MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
  733. MODULE_LICENSE("GPL");
  734. MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);