pata_icside.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/kernel.h>
  3. #include <linux/module.h>
  4. #include <linux/init.h>
  5. #include <linux/blkdev.h>
  6. #include <linux/gfp.h>
  7. #include <scsi/scsi_host.h>
  8. #include <linux/ata.h>
  9. #include <linux/libata.h>
  10. #include <asm/dma.h>
  11. #include <asm/ecard.h>
  12. #define DRV_NAME "pata_icside"
  13. #define ICS_IDENT_OFFSET 0x2280
  14. #define ICS_ARCIN_V5_INTRSTAT 0x0000
  15. #define ICS_ARCIN_V5_INTROFFSET 0x0004
  16. #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
  17. #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
  18. #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
  19. #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
  20. struct portinfo {
  21. unsigned int dataoffset;
  22. unsigned int ctrloffset;
  23. unsigned int stepping;
  24. };
  25. static const struct portinfo pata_icside_portinfo_v5 = {
  26. .dataoffset = 0x2800,
  27. .ctrloffset = 0x2b80,
  28. .stepping = 6,
  29. };
  30. static const struct portinfo pata_icside_portinfo_v6_1 = {
  31. .dataoffset = 0x2000,
  32. .ctrloffset = 0x2380,
  33. .stepping = 6,
  34. };
  35. static const struct portinfo pata_icside_portinfo_v6_2 = {
  36. .dataoffset = 0x3000,
  37. .ctrloffset = 0x3380,
  38. .stepping = 6,
  39. };
  40. struct pata_icside_state {
  41. void __iomem *irq_port;
  42. void __iomem *ioc_base;
  43. unsigned int type;
  44. unsigned int dma;
  45. struct {
  46. u8 port_sel;
  47. u8 disabled;
  48. unsigned int speed[ATA_MAX_DEVICES];
  49. } port[2];
  50. };
  51. struct pata_icside_info {
  52. struct pata_icside_state *state;
  53. struct expansion_card *ec;
  54. void __iomem *base;
  55. void __iomem *irqaddr;
  56. unsigned int irqmask;
  57. const expansioncard_ops_t *irqops;
  58. unsigned int mwdma_mask;
  59. unsigned int nr_ports;
  60. const struct portinfo *port[2];
  61. unsigned long raw_base;
  62. unsigned long raw_ioc_base;
  63. };
  64. #define ICS_TYPE_A3IN 0
  65. #define ICS_TYPE_A3USER 1
  66. #define ICS_TYPE_V6 3
  67. #define ICS_TYPE_V5 15
  68. #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  69. /* ---------------- Version 5 PCB Support Functions --------------------- */
  70. /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  71. * Purpose : enable interrupts from card
  72. */
  73. static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  74. {
  75. struct pata_icside_state *state = ec->irq_data;
  76. writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  77. }
  78. /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  79. * Purpose : disable interrupts from card
  80. */
  81. static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  82. {
  83. struct pata_icside_state *state = ec->irq_data;
  84. readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  85. }
  86. static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
  87. .irqenable = pata_icside_irqenable_arcin_v5,
  88. .irqdisable = pata_icside_irqdisable_arcin_v5,
  89. };
  90. /* ---------------- Version 6 PCB Support Functions --------------------- */
  91. /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  92. * Purpose : enable interrupts from card
  93. */
  94. static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  95. {
  96. struct pata_icside_state *state = ec->irq_data;
  97. void __iomem *base = state->irq_port;
  98. if (!state->port[0].disabled)
  99. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
  100. if (!state->port[1].disabled)
  101. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
  102. }
  103. /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  104. * Purpose : disable interrupts from card
  105. */
  106. static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  107. {
  108. struct pata_icside_state *state = ec->irq_data;
  109. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  110. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  111. }
  112. /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
  113. * Purpose : detect an active interrupt from card
  114. */
  115. static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
  116. {
  117. struct pata_icside_state *state = ec->irq_data;
  118. return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
  119. readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
  120. }
  121. static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
  122. .irqenable = pata_icside_irqenable_arcin_v6,
  123. .irqdisable = pata_icside_irqdisable_arcin_v6,
  124. .irqpending = pata_icside_irqpending_arcin_v6,
  125. };
  126. /*
  127. * SG-DMA support.
  128. *
  129. * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
  130. * There is only one DMA controller per card, which means that only
  131. * one drive can be accessed at one time. NOTE! We do not enforce that
  132. * here, but we rely on the main IDE driver spotting that both
  133. * interfaces use the same IRQ, which should guarantee this.
  134. */
  135. /*
  136. * Configure the IOMD to give the appropriate timings for the transfer
  137. * mode being requested. We take the advice of the ATA standards, and
  138. * calculate the cycle time based on the transfer mode, and the EIDE
  139. * MW DMA specs that the drive provides in the IDENTIFY command.
  140. *
  141. * We have the following IOMD DMA modes to choose from:
  142. *
  143. * Type Active Recovery Cycle
  144. * A 250 (250) 312 (550) 562 (800)
  145. * B 187 (200) 250 (550) 437 (750)
  146. * C 125 (125) 125 (375) 250 (500)
  147. * D 62 (50) 125 (375) 187 (425)
  148. *
  149. * (figures in brackets are actual measured timings on DIOR/DIOW)
  150. *
  151. * However, we also need to take care of the read/write active and
  152. * recovery timings:
  153. *
  154. * Read Write
  155. * Mode Active -- Recovery -- Cycle IOMD type
  156. * MW0 215 50 215 480 A
  157. * MW1 80 50 50 150 C
  158. * MW2 70 25 25 120 C
  159. */
  160. static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  161. {
  162. struct pata_icside_state *state = ap->host->private_data;
  163. struct ata_timing t;
  164. unsigned int cycle;
  165. char iomd_type;
  166. /*
  167. * DMA is based on a 16MHz clock
  168. */
  169. if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
  170. return;
  171. /*
  172. * Choose the IOMD cycle timing which ensure that the interface
  173. * satisfies the measured active, recovery and cycle times.
  174. */
  175. if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) {
  176. iomd_type = 'D';
  177. cycle = 187;
  178. } else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) {
  179. iomd_type = 'C';
  180. cycle = 250;
  181. } else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) {
  182. iomd_type = 'B';
  183. cycle = 437;
  184. } else {
  185. iomd_type = 'A';
  186. cycle = 562;
  187. }
  188. ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
  189. t.active, t.recover, t.cycle, iomd_type);
  190. state->port[ap->port_no].speed[adev->devno] = cycle;
  191. }
  192. static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
  193. {
  194. struct ata_port *ap = qc->ap;
  195. struct pata_icside_state *state = ap->host->private_data;
  196. unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
  197. /*
  198. * We are simplex; BUG if we try to fiddle with DMA
  199. * while it's active.
  200. */
  201. BUG_ON(dma_channel_active(state->dma));
  202. /*
  203. * Route the DMA signals to the correct interface
  204. */
  205. writeb(state->port[ap->port_no].port_sel, state->ioc_base);
  206. set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
  207. set_dma_sg(state->dma, qc->sg, qc->n_elem);
  208. set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
  209. /* issue r/w command */
  210. ap->ops->sff_exec_command(ap, &qc->tf);
  211. }
  212. static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
  213. {
  214. struct ata_port *ap = qc->ap;
  215. struct pata_icside_state *state = ap->host->private_data;
  216. BUG_ON(dma_channel_active(state->dma));
  217. enable_dma(state->dma);
  218. }
  219. static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
  220. {
  221. struct ata_port *ap = qc->ap;
  222. struct pata_icside_state *state = ap->host->private_data;
  223. disable_dma(state->dma);
  224. /* see ata_bmdma_stop */
  225. ata_sff_dma_pause(ap);
  226. }
  227. static u8 pata_icside_bmdma_status(struct ata_port *ap)
  228. {
  229. struct pata_icside_state *state = ap->host->private_data;
  230. void __iomem *irq_port;
  231. irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
  232. ICS_ARCIN_V6_INTRSTAT_1);
  233. return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
  234. }
  235. static int icside_dma_init(struct pata_icside_info *info)
  236. {
  237. struct pata_icside_state *state = info->state;
  238. struct expansion_card *ec = info->ec;
  239. int i;
  240. for (i = 0; i < ATA_MAX_DEVICES; i++) {
  241. state->port[0].speed[i] = 480;
  242. state->port[1].speed[i] = 480;
  243. }
  244. if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
  245. state->dma = ec->dma;
  246. info->mwdma_mask = ATA_MWDMA2;
  247. }
  248. return 0;
  249. }
  250. static struct scsi_host_template pata_icside_sht = {
  251. ATA_BASE_SHT(DRV_NAME),
  252. .sg_tablesize = SG_MAX_SEGMENTS,
  253. .dma_boundary = IOMD_DMA_BOUNDARY,
  254. };
  255. static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
  256. {
  257. struct ata_port *ap = link->ap;
  258. struct pata_icside_state *state = ap->host->private_data;
  259. if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
  260. return ata_sff_postreset(link, classes);
  261. state->port[ap->port_no].disabled = 1;
  262. if (state->type == ICS_TYPE_V6) {
  263. /*
  264. * Disable interrupts from this port, otherwise we
  265. * receive spurious interrupts from the floating
  266. * interrupt line.
  267. */
  268. void __iomem *irq_port = state->irq_port +
  269. (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
  270. readb(irq_port);
  271. }
  272. }
  273. static struct ata_port_operations pata_icside_port_ops = {
  274. .inherits = &ata_bmdma_port_ops,
  275. /* no need to build any PRD tables for DMA */
  276. .qc_prep = ata_noop_qc_prep,
  277. .sff_data_xfer = ata_sff_data_xfer32,
  278. .bmdma_setup = pata_icside_bmdma_setup,
  279. .bmdma_start = pata_icside_bmdma_start,
  280. .bmdma_stop = pata_icside_bmdma_stop,
  281. .bmdma_status = pata_icside_bmdma_status,
  282. .cable_detect = ata_cable_40wire,
  283. .set_dmamode = pata_icside_set_dmamode,
  284. .postreset = pata_icside_postreset,
  285. .port_start = ATA_OP_NULL, /* don't need PRD table */
  286. };
  287. static void pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
  288. struct pata_icside_info *info,
  289. const struct portinfo *port)
  290. {
  291. struct ata_ioports *ioaddr = &ap->ioaddr;
  292. void __iomem *cmd = base + port->dataoffset;
  293. ioaddr->cmd_addr = cmd;
  294. ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
  295. ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
  296. ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
  297. ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
  298. ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
  299. ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
  300. ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
  301. ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
  302. ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
  303. ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
  304. ioaddr->ctl_addr = base + port->ctrloffset;
  305. ioaddr->altstatus_addr = ioaddr->ctl_addr;
  306. ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
  307. info->raw_base + port->dataoffset,
  308. info->raw_base + port->ctrloffset);
  309. if (info->raw_ioc_base)
  310. ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
  311. }
  312. static int pata_icside_register_v5(struct pata_icside_info *info)
  313. {
  314. struct pata_icside_state *state = info->state;
  315. void __iomem *base;
  316. base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
  317. if (!base)
  318. return -ENOMEM;
  319. state->irq_port = base;
  320. info->base = base;
  321. info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
  322. info->irqmask = 1;
  323. info->irqops = &pata_icside_ops_arcin_v5;
  324. info->nr_ports = 1;
  325. info->port[0] = &pata_icside_portinfo_v5;
  326. info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
  327. return 0;
  328. }
  329. static int pata_icside_register_v6(struct pata_icside_info *info)
  330. {
  331. struct pata_icside_state *state = info->state;
  332. struct expansion_card *ec = info->ec;
  333. void __iomem *ioc_base, *easi_base;
  334. unsigned int sel = 0;
  335. ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  336. if (!ioc_base)
  337. return -ENOMEM;
  338. easi_base = ioc_base;
  339. if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
  340. easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
  341. if (!easi_base)
  342. return -ENOMEM;
  343. /*
  344. * Enable access to the EASI region.
  345. */
  346. sel = 1 << 5;
  347. }
  348. writeb(sel, ioc_base);
  349. state->irq_port = easi_base;
  350. state->ioc_base = ioc_base;
  351. state->port[0].port_sel = sel;
  352. state->port[1].port_sel = sel | 1;
  353. info->base = easi_base;
  354. info->irqops = &pata_icside_ops_arcin_v6;
  355. info->nr_ports = 2;
  356. info->port[0] = &pata_icside_portinfo_v6_1;
  357. info->port[1] = &pata_icside_portinfo_v6_2;
  358. info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
  359. info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
  360. return icside_dma_init(info);
  361. }
  362. static int pata_icside_add_ports(struct pata_icside_info *info)
  363. {
  364. struct expansion_card *ec = info->ec;
  365. struct ata_host *host;
  366. int i;
  367. if (info->irqaddr) {
  368. ec->irqaddr = info->irqaddr;
  369. ec->irqmask = info->irqmask;
  370. }
  371. if (info->irqops)
  372. ecard_setirq(ec, info->irqops, info->state);
  373. /*
  374. * Be on the safe side - disable interrupts
  375. */
  376. ec->ops->irqdisable(ec, ec->irq);
  377. host = ata_host_alloc(&ec->dev, info->nr_ports);
  378. if (!host)
  379. return -ENOMEM;
  380. host->private_data = info->state;
  381. host->flags = ATA_HOST_SIMPLEX;
  382. for (i = 0; i < info->nr_ports; i++) {
  383. struct ata_port *ap = host->ports[i];
  384. ap->pio_mask = ATA_PIO4;
  385. ap->mwdma_mask = info->mwdma_mask;
  386. ap->flags |= ATA_FLAG_SLAVE_POSS;
  387. ap->ops = &pata_icside_port_ops;
  388. pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
  389. }
  390. return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
  391. &pata_icside_sht);
  392. }
  393. static int pata_icside_probe(struct expansion_card *ec,
  394. const struct ecard_id *id)
  395. {
  396. struct pata_icside_state *state;
  397. struct pata_icside_info info;
  398. void __iomem *idmem;
  399. int ret;
  400. ret = ecard_request_resources(ec);
  401. if (ret)
  402. goto out;
  403. state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
  404. if (!state) {
  405. ret = -ENOMEM;
  406. goto release;
  407. }
  408. state->type = ICS_TYPE_NOTYPE;
  409. state->dma = NO_DMA;
  410. idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  411. if (idmem) {
  412. unsigned int type;
  413. type = readb(idmem + ICS_IDENT_OFFSET) & 1;
  414. type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
  415. type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
  416. type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
  417. ecardm_iounmap(ec, idmem);
  418. state->type = type;
  419. }
  420. memset(&info, 0, sizeof(info));
  421. info.state = state;
  422. info.ec = ec;
  423. switch (state->type) {
  424. case ICS_TYPE_A3IN:
  425. dev_warn(&ec->dev, "A3IN unsupported\n");
  426. ret = -ENODEV;
  427. break;
  428. case ICS_TYPE_A3USER:
  429. dev_warn(&ec->dev, "A3USER unsupported\n");
  430. ret = -ENODEV;
  431. break;
  432. case ICS_TYPE_V5:
  433. ret = pata_icside_register_v5(&info);
  434. break;
  435. case ICS_TYPE_V6:
  436. ret = pata_icside_register_v6(&info);
  437. break;
  438. default:
  439. dev_warn(&ec->dev, "unknown interface type\n");
  440. ret = -ENODEV;
  441. break;
  442. }
  443. if (ret == 0)
  444. ret = pata_icside_add_ports(&info);
  445. if (ret == 0)
  446. goto out;
  447. release:
  448. ecard_release_resources(ec);
  449. out:
  450. return ret;
  451. }
  452. static void pata_icside_shutdown(struct expansion_card *ec)
  453. {
  454. struct ata_host *host = ecard_get_drvdata(ec);
  455. unsigned long flags;
  456. /*
  457. * Disable interrupts from this card. We need to do
  458. * this before disabling EASI since we may be accessing
  459. * this register via that region.
  460. */
  461. local_irq_save(flags);
  462. ec->ops->irqdisable(ec, ec->irq);
  463. local_irq_restore(flags);
  464. /*
  465. * Reset the ROM pointer so that we can read the ROM
  466. * after a soft reboot. This also disables access to
  467. * the IDE taskfile via the EASI region.
  468. */
  469. if (host) {
  470. struct pata_icside_state *state = host->private_data;
  471. if (state->ioc_base)
  472. writeb(0, state->ioc_base);
  473. }
  474. }
  475. static void pata_icside_remove(struct expansion_card *ec)
  476. {
  477. struct ata_host *host = ecard_get_drvdata(ec);
  478. struct pata_icside_state *state = host->private_data;
  479. ata_host_detach(host);
  480. pata_icside_shutdown(ec);
  481. /*
  482. * don't NULL out the drvdata - devres/libata wants it
  483. * to free the ata_host structure.
  484. */
  485. if (state->dma != NO_DMA)
  486. free_dma(state->dma);
  487. ecard_release_resources(ec);
  488. }
  489. static const struct ecard_id pata_icside_ids[] = {
  490. { MANU_ICS, PROD_ICS_IDE },
  491. { MANU_ICS2, PROD_ICS2_IDE },
  492. { 0xffff, 0xffff }
  493. };
  494. static struct ecard_driver pata_icside_driver = {
  495. .probe = pata_icside_probe,
  496. .remove = pata_icside_remove,
  497. .shutdown = pata_icside_shutdown,
  498. .id_table = pata_icside_ids,
  499. .drv = {
  500. .name = DRV_NAME,
  501. },
  502. };
  503. static int __init pata_icside_init(void)
  504. {
  505. return ecard_register_driver(&pata_icside_driver);
  506. }
  507. static void __exit pata_icside_exit(void)
  508. {
  509. ecard_remove_driver(&pata_icside_driver);
  510. }
  511. MODULE_AUTHOR("Russell King <[email protected]>");
  512. MODULE_LICENSE("GPL");
  513. MODULE_DESCRIPTION("ICS PATA driver");
  514. module_init(pata_icside_init);
  515. module_exit(pata_icside_exit);