perf-c2c.txt 9.0 KB

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  1. perf-c2c(1)
  2. ===========
  3. NAME
  4. ----
  5. perf-c2c - Shared Data C2C/HITM Analyzer.
  6. SYNOPSIS
  7. --------
  8. [verse]
  9. 'perf c2c record' [<options>] <command>
  10. 'perf c2c record' [<options>] \-- [<record command options>] <command>
  11. 'perf c2c report' [<options>]
  12. DESCRIPTION
  13. -----------
  14. C2C stands for Cache To Cache.
  15. The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
  16. you to track down the cacheline contentions.
  17. On Intel, the tool is based on load latency and precise store facility events
  18. provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
  19. with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
  20. limitations, perf c2c is not supported on Zen3 cpus).
  21. These events provide:
  22. - memory address of the access
  23. - type of the access (load and store details)
  24. - latency (in cycles) of the load access
  25. The c2c tool provide means to record this data and report back access details
  26. for cachelines with highest contention - highest number of HITM accesses.
  27. The basic workflow with this tool follows the standard record/report phase.
  28. User uses the record command to record events data and report command to
  29. display it.
  30. RECORD OPTIONS
  31. --------------
  32. -e::
  33. --event=::
  34. Select the PMU event. Use 'perf c2c record -e list'
  35. to list available events.
  36. -v::
  37. --verbose::
  38. Be more verbose (show counter open errors, etc).
  39. -l::
  40. --ldlat::
  41. Configure mem-loads latency. Supported on Intel and Arm64 processors
  42. only. Ignored on other archs.
  43. -k::
  44. --all-kernel::
  45. Configure all used events to run in kernel space.
  46. -u::
  47. --all-user::
  48. Configure all used events to run in user space.
  49. REPORT OPTIONS
  50. --------------
  51. -k::
  52. --vmlinux=<file>::
  53. vmlinux pathname
  54. -v::
  55. --verbose::
  56. Be more verbose (show counter open errors, etc).
  57. -i::
  58. --input::
  59. Specify the input file to process.
  60. -N::
  61. --node-info::
  62. Show extra node info in report (see NODE INFO section)
  63. -c::
  64. --coalesce::
  65. Specify sorting fields for single cacheline display.
  66. Following fields are available: tid,pid,iaddr,dso
  67. (see COALESCE)
  68. -g::
  69. --call-graph::
  70. Setup callchains parameters.
  71. Please refer to perf-report man page for details.
  72. --stdio::
  73. Force the stdio output (see STDIO OUTPUT)
  74. --stats::
  75. Display only statistic tables and force stdio mode.
  76. --full-symbols::
  77. Display full length of symbols.
  78. --no-source::
  79. Do not display Source:Line column.
  80. --show-all::
  81. Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
  82. -f::
  83. --force::
  84. Don't do ownership validation.
  85. -d::
  86. --display::
  87. Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
  88. and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode
  89. as default.
  90. --stitch-lbr::
  91. Show callgraph with stitched LBRs, which may have more complete
  92. callgraph. The perf.data file must have been obtained using
  93. perf c2c record --call-graph lbr.
  94. Disabled by default. In common cases with call stack overflows,
  95. it can recreate better call stacks than the default lbr call stack
  96. output. But this approach is not full proof. There can be cases
  97. where it creates incorrect call stacks from incorrect matches.
  98. The known limitations include exception handing such as
  99. setjmp/longjmp will have calls/returns not match.
  100. C2C RECORD
  101. ----------
  102. The perf c2c record command setup options related to HITM cacheline analysis
  103. and calls standard perf record command.
  104. Following perf record options are configured by default:
  105. (check perf record man page for details)
  106. -W,-d,--phys-data,--sample-cpu
  107. Unless specified otherwise with '-e' option, following events are monitored by
  108. default on Intel:
  109. cpu/mem-loads,ldlat=30/P
  110. cpu/mem-stores/P
  111. following on AMD:
  112. ibs_op//
  113. and following on PowerPC:
  114. cpu/mem-loads/
  115. cpu/mem-stores/
  116. User can pass any 'perf record' option behind '--' mark, like (to enable
  117. callchains and system wide monitoring):
  118. $ perf c2c record -- -g -a
  119. Please check RECORD OPTIONS section for specific c2c record options.
  120. C2C REPORT
  121. ----------
  122. The perf c2c report command displays shared data analysis. It comes in two
  123. display modes: stdio and tui (default).
  124. The report command workflow is following:
  125. - sort all the data based on the cacheline address
  126. - store access details for each cacheline
  127. - sort all cachelines based on user settings
  128. - display data
  129. In general perf report output consist of 2 basic views:
  130. 1) most expensive cachelines list
  131. 2) offsets details for each cacheline
  132. For each cacheline in the 1) list we display following data:
  133. (Both stdio and TUI modes follow the same fields output)
  134. Index
  135. - zero based index to identify the cacheline
  136. Cacheline
  137. - cacheline address (hex number)
  138. Rmt/Lcl Hitm (Display with HITM types)
  139. - cacheline percentage of all Remote/Local HITM accesses
  140. Peer Snoop (Display with peer type)
  141. - cacheline percentage of all peer accesses
  142. LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
  143. - count of Total/Local/Remote load HITMs
  144. Load Peer - Total, Local, Remote (For display with peer type)
  145. - count of Total/Local/Remote load from peer cache or DRAM
  146. Total records
  147. - sum of all cachelines accesses
  148. Total loads
  149. - sum of all load accesses
  150. Total stores
  151. - sum of all store accesses
  152. Store Reference - L1Hit, L1Miss, N/A
  153. L1Hit - store accesses that hit L1
  154. L1Miss - store accesses that missed L1
  155. N/A - store accesses with memory level is not available
  156. Core Load Hit - FB, L1, L2
  157. - count of load hits in FB (Fill Buffer), L1 and L2 cache
  158. LLC Load Hit - LlcHit, LclHitm
  159. - count of LLC load accesses, includes LLC hits and LLC HITMs
  160. RMT Load Hit - RmtHit, RmtHitm
  161. - count of remote load accesses, includes remote hits and remote HITMs;
  162. on Arm neoverse cores, RmtHit is used to account remote accesses,
  163. includes remote DRAM or any upward cache level in remote node
  164. Load Dram - Lcl, Rmt
  165. - count of local and remote DRAM accesses
  166. For each offset in the 2) list we display following data:
  167. HITM - Rmt, Lcl (Display with HITM types)
  168. - % of Remote/Local HITM accesses for given offset within cacheline
  169. Peer Snoop - Rmt, Lcl (Display with peer type)
  170. - % of Remote/Local peer accesses for given offset within cacheline
  171. Store Refs - L1 Hit, L1 Miss, N/A
  172. - % of store accesses that hit L1, missed L1 and N/A (no available) memory
  173. level for given offset within cacheline
  174. Data address - Offset
  175. - offset address
  176. Pid
  177. - pid of the process responsible for the accesses
  178. Tid
  179. - tid of the process responsible for the accesses
  180. Code address
  181. - code address responsible for the accesses
  182. cycles - rmt hitm, lcl hitm, load (Display with HITM types)
  183. - sum of cycles for given accesses - Remote/Local HITM and generic load
  184. cycles - rmt peer, lcl peer, load (Display with peer type)
  185. - sum of cycles for given accesses - Remote/Local peer load and generic load
  186. cpu cnt
  187. - number of cpus that participated on the access
  188. Symbol
  189. - code symbol related to the 'Code address' value
  190. Shared Object
  191. - shared object name related to the 'Code address' value
  192. Source:Line
  193. - source information related to the 'Code address' value
  194. Node
  195. - nodes participating on the access (see NODE INFO section)
  196. NODE INFO
  197. ---------
  198. The 'Node' field displays nodes that accesses given cacheline
  199. offset. Its output comes in 3 flavors:
  200. - node IDs separated by ','
  201. - node IDs with stats for each ID, in following format:
  202. Node{cpus %hitms %stores} (Display with HITM types)
  203. Node{cpus %peers %stores} (Display with peer type)
  204. - node IDs with list of affected CPUs in following format:
  205. Node{cpu list}
  206. User can switch between above flavors with -N option or
  207. use 'n' key to interactively switch in TUI mode.
  208. COALESCE
  209. --------
  210. User can specify how to sort offsets for cacheline.
  211. Following fields are available and governs the final
  212. output fields set for cacheline offsets output:
  213. tid - coalesced by process TIDs
  214. pid - coalesced by process PIDs
  215. iaddr - coalesced by code address, following fields are displayed:
  216. Code address, Code symbol, Shared Object, Source line
  217. dso - coalesced by shared object
  218. By default the coalescing is setup with 'pid,iaddr'.
  219. STDIO OUTPUT
  220. ------------
  221. The stdio output displays data on standard output.
  222. Following tables are displayed:
  223. Trace Event Information
  224. - overall statistics of memory accesses
  225. Global Shared Cache Line Event Information
  226. - overall statistics on shared cachelines
  227. Shared Data Cache Line Table
  228. - list of most expensive cachelines
  229. Shared Cache Line Distribution Pareto
  230. - list of all accessed offsets for each cacheline
  231. TUI OUTPUT
  232. ----------
  233. The TUI output provides interactive interface to navigate
  234. through cachelines list and to display offset details.
  235. For details please refer to the help window by pressing '?' key.
  236. CREDITS
  237. -------
  238. Although Don Zickus, Dick Fowles and Joe Mario worked together
  239. to get this implemented, we got lots of early help from Arnaldo
  240. Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
  241. C2C BLOG
  242. --------
  243. Check Joe's blog on c2c tool for detailed use case explanation:
  244. https://joemario.github.io/blog/2016/09/01/c2c-blog/
  245. SEE ALSO
  246. --------
  247. linkperf:perf-record[1], linkperf:perf-mem[1]