wm8958-dsp2.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8958-dsp2.c -- WM8958 DSP2 support
  4. *
  5. * Copyright 2011 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <sound/soc.h>
  18. #include <sound/initval.h>
  19. #include <sound/tlv.h>
  20. #include <trace/events/asoc.h>
  21. #include <linux/mfd/wm8994/core.h>
  22. #include <linux/mfd/wm8994/registers.h>
  23. #include <linux/mfd/wm8994/pdata.h>
  24. #include <linux/mfd/wm8994/gpio.h>
  25. #include <asm/unaligned.h>
  26. #include "wm8994.h"
  27. #define WM_FW_BLOCK_INFO 0xff
  28. #define WM_FW_BLOCK_PM 0x00
  29. #define WM_FW_BLOCK_X 0x01
  30. #define WM_FW_BLOCK_Y 0x02
  31. #define WM_FW_BLOCK_Z 0x03
  32. #define WM_FW_BLOCK_I 0x06
  33. #define WM_FW_BLOCK_A 0x08
  34. #define WM_FW_BLOCK_C 0x0c
  35. static int wm8958_dsp2_fw(struct snd_soc_component *component, const char *name,
  36. const struct firmware *fw, bool check)
  37. {
  38. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  39. u64 data64;
  40. u32 data32;
  41. const u8 *data;
  42. char *str;
  43. size_t block_len, len;
  44. int ret = 0;
  45. /* Suppress unneeded downloads */
  46. if (wm8994->cur_fw == fw)
  47. return 0;
  48. if (fw->size < 32) {
  49. dev_err(component->dev, "%s: firmware too short (%zd bytes)\n",
  50. name, fw->size);
  51. goto err;
  52. }
  53. if (memcmp(fw->data, "WMFW", 4) != 0) {
  54. data32 = get_unaligned_be32(fw->data);
  55. dev_err(component->dev, "%s: firmware has bad file magic %08x\n",
  56. name, data32);
  57. goto err;
  58. }
  59. len = get_unaligned_be32(fw->data + 4);
  60. data32 = get_unaligned_be32(fw->data + 8);
  61. if ((data32 >> 24) & 0xff) {
  62. dev_err(component->dev, "%s: unsupported firmware version %d\n",
  63. name, (data32 >> 24) & 0xff);
  64. goto err;
  65. }
  66. if ((data32 & 0xffff) != 8958) {
  67. dev_err(component->dev, "%s: unsupported target device %d\n",
  68. name, data32 & 0xffff);
  69. goto err;
  70. }
  71. if (((data32 >> 16) & 0xff) != 0xc) {
  72. dev_err(component->dev, "%s: unsupported target core %d\n",
  73. name, (data32 >> 16) & 0xff);
  74. goto err;
  75. }
  76. if (check) {
  77. data64 = get_unaligned_be64(fw->data + 24);
  78. dev_info(component->dev, "%s timestamp %llx\n", name, data64);
  79. } else {
  80. snd_soc_component_write(component, 0x102, 0x2);
  81. snd_soc_component_write(component, 0x900, 0x2);
  82. }
  83. data = fw->data + len;
  84. len = fw->size - len;
  85. while (len) {
  86. if (len < 12) {
  87. dev_err(component->dev, "%s short data block of %zd\n",
  88. name, len);
  89. goto err;
  90. }
  91. block_len = get_unaligned_be32(data + 4);
  92. if (block_len + 8 > len) {
  93. dev_err(component->dev, "%zd byte block longer than file\n",
  94. block_len);
  95. goto err;
  96. }
  97. if (block_len == 0) {
  98. dev_err(component->dev, "Zero length block\n");
  99. goto err;
  100. }
  101. data32 = get_unaligned_be32(data);
  102. switch ((data32 >> 24) & 0xff) {
  103. case WM_FW_BLOCK_INFO:
  104. /* Informational text */
  105. if (!check)
  106. break;
  107. str = kzalloc(block_len + 1, GFP_KERNEL);
  108. if (str) {
  109. memcpy(str, data + 8, block_len);
  110. dev_info(component->dev, "%s: %s\n", name, str);
  111. kfree(str);
  112. } else {
  113. dev_err(component->dev, "Out of memory\n");
  114. }
  115. break;
  116. case WM_FW_BLOCK_PM:
  117. case WM_FW_BLOCK_X:
  118. case WM_FW_BLOCK_Y:
  119. case WM_FW_BLOCK_Z:
  120. case WM_FW_BLOCK_I:
  121. case WM_FW_BLOCK_A:
  122. case WM_FW_BLOCK_C:
  123. dev_dbg(component->dev, "%s: %zd bytes of %x@%x\n", name,
  124. block_len, (data32 >> 24) & 0xff,
  125. data32 & 0xffffff);
  126. if (check)
  127. break;
  128. data32 &= 0xffffff;
  129. wm8994_bulk_write(wm8994->wm8994,
  130. data32 & 0xffffff,
  131. block_len / 2,
  132. (void *)(data + 8));
  133. break;
  134. default:
  135. dev_warn(component->dev, "%s: unknown block type %d\n",
  136. name, (data32 >> 24) & 0xff);
  137. break;
  138. }
  139. /* Round up to the next 32 bit word */
  140. block_len += block_len % 4;
  141. data += block_len + 8;
  142. len -= block_len + 8;
  143. }
  144. if (!check) {
  145. dev_dbg(component->dev, "%s: download done\n", name);
  146. wm8994->cur_fw = fw;
  147. } else {
  148. dev_info(component->dev, "%s: got firmware\n", name);
  149. }
  150. goto ok;
  151. err:
  152. ret = -EINVAL;
  153. ok:
  154. if (!check) {
  155. snd_soc_component_write(component, 0x900, 0x0);
  156. snd_soc_component_write(component, 0x102, 0x0);
  157. }
  158. return ret;
  159. }
  160. static void wm8958_dsp_start_mbc(struct snd_soc_component *component, int path)
  161. {
  162. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  163. struct wm8994 *control = wm8994->wm8994;
  164. int i;
  165. /* If the DSP is already running then noop */
  166. if (snd_soc_component_read(component, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  167. return;
  168. /* If we have MBC firmware download it */
  169. if (wm8994->mbc)
  170. wm8958_dsp2_fw(component, "MBC", wm8994->mbc, false);
  171. snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
  172. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  173. /* If we've got user supplied MBC settings use them */
  174. if (control->pdata.num_mbc_cfgs) {
  175. struct wm8958_mbc_cfg *cfg
  176. = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
  177. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  178. snd_soc_component_write(component, i + WM8958_MBC_BAND_1_K_1,
  179. cfg->coeff_regs[i]);
  180. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  181. snd_soc_component_write(component,
  182. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  183. cfg->cutoff_regs[i]);
  184. }
  185. /* Run the DSP */
  186. snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
  187. WM8958_DSP2_RUNR);
  188. /* And we're off! */
  189. snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
  190. WM8958_MBC_ENA |
  191. WM8958_MBC_SEL_MASK,
  192. path << WM8958_MBC_SEL_SHIFT |
  193. WM8958_MBC_ENA);
  194. }
  195. static void wm8958_dsp_start_vss(struct snd_soc_component *component, int path)
  196. {
  197. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  198. struct wm8994 *control = wm8994->wm8994;
  199. int i, ena;
  200. if (wm8994->mbc_vss)
  201. wm8958_dsp2_fw(component, "MBC+VSS", wm8994->mbc_vss, false);
  202. snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
  203. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  204. /* If we've got user supplied settings use them */
  205. if (control->pdata.num_mbc_cfgs) {
  206. struct wm8958_mbc_cfg *cfg
  207. = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
  208. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  209. snd_soc_component_write(component, i + 0x2800,
  210. cfg->combined_regs[i]);
  211. }
  212. if (control->pdata.num_vss_cfgs) {
  213. struct wm8958_vss_cfg *cfg
  214. = &control->pdata.vss_cfgs[wm8994->vss_cfg];
  215. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  216. snd_soc_component_write(component, i + 0x2600, cfg->regs[i]);
  217. }
  218. if (control->pdata.num_vss_hpf_cfgs) {
  219. struct wm8958_vss_hpf_cfg *cfg
  220. = &control->pdata.vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  221. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  222. snd_soc_component_write(component, i + 0x2400, cfg->regs[i]);
  223. }
  224. /* Run the DSP */
  225. snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
  226. WM8958_DSP2_RUNR);
  227. /* Enable the algorithms we've selected */
  228. ena = 0;
  229. if (wm8994->mbc_ena[path])
  230. ena |= 0x8;
  231. if (wm8994->hpf2_ena[path])
  232. ena |= 0x4;
  233. if (wm8994->hpf1_ena[path])
  234. ena |= 0x2;
  235. if (wm8994->vss_ena[path])
  236. ena |= 0x1;
  237. snd_soc_component_write(component, 0x2201, ena);
  238. /* Switch the DSP into the data path */
  239. snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
  240. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  241. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  242. }
  243. static void wm8958_dsp_start_enh_eq(struct snd_soc_component *component, int path)
  244. {
  245. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  246. struct wm8994 *control = wm8994->wm8994;
  247. int i;
  248. wm8958_dsp2_fw(component, "ENH_EQ", wm8994->enh_eq, false);
  249. snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
  250. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  251. /* If we've got user supplied settings use them */
  252. if (control->pdata.num_enh_eq_cfgs) {
  253. struct wm8958_enh_eq_cfg *cfg
  254. = &control->pdata.enh_eq_cfgs[wm8994->enh_eq_cfg];
  255. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  256. snd_soc_component_write(component, i + 0x2200,
  257. cfg->regs[i]);
  258. }
  259. /* Run the DSP */
  260. snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
  261. WM8958_DSP2_RUNR);
  262. /* Switch the DSP into the data path */
  263. snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
  264. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  265. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  266. }
  267. static void wm8958_dsp_apply(struct snd_soc_component *component, int path, int start)
  268. {
  269. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  270. int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5);
  271. int ena, reg, aif;
  272. switch (path) {
  273. case 0:
  274. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  275. aif = 0;
  276. break;
  277. case 1:
  278. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  279. aif = 0;
  280. break;
  281. case 2:
  282. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  283. aif = 1;
  284. break;
  285. default:
  286. WARN(1, "Invalid path %d\n", path);
  287. return;
  288. }
  289. /* Do we have both an active AIF and an active algorithm? */
  290. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  291. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  292. wm8994->enh_eq_ena[path];
  293. if (!pwr_reg)
  294. ena = 0;
  295. reg = snd_soc_component_read(component, WM8958_DSP2_PROGRAM);
  296. dev_dbg(component->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  297. path, wm8994->dsp_active, start, pwr_reg, reg);
  298. if (start && ena) {
  299. /* If the DSP is already running then noop */
  300. if (reg & WM8958_DSP2_ENA)
  301. return;
  302. /* If either AIFnCLK is not yet enabled postpone */
  303. if (!(snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1)
  304. & WM8994_AIF1CLK_ENA_MASK) &&
  305. !(snd_soc_component_read(component, WM8994_AIF2_CLOCKING_1)
  306. & WM8994_AIF2CLK_ENA_MASK))
  307. return;
  308. /* Switch the clock over to the appropriate AIF */
  309. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  310. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  311. aif << WM8958_DSP2CLK_SRC_SHIFT |
  312. WM8958_DSP2CLK_ENA);
  313. if (wm8994->enh_eq_ena[path])
  314. wm8958_dsp_start_enh_eq(component, path);
  315. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  316. wm8994->hpf2_ena[path])
  317. wm8958_dsp_start_vss(component, path);
  318. else if (wm8994->mbc_ena[path])
  319. wm8958_dsp_start_mbc(component, path);
  320. wm8994->dsp_active = path;
  321. dev_dbg(component->dev, "DSP running in path %d\n", path);
  322. }
  323. if (!start && wm8994->dsp_active == path) {
  324. /* If the DSP is already stopped then noop */
  325. if (!(reg & WM8958_DSP2_ENA))
  326. return;
  327. snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
  328. WM8958_MBC_ENA, 0);
  329. snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
  330. WM8958_DSP2_STOP);
  331. snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
  332. WM8958_DSP2_ENA, 0);
  333. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  334. WM8958_DSP2CLK_ENA, 0);
  335. wm8994->dsp_active = -1;
  336. dev_dbg(component->dev, "DSP stopped\n");
  337. }
  338. }
  339. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  340. struct snd_kcontrol *kcontrol, int event)
  341. {
  342. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  343. struct wm8994 *control = dev_get_drvdata(component->dev->parent);
  344. int i;
  345. if (control->type != WM8958)
  346. return 0;
  347. switch (event) {
  348. case SND_SOC_DAPM_POST_PMU:
  349. case SND_SOC_DAPM_PRE_PMU:
  350. for (i = 0; i < 3; i++)
  351. wm8958_dsp_apply(component, i, 1);
  352. break;
  353. case SND_SOC_DAPM_POST_PMD:
  354. case SND_SOC_DAPM_PRE_PMD:
  355. for (i = 0; i < 3; i++)
  356. wm8958_dsp_apply(component, i, 0);
  357. break;
  358. }
  359. return 0;
  360. }
  361. /* Check if DSP2 is in use on another AIF */
  362. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  363. {
  364. int i;
  365. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  366. if (i == aif)
  367. continue;
  368. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  369. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  370. return 1;
  371. }
  372. return 0;
  373. }
  374. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  375. struct snd_ctl_elem_value *ucontrol)
  376. {
  377. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  378. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  379. struct wm8994 *control = wm8994->wm8994;
  380. int value = ucontrol->value.enumerated.item[0];
  381. int reg;
  382. /* Don't allow on the fly reconfiguration */
  383. reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
  384. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  385. return -EBUSY;
  386. if (value >= control->pdata.num_mbc_cfgs)
  387. return -EINVAL;
  388. wm8994->mbc_cfg = value;
  389. return 0;
  390. }
  391. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  392. struct snd_ctl_elem_value *ucontrol)
  393. {
  394. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  395. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  396. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  397. return 0;
  398. }
  399. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  400. struct snd_ctl_elem_info *uinfo)
  401. {
  402. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  403. uinfo->count = 1;
  404. uinfo->value.integer.min = 0;
  405. uinfo->value.integer.max = 1;
  406. return 0;
  407. }
  408. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  409. struct snd_ctl_elem_value *ucontrol)
  410. {
  411. int mbc = kcontrol->private_value;
  412. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  413. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  414. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  415. return 0;
  416. }
  417. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  418. struct snd_ctl_elem_value *ucontrol)
  419. {
  420. int mbc = kcontrol->private_value;
  421. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  422. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  423. if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
  424. return 0;
  425. if (ucontrol->value.integer.value[0] > 1)
  426. return -EINVAL;
  427. if (wm8958_dsp2_busy(wm8994, mbc)) {
  428. dev_dbg(component->dev, "DSP2 active on %d already\n", mbc);
  429. return -EBUSY;
  430. }
  431. if (wm8994->enh_eq_ena[mbc])
  432. return -EBUSY;
  433. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  434. wm8958_dsp_apply(component, mbc, wm8994->mbc_ena[mbc]);
  435. return 1;
  436. }
  437. #define WM8958_MBC_SWITCH(xname, xval) {\
  438. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  439. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  440. .info = wm8958_mbc_info, \
  441. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  442. .private_value = xval }
  443. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  444. struct snd_ctl_elem_value *ucontrol)
  445. {
  446. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  447. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  448. struct wm8994 *control = wm8994->wm8994;
  449. int value = ucontrol->value.enumerated.item[0];
  450. int reg;
  451. /* Don't allow on the fly reconfiguration */
  452. reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
  453. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  454. return -EBUSY;
  455. if (value >= control->pdata.num_vss_cfgs)
  456. return -EINVAL;
  457. wm8994->vss_cfg = value;
  458. return 0;
  459. }
  460. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  461. struct snd_ctl_elem_value *ucontrol)
  462. {
  463. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  464. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  465. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  466. return 0;
  467. }
  468. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  469. struct snd_ctl_elem_value *ucontrol)
  470. {
  471. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  472. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  473. struct wm8994 *control = wm8994->wm8994;
  474. int value = ucontrol->value.enumerated.item[0];
  475. int reg;
  476. /* Don't allow on the fly reconfiguration */
  477. reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
  478. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  479. return -EBUSY;
  480. if (value >= control->pdata.num_vss_hpf_cfgs)
  481. return -EINVAL;
  482. wm8994->vss_hpf_cfg = value;
  483. return 0;
  484. }
  485. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  486. struct snd_ctl_elem_value *ucontrol)
  487. {
  488. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  489. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  490. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  491. return 0;
  492. }
  493. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  494. struct snd_ctl_elem_info *uinfo)
  495. {
  496. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  497. uinfo->count = 1;
  498. uinfo->value.integer.min = 0;
  499. uinfo->value.integer.max = 1;
  500. return 0;
  501. }
  502. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  503. struct snd_ctl_elem_value *ucontrol)
  504. {
  505. int vss = kcontrol->private_value;
  506. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  507. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  508. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  509. return 0;
  510. }
  511. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  512. struct snd_ctl_elem_value *ucontrol)
  513. {
  514. int vss = kcontrol->private_value;
  515. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  516. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  517. if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
  518. return 0;
  519. if (ucontrol->value.integer.value[0] > 1)
  520. return -EINVAL;
  521. if (!wm8994->mbc_vss)
  522. return -ENODEV;
  523. if (wm8958_dsp2_busy(wm8994, vss)) {
  524. dev_dbg(component->dev, "DSP2 active on %d already\n", vss);
  525. return -EBUSY;
  526. }
  527. if (wm8994->enh_eq_ena[vss])
  528. return -EBUSY;
  529. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  530. wm8958_dsp_apply(component, vss, wm8994->vss_ena[vss]);
  531. return 1;
  532. }
  533. #define WM8958_VSS_SWITCH(xname, xval) {\
  534. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  535. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  536. .info = wm8958_vss_info, \
  537. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  538. .private_value = xval }
  539. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  540. struct snd_ctl_elem_info *uinfo)
  541. {
  542. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  543. uinfo->count = 1;
  544. uinfo->value.integer.min = 0;
  545. uinfo->value.integer.max = 1;
  546. return 0;
  547. }
  548. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  549. struct snd_ctl_elem_value *ucontrol)
  550. {
  551. int hpf = kcontrol->private_value;
  552. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  553. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  554. if (hpf < 3)
  555. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  556. else
  557. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  558. return 0;
  559. }
  560. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  561. struct snd_ctl_elem_value *ucontrol)
  562. {
  563. int hpf = kcontrol->private_value;
  564. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  565. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  566. if (hpf < 3) {
  567. if (wm8994->hpf1_ena[hpf % 3] ==
  568. ucontrol->value.integer.value[0])
  569. return 0;
  570. } else {
  571. if (wm8994->hpf2_ena[hpf % 3] ==
  572. ucontrol->value.integer.value[0])
  573. return 0;
  574. }
  575. if (ucontrol->value.integer.value[0] > 1)
  576. return -EINVAL;
  577. if (!wm8994->mbc_vss)
  578. return -ENODEV;
  579. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  580. dev_dbg(component->dev, "DSP2 active on %d already\n", hpf);
  581. return -EBUSY;
  582. }
  583. if (wm8994->enh_eq_ena[hpf % 3])
  584. return -EBUSY;
  585. if (hpf < 3)
  586. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  587. else
  588. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  589. wm8958_dsp_apply(component, hpf % 3, ucontrol->value.integer.value[0]);
  590. return 1;
  591. }
  592. #define WM8958_HPF_SWITCH(xname, xval) {\
  593. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  594. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  595. .info = wm8958_hpf_info, \
  596. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  597. .private_value = xval }
  598. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  599. struct snd_ctl_elem_value *ucontrol)
  600. {
  601. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  602. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  603. struct wm8994 *control = wm8994->wm8994;
  604. int value = ucontrol->value.enumerated.item[0];
  605. int reg;
  606. /* Don't allow on the fly reconfiguration */
  607. reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
  608. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  609. return -EBUSY;
  610. if (value >= control->pdata.num_enh_eq_cfgs)
  611. return -EINVAL;
  612. wm8994->enh_eq_cfg = value;
  613. return 0;
  614. }
  615. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  616. struct snd_ctl_elem_value *ucontrol)
  617. {
  618. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  619. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  620. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  621. return 0;
  622. }
  623. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  624. struct snd_ctl_elem_info *uinfo)
  625. {
  626. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  627. uinfo->count = 1;
  628. uinfo->value.integer.min = 0;
  629. uinfo->value.integer.max = 1;
  630. return 0;
  631. }
  632. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  633. struct snd_ctl_elem_value *ucontrol)
  634. {
  635. int eq = kcontrol->private_value;
  636. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  637. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  638. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  639. return 0;
  640. }
  641. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  642. struct snd_ctl_elem_value *ucontrol)
  643. {
  644. int eq = kcontrol->private_value;
  645. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  646. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  647. if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
  648. return 0;
  649. if (ucontrol->value.integer.value[0] > 1)
  650. return -EINVAL;
  651. if (!wm8994->enh_eq)
  652. return -ENODEV;
  653. if (wm8958_dsp2_busy(wm8994, eq)) {
  654. dev_dbg(component->dev, "DSP2 active on %d already\n", eq);
  655. return -EBUSY;
  656. }
  657. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  658. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  659. return -EBUSY;
  660. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  661. wm8958_dsp_apply(component, eq, ucontrol->value.integer.value[0]);
  662. return 1;
  663. }
  664. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  665. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  666. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  667. .info = wm8958_enh_eq_info, \
  668. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  669. .private_value = xval }
  670. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  671. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  672. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  673. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  674. };
  675. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  676. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  677. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  678. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  679. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  680. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  681. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  682. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  683. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  684. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  685. };
  686. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  687. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  688. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  689. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  690. };
  691. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  692. {
  693. struct snd_soc_component *component = context;
  694. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  695. if (fw && (wm8958_dsp2_fw(component, "ENH_EQ", fw, true) == 0)) {
  696. mutex_lock(&wm8994->fw_lock);
  697. wm8994->enh_eq = fw;
  698. mutex_unlock(&wm8994->fw_lock);
  699. }
  700. }
  701. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  702. {
  703. struct snd_soc_component *component = context;
  704. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  705. if (fw && (wm8958_dsp2_fw(component, "MBC+VSS", fw, true) == 0)) {
  706. mutex_lock(&wm8994->fw_lock);
  707. wm8994->mbc_vss = fw;
  708. mutex_unlock(&wm8994->fw_lock);
  709. }
  710. }
  711. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  712. {
  713. struct snd_soc_component *component = context;
  714. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  715. if (fw && (wm8958_dsp2_fw(component, "MBC", fw, true) == 0)) {
  716. mutex_lock(&wm8994->fw_lock);
  717. wm8994->mbc = fw;
  718. mutex_unlock(&wm8994->fw_lock);
  719. }
  720. }
  721. void wm8958_dsp2_init(struct snd_soc_component *component)
  722. {
  723. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  724. struct wm8994 *control = wm8994->wm8994;
  725. struct wm8994_pdata *pdata = &control->pdata;
  726. int ret, i;
  727. wm8994->dsp_active = -1;
  728. snd_soc_add_component_controls(component, wm8958_mbc_snd_controls,
  729. ARRAY_SIZE(wm8958_mbc_snd_controls));
  730. snd_soc_add_component_controls(component, wm8958_vss_snd_controls,
  731. ARRAY_SIZE(wm8958_vss_snd_controls));
  732. snd_soc_add_component_controls(component, wm8958_enh_eq_snd_controls,
  733. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  734. /* We don't *require* firmware and don't want to delay boot */
  735. request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
  736. "wm8958_mbc.wfw", component->dev, GFP_KERNEL,
  737. component, wm8958_mbc_loaded);
  738. request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
  739. "wm8958_mbc_vss.wfw", component->dev, GFP_KERNEL,
  740. component, wm8958_mbc_vss_loaded);
  741. request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
  742. "wm8958_enh_eq.wfw", component->dev, GFP_KERNEL,
  743. component, wm8958_enh_eq_loaded);
  744. if (pdata->num_mbc_cfgs) {
  745. struct snd_kcontrol_new mbc_control[] = {
  746. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  747. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  748. };
  749. /* We need an array of texts for the enum API */
  750. wm8994->mbc_texts = kmalloc_array(pdata->num_mbc_cfgs,
  751. sizeof(char *),
  752. GFP_KERNEL);
  753. if (!wm8994->mbc_texts)
  754. return;
  755. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  756. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  757. wm8994->mbc_enum.items = pdata->num_mbc_cfgs;
  758. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  759. ret = snd_soc_add_component_controls(wm8994->hubs.component,
  760. mbc_control, 1);
  761. if (ret != 0)
  762. dev_err(wm8994->hubs.component->dev,
  763. "Failed to add MBC mode controls: %d\n", ret);
  764. }
  765. if (pdata->num_vss_cfgs) {
  766. struct snd_kcontrol_new vss_control[] = {
  767. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  768. wm8958_get_vss_enum, wm8958_put_vss_enum),
  769. };
  770. /* We need an array of texts for the enum API */
  771. wm8994->vss_texts = kmalloc_array(pdata->num_vss_cfgs,
  772. sizeof(char *),
  773. GFP_KERNEL);
  774. if (!wm8994->vss_texts)
  775. return;
  776. for (i = 0; i < pdata->num_vss_cfgs; i++)
  777. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  778. wm8994->vss_enum.items = pdata->num_vss_cfgs;
  779. wm8994->vss_enum.texts = wm8994->vss_texts;
  780. ret = snd_soc_add_component_controls(wm8994->hubs.component,
  781. vss_control, 1);
  782. if (ret != 0)
  783. dev_err(wm8994->hubs.component->dev,
  784. "Failed to add VSS mode controls: %d\n", ret);
  785. }
  786. if (pdata->num_vss_hpf_cfgs) {
  787. struct snd_kcontrol_new hpf_control[] = {
  788. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  789. wm8958_get_vss_hpf_enum,
  790. wm8958_put_vss_hpf_enum),
  791. };
  792. /* We need an array of texts for the enum API */
  793. wm8994->vss_hpf_texts = kmalloc_array(pdata->num_vss_hpf_cfgs,
  794. sizeof(char *),
  795. GFP_KERNEL);
  796. if (!wm8994->vss_hpf_texts)
  797. return;
  798. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  799. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  800. wm8994->vss_hpf_enum.items = pdata->num_vss_hpf_cfgs;
  801. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  802. ret = snd_soc_add_component_controls(wm8994->hubs.component,
  803. hpf_control, 1);
  804. if (ret != 0)
  805. dev_err(wm8994->hubs.component->dev,
  806. "Failed to add VSS HPFmode controls: %d\n",
  807. ret);
  808. }
  809. if (pdata->num_enh_eq_cfgs) {
  810. struct snd_kcontrol_new eq_control[] = {
  811. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  812. wm8958_get_enh_eq_enum,
  813. wm8958_put_enh_eq_enum),
  814. };
  815. /* We need an array of texts for the enum API */
  816. wm8994->enh_eq_texts = kmalloc_array(pdata->num_enh_eq_cfgs,
  817. sizeof(char *),
  818. GFP_KERNEL);
  819. if (!wm8994->enh_eq_texts)
  820. return;
  821. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  822. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  823. wm8994->enh_eq_enum.items = pdata->num_enh_eq_cfgs;
  824. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  825. ret = snd_soc_add_component_controls(wm8994->hubs.component,
  826. eq_control, 1);
  827. if (ret != 0)
  828. dev_err(wm8994->hubs.component->dev,
  829. "Failed to add enhanced EQ controls: %d\n",
  830. ret);
  831. }
  832. }