rt715-sdca.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // rt715-sdca.c -- rt715 ALSA SoC audio driver
  4. //
  5. // Copyright(c) 2020 Realtek Semiconductor Corp.
  6. //
  7. //
  8. //
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/pm.h>
  15. #include <linux/soundwire/sdw.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/platform_device.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/soc-dapm.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include <linux/soundwire/sdw_registers.h>
  27. #include "rt715-sdca.h"
  28. static int rt715_sdca_index_write(struct rt715_sdca_priv *rt715,
  29. unsigned int nid, unsigned int reg, unsigned int value)
  30. {
  31. struct regmap *regmap = rt715->mbq_regmap;
  32. unsigned int addr;
  33. int ret;
  34. addr = (nid << 20) | reg;
  35. ret = regmap_write(regmap, addr, value);
  36. if (ret < 0)
  37. dev_err(&rt715->slave->dev,
  38. "Failed to set private value: %08x <= %04x %d\n", ret, addr,
  39. value);
  40. return ret;
  41. }
  42. static int rt715_sdca_index_read(struct rt715_sdca_priv *rt715,
  43. unsigned int nid, unsigned int reg, unsigned int *value)
  44. {
  45. struct regmap *regmap = rt715->mbq_regmap;
  46. unsigned int addr;
  47. int ret;
  48. addr = (nid << 20) | reg;
  49. ret = regmap_read(regmap, addr, value);
  50. if (ret < 0)
  51. dev_err(&rt715->slave->dev,
  52. "Failed to get private value: %06x => %04x ret=%d\n",
  53. addr, *value, ret);
  54. return ret;
  55. }
  56. static int rt715_sdca_index_update_bits(struct rt715_sdca_priv *rt715,
  57. unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
  58. {
  59. unsigned int tmp;
  60. int ret;
  61. ret = rt715_sdca_index_read(rt715, nid, reg, &tmp);
  62. if (ret < 0)
  63. return ret;
  64. set_mask_bits(&tmp, mask, val);
  65. return rt715_sdca_index_write(rt715, nid, reg, tmp);
  66. }
  67. static inline unsigned int rt715_sdca_vol_gain(unsigned int u_ctrl_val,
  68. unsigned int vol_max, unsigned int vol_gain_sft)
  69. {
  70. unsigned int val;
  71. if (u_ctrl_val > vol_max)
  72. u_ctrl_val = vol_max;
  73. val = u_ctrl_val;
  74. u_ctrl_val =
  75. ((abs(u_ctrl_val - vol_gain_sft) * RT715_SDCA_DB_STEP) << 8) / 1000;
  76. if (val <= vol_gain_sft) {
  77. u_ctrl_val = ~u_ctrl_val;
  78. u_ctrl_val += 1;
  79. }
  80. u_ctrl_val &= 0xffff;
  81. return u_ctrl_val;
  82. }
  83. static inline unsigned int rt715_sdca_boost_gain(unsigned int u_ctrl_val,
  84. unsigned int b_max, unsigned int b_gain_sft)
  85. {
  86. if (u_ctrl_val > b_max)
  87. u_ctrl_val = b_max;
  88. return (u_ctrl_val * 10) << b_gain_sft;
  89. }
  90. static inline unsigned int rt715_sdca_get_gain(unsigned int reg_val,
  91. unsigned int gain_sft)
  92. {
  93. unsigned int neg_flag = 0;
  94. if (reg_val & BIT(15)) {
  95. reg_val = ~(reg_val - 1) & 0xffff;
  96. neg_flag = 1;
  97. }
  98. reg_val *= 1000;
  99. reg_val >>= 8;
  100. if (neg_flag)
  101. reg_val = gain_sft - reg_val / RT715_SDCA_DB_STEP;
  102. else
  103. reg_val = gain_sft + reg_val / RT715_SDCA_DB_STEP;
  104. return reg_val;
  105. }
  106. /* SDCA Volume/Boost control */
  107. static int rt715_sdca_set_amp_gain_put(struct snd_kcontrol *kcontrol,
  108. struct snd_ctl_elem_value *ucontrol)
  109. {
  110. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  111. struct soc_mixer_control *mc =
  112. (struct soc_mixer_control *)kcontrol->private_value;
  113. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  114. unsigned int gain_val, i, k_changed = 0;
  115. int ret;
  116. for (i = 0; i < 2; i++) {
  117. if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_orig[i]) {
  118. k_changed = 1;
  119. break;
  120. }
  121. }
  122. for (i = 0; i < 2; i++) {
  123. rt715->kctl_2ch_orig[i] = ucontrol->value.integer.value[i];
  124. gain_val =
  125. rt715_sdca_vol_gain(ucontrol->value.integer.value[i], mc->max,
  126. mc->shift);
  127. ret = regmap_write(rt715->mbq_regmap, mc->reg + i, gain_val);
  128. if (ret != 0) {
  129. dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
  130. mc->reg + i, gain_val);
  131. return ret;
  132. }
  133. }
  134. return k_changed;
  135. }
  136. static int rt715_sdca_set_amp_gain_4ch_put(struct snd_kcontrol *kcontrol,
  137. struct snd_ctl_elem_value *ucontrol)
  138. {
  139. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  140. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  141. struct rt715_sdca_kcontrol_private *p =
  142. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  143. unsigned int reg_base = p->reg_base, k_changed = 0;
  144. const unsigned int gain_sft = 0x2f;
  145. unsigned int gain_val, i;
  146. int ret;
  147. for (i = 0; i < 4; i++) {
  148. if (ucontrol->value.integer.value[i] != rt715->kctl_4ch_orig[i]) {
  149. k_changed = 1;
  150. break;
  151. }
  152. }
  153. for (i = 0; i < 4; i++) {
  154. rt715->kctl_4ch_orig[i] = ucontrol->value.integer.value[i];
  155. gain_val =
  156. rt715_sdca_vol_gain(ucontrol->value.integer.value[i], p->max,
  157. gain_sft);
  158. ret = regmap_write(rt715->mbq_regmap, reg_base + i,
  159. gain_val);
  160. if (ret != 0) {
  161. dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
  162. reg_base + i, gain_val);
  163. return ret;
  164. }
  165. }
  166. return k_changed;
  167. }
  168. static int rt715_sdca_set_amp_gain_8ch_put(struct snd_kcontrol *kcontrol,
  169. struct snd_ctl_elem_value *ucontrol)
  170. {
  171. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  172. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  173. struct rt715_sdca_kcontrol_private *p =
  174. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  175. unsigned int reg_base = p->reg_base, i, k_changed = 0;
  176. const unsigned int gain_sft = 8;
  177. unsigned int gain_val, reg;
  178. int ret;
  179. for (i = 0; i < 8; i++) {
  180. if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_orig[i]) {
  181. k_changed = 1;
  182. break;
  183. }
  184. }
  185. for (i = 0; i < 8; i++) {
  186. rt715->kctl_8ch_orig[i] = ucontrol->value.integer.value[i];
  187. gain_val =
  188. rt715_sdca_boost_gain(ucontrol->value.integer.value[i], p->max,
  189. gain_sft);
  190. reg = i < 7 ? reg_base + i : (reg_base - 1) | BIT(15);
  191. ret = regmap_write(rt715->mbq_regmap, reg, gain_val);
  192. if (ret != 0) {
  193. dev_err(component->dev, "Failed to write 0x%x=0x%x\n",
  194. reg, gain_val);
  195. return ret;
  196. }
  197. }
  198. return k_changed;
  199. }
  200. static int rt715_sdca_set_amp_gain_get(struct snd_kcontrol *kcontrol,
  201. struct snd_ctl_elem_value *ucontrol)
  202. {
  203. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  204. struct soc_mixer_control *mc =
  205. (struct soc_mixer_control *)kcontrol->private_value;
  206. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  207. unsigned int val, i;
  208. int ret;
  209. for (i = 0; i < 2; i++) {
  210. ret = regmap_read(rt715->mbq_regmap, mc->reg + i, &val);
  211. if (ret < 0) {
  212. dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
  213. mc->reg + i, ret);
  214. return ret;
  215. }
  216. ucontrol->value.integer.value[i] = rt715_sdca_get_gain(val, mc->shift);
  217. }
  218. return 0;
  219. }
  220. static int rt715_sdca_set_amp_gain_4ch_get(struct snd_kcontrol *kcontrol,
  221. struct snd_ctl_elem_value *ucontrol)
  222. {
  223. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  224. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  225. struct rt715_sdca_kcontrol_private *p =
  226. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  227. unsigned int reg_base = p->reg_base, i;
  228. const unsigned int gain_sft = 0x2f;
  229. unsigned int val;
  230. int ret;
  231. for (i = 0; i < 4; i++) {
  232. ret = regmap_read(rt715->mbq_regmap, reg_base + i, &val);
  233. if (ret < 0) {
  234. dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
  235. reg_base + i, ret);
  236. return ret;
  237. }
  238. ucontrol->value.integer.value[i] = rt715_sdca_get_gain(val, gain_sft);
  239. }
  240. return 0;
  241. }
  242. static int rt715_sdca_set_amp_gain_8ch_get(struct snd_kcontrol *kcontrol,
  243. struct snd_ctl_elem_value *ucontrol)
  244. {
  245. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  246. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  247. struct rt715_sdca_kcontrol_private *p =
  248. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  249. unsigned int reg_base = p->reg_base;
  250. const unsigned int gain_sft = 8;
  251. unsigned int val_l, val_r;
  252. unsigned int i, reg;
  253. int ret;
  254. for (i = 0; i < 8; i += 2) {
  255. ret = regmap_read(rt715->mbq_regmap, reg_base + i, &val_l);
  256. if (ret < 0) {
  257. dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
  258. reg_base + i, ret);
  259. return ret;
  260. }
  261. ucontrol->value.integer.value[i] = (val_l >> gain_sft) / 10;
  262. reg = (i == 6) ? (reg_base - 1) | BIT(15) : reg_base + 1 + i;
  263. ret = regmap_read(rt715->mbq_regmap, reg, &val_r);
  264. if (ret < 0) {
  265. dev_err(component->dev, "Failed to read 0x%x, ret=%d\n",
  266. reg, ret);
  267. return ret;
  268. }
  269. ucontrol->value.integer.value[i + 1] = (val_r >> gain_sft) / 10;
  270. }
  271. return 0;
  272. }
  273. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -17625, 375, 0);
  274. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  275. static int rt715_sdca_get_volsw(struct snd_kcontrol *kcontrol,
  276. struct snd_ctl_elem_value *ucontrol)
  277. {
  278. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  279. struct rt715_sdca_kcontrol_private *p =
  280. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  281. unsigned int reg_base = p->reg_base;
  282. unsigned int invert = p->invert, i;
  283. int val;
  284. for (i = 0; i < p->count; i += 2) {
  285. val = snd_soc_component_read(component, reg_base + i);
  286. if (val < 0)
  287. return -EINVAL;
  288. ucontrol->value.integer.value[i] = invert ? p->max - val : val;
  289. val = snd_soc_component_read(component, reg_base + 1 + i);
  290. if (val < 0)
  291. return -EINVAL;
  292. ucontrol->value.integer.value[i + 1] =
  293. invert ? p->max - val : val;
  294. }
  295. return 0;
  296. }
  297. static int rt715_sdca_put_volsw(struct snd_kcontrol *kcontrol,
  298. struct snd_ctl_elem_value *ucontrol)
  299. {
  300. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  301. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  302. struct rt715_sdca_kcontrol_private *p =
  303. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  304. unsigned int val[4] = {0}, val_mask, i, k_changed = 0;
  305. unsigned int reg = p->reg_base;
  306. unsigned int shift = p->shift;
  307. unsigned int max = p->max;
  308. unsigned int mask = (1 << fls(max)) - 1;
  309. unsigned int invert = p->invert;
  310. int err;
  311. for (i = 0; i < 4; i++) {
  312. if (ucontrol->value.integer.value[i] != rt715->kctl_switch_orig[i]) {
  313. k_changed = 1;
  314. break;
  315. }
  316. }
  317. for (i = 0; i < 2; i++) {
  318. rt715->kctl_switch_orig[i * 2] = ucontrol->value.integer.value[i * 2];
  319. val[i * 2] = ucontrol->value.integer.value[i * 2] & mask;
  320. if (invert)
  321. val[i * 2] = max - val[i * 2];
  322. val_mask = mask << shift;
  323. val[i * 2] <<= shift;
  324. rt715->kctl_switch_orig[i * 2 + 1] =
  325. ucontrol->value.integer.value[i * 2 + 1];
  326. val[i * 2 + 1] =
  327. ucontrol->value.integer.value[i * 2 + 1] & mask;
  328. if (invert)
  329. val[i * 2 + 1] = max - val[i * 2 + 1];
  330. val[i * 2 + 1] <<= shift;
  331. err = snd_soc_component_update_bits(component, reg + i * 2, val_mask,
  332. val[i * 2]);
  333. if (err < 0)
  334. return err;
  335. err = snd_soc_component_update_bits(component, reg + 1 + i * 2,
  336. val_mask, val[i * 2 + 1]);
  337. if (err < 0)
  338. return err;
  339. }
  340. return k_changed;
  341. }
  342. static int rt715_sdca_fu_info(struct snd_kcontrol *kcontrol,
  343. struct snd_ctl_elem_info *uinfo)
  344. {
  345. struct rt715_sdca_kcontrol_private *p =
  346. (struct rt715_sdca_kcontrol_private *)kcontrol->private_value;
  347. if (p->max == 1)
  348. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  349. else
  350. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  351. uinfo->count = p->count;
  352. uinfo->value.integer.min = 0;
  353. uinfo->value.integer.max = p->max;
  354. return 0;
  355. }
  356. #define RT715_SDCA_PR_VALUE(xreg_base, xcount, xmax, xshift, xinvert) \
  357. ((unsigned long)&(struct rt715_sdca_kcontrol_private) \
  358. {.reg_base = xreg_base, .count = xcount, .max = xmax, \
  359. .shift = xshift, .invert = xinvert})
  360. #define RT715_SDCA_FU_CTRL(xname, reg_base, xshift, xmax, xinvert, xcount) \
  361. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  362. .info = rt715_sdca_fu_info, \
  363. .get = rt715_sdca_get_volsw, \
  364. .put = rt715_sdca_put_volsw, \
  365. .private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, \
  366. xshift, xinvert)}
  367. #define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
  368. xhandler_get, xhandler_put) \
  369. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  370. .info = snd_soc_info_volsw, \
  371. .get = xhandler_get, .put = xhandler_put, \
  372. .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
  373. xmax, xinvert) }
  374. #define RT715_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
  375. xhandler_put, tlv_array, xcount, xmax) \
  376. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  377. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
  378. SNDRV_CTL_ELEM_ACCESS_READWRITE, \
  379. .tlv.p = (tlv_array), \
  380. .info = rt715_sdca_fu_info, \
  381. .get = xhandler_get, .put = xhandler_put, \
  382. .private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, 0, 0) }
  383. #define RT715_SDCA_BOOST_EXT_TLV(xname, reg_base, xhandler_get,\
  384. xhandler_put, tlv_array, xcount, xmax) \
  385. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  386. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
  387. SNDRV_CTL_ELEM_ACCESS_READWRITE, \
  388. .tlv.p = (tlv_array), \
  389. .info = rt715_sdca_fu_info, \
  390. .get = xhandler_get, .put = xhandler_put, \
  391. .private_value = RT715_SDCA_PR_VALUE(reg_base, xcount, xmax, 0, 0) }
  392. static const struct snd_kcontrol_new rt715_sdca_snd_controls[] = {
  393. /* Capture switch */
  394. SOC_DOUBLE_R("FU0A Capture Switch",
  395. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
  396. RT715_SDCA_FU_MUTE_CTRL, CH_01),
  397. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
  398. RT715_SDCA_FU_MUTE_CTRL, CH_02),
  399. 0, 1, 1),
  400. RT715_SDCA_FU_CTRL("FU02 Capture Switch",
  401. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL,
  402. RT715_SDCA_FU_MUTE_CTRL, CH_01),
  403. 0, 1, 1, 4),
  404. RT715_SDCA_FU_CTRL("FU06 Capture Switch",
  405. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC10_11_VOL,
  406. RT715_SDCA_FU_MUTE_CTRL, CH_01),
  407. 0, 1, 1, 4),
  408. /* Volume Control */
  409. SOC_DOUBLE_R_EXT_TLV("FU0A Capture Volume",
  410. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
  411. RT715_SDCA_FU_VOL_CTRL, CH_01),
  412. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC7_27_VOL,
  413. RT715_SDCA_FU_VOL_CTRL, CH_02),
  414. 0x2f, 0x7f, 0,
  415. rt715_sdca_set_amp_gain_get, rt715_sdca_set_amp_gain_put,
  416. in_vol_tlv),
  417. RT715_SDCA_EXT_TLV("FU02 Capture Volume",
  418. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL,
  419. RT715_SDCA_FU_VOL_CTRL, CH_01),
  420. rt715_sdca_set_amp_gain_4ch_get,
  421. rt715_sdca_set_amp_gain_4ch_put,
  422. in_vol_tlv, 4, 0x7f),
  423. RT715_SDCA_EXT_TLV("FU06 Capture Volume",
  424. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC10_11_VOL,
  425. RT715_SDCA_FU_VOL_CTRL, CH_01),
  426. rt715_sdca_set_amp_gain_4ch_get,
  427. rt715_sdca_set_amp_gain_4ch_put,
  428. in_vol_tlv, 4, 0x7f),
  429. /* MIC Boost Control */
  430. RT715_SDCA_BOOST_EXT_TLV("FU0E Boost",
  431. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_DMIC_GAIN_EN,
  432. RT715_SDCA_FU_DMIC_GAIN_CTRL, CH_01),
  433. rt715_sdca_set_amp_gain_8ch_get,
  434. rt715_sdca_set_amp_gain_8ch_put,
  435. mic_vol_tlv, 8, 3),
  436. RT715_SDCA_BOOST_EXT_TLV("FU0C Boost",
  437. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_AMIC_GAIN_EN,
  438. RT715_SDCA_FU_DMIC_GAIN_CTRL, CH_01),
  439. rt715_sdca_set_amp_gain_8ch_get,
  440. rt715_sdca_set_amp_gain_8ch_put,
  441. mic_vol_tlv, 8, 3),
  442. };
  443. static int rt715_sdca_mux_get(struct snd_kcontrol *kcontrol,
  444. struct snd_ctl_elem_value *ucontrol)
  445. {
  446. struct snd_soc_component *component =
  447. snd_soc_dapm_kcontrol_component(kcontrol);
  448. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  449. unsigned int val, mask_sft;
  450. if (strstr(ucontrol->id.name, "ADC 22 Mux"))
  451. mask_sft = 12;
  452. else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
  453. mask_sft = 8;
  454. else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
  455. mask_sft = 4;
  456. else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
  457. mask_sft = 0;
  458. else
  459. return -EINVAL;
  460. rt715_sdca_index_read(rt715, RT715_VENDOR_HDA_CTL,
  461. RT715_HDA_LEGACY_MUX_CTL1, &val);
  462. val = (val >> mask_sft) & 0xf;
  463. /*
  464. * The first two indices of ADC Mux 24/25 are routed to the same
  465. * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
  466. * To have a unique set of inputs, we skip the index1 of the muxes.
  467. */
  468. if ((strstr(ucontrol->id.name, "ADC 24 Mux") ||
  469. strstr(ucontrol->id.name, "ADC 25 Mux")) && val > 0)
  470. val -= 1;
  471. ucontrol->value.enumerated.item[0] = val;
  472. return 0;
  473. }
  474. static int rt715_sdca_mux_put(struct snd_kcontrol *kcontrol,
  475. struct snd_ctl_elem_value *ucontrol)
  476. {
  477. struct snd_soc_component *component =
  478. snd_soc_dapm_kcontrol_component(kcontrol);
  479. struct snd_soc_dapm_context *dapm =
  480. snd_soc_dapm_kcontrol_dapm(kcontrol);
  481. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  482. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  483. unsigned int *item = ucontrol->value.enumerated.item;
  484. unsigned int val, val2 = 0, change, mask_sft;
  485. if (item[0] >= e->items)
  486. return -EINVAL;
  487. if (strstr(ucontrol->id.name, "ADC 22 Mux"))
  488. mask_sft = 12;
  489. else if (strstr(ucontrol->id.name, "ADC 23 Mux"))
  490. mask_sft = 8;
  491. else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
  492. mask_sft = 4;
  493. else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
  494. mask_sft = 0;
  495. else
  496. return -EINVAL;
  497. /* Verb ID = 0x701h, nid = e->reg */
  498. val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
  499. rt715_sdca_index_read(rt715, RT715_VENDOR_HDA_CTL,
  500. RT715_HDA_LEGACY_MUX_CTL1, &val2);
  501. val2 = (val2 >> mask_sft) & 0xf;
  502. change = val != val2;
  503. if (change)
  504. rt715_sdca_index_update_bits(rt715, RT715_VENDOR_HDA_CTL,
  505. RT715_HDA_LEGACY_MUX_CTL1, 0xf << mask_sft, val << mask_sft);
  506. snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL);
  507. return change;
  508. }
  509. static const char * const adc_22_23_mux_text[] = {
  510. "MIC1",
  511. "MIC2",
  512. "LINE1",
  513. "LINE2",
  514. "DMIC1",
  515. "DMIC2",
  516. "DMIC3",
  517. "DMIC4",
  518. };
  519. /*
  520. * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
  521. * 1 will be connected to the same dmic source, therefore we skip index 1 to
  522. * avoid misunderstanding on usage of dapm routing.
  523. */
  524. static int rt715_adc_24_25_values[] = {
  525. 0,
  526. 2,
  527. 3,
  528. 4,
  529. 5,
  530. };
  531. static const char * const adc_24_mux_text[] = {
  532. "MIC2",
  533. "DMIC1",
  534. "DMIC2",
  535. "DMIC3",
  536. "DMIC4",
  537. };
  538. static const char * const adc_25_mux_text[] = {
  539. "MIC1",
  540. "DMIC1",
  541. "DMIC2",
  542. "DMIC3",
  543. "DMIC4",
  544. };
  545. static SOC_ENUM_SINGLE_DECL(rt715_adc22_enum, SND_SOC_NOPM, 0,
  546. adc_22_23_mux_text);
  547. static SOC_ENUM_SINGLE_DECL(rt715_adc23_enum, SND_SOC_NOPM, 0,
  548. adc_22_23_mux_text);
  549. static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
  550. SND_SOC_NOPM, 0, 0xf,
  551. adc_24_mux_text, rt715_adc_24_25_values);
  552. static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
  553. SND_SOC_NOPM, 0, 0xf,
  554. adc_25_mux_text, rt715_adc_24_25_values);
  555. static const struct snd_kcontrol_new rt715_adc22_mux =
  556. SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
  557. rt715_sdca_mux_get, rt715_sdca_mux_put);
  558. static const struct snd_kcontrol_new rt715_adc23_mux =
  559. SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
  560. rt715_sdca_mux_get, rt715_sdca_mux_put);
  561. static const struct snd_kcontrol_new rt715_adc24_mux =
  562. SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
  563. rt715_sdca_mux_get, rt715_sdca_mux_put);
  564. static const struct snd_kcontrol_new rt715_adc25_mux =
  565. SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
  566. rt715_sdca_mux_get, rt715_sdca_mux_put);
  567. static int rt715_sdca_pde23_24_event(struct snd_soc_dapm_widget *w,
  568. struct snd_kcontrol *kcontrol, int event)
  569. {
  570. struct snd_soc_component *component =
  571. snd_soc_dapm_to_component(w->dapm);
  572. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  573. switch (event) {
  574. case SND_SOC_DAPM_POST_PMU:
  575. regmap_write(rt715->regmap,
  576. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CREQ_POW_EN,
  577. RT715_SDCA_REQ_POW_CTRL,
  578. CH_00), 0x00);
  579. break;
  580. case SND_SOC_DAPM_PRE_PMD:
  581. regmap_write(rt715->regmap,
  582. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CREQ_POW_EN,
  583. RT715_SDCA_REQ_POW_CTRL,
  584. CH_00), 0x03);
  585. break;
  586. }
  587. return 0;
  588. }
  589. static const struct snd_soc_dapm_widget rt715_sdca_dapm_widgets[] = {
  590. SND_SOC_DAPM_INPUT("DMIC1"),
  591. SND_SOC_DAPM_INPUT("DMIC2"),
  592. SND_SOC_DAPM_INPUT("DMIC3"),
  593. SND_SOC_DAPM_INPUT("DMIC4"),
  594. SND_SOC_DAPM_INPUT("MIC1"),
  595. SND_SOC_DAPM_INPUT("MIC2"),
  596. SND_SOC_DAPM_INPUT("LINE1"),
  597. SND_SOC_DAPM_INPUT("LINE2"),
  598. SND_SOC_DAPM_SUPPLY("PDE23_24", SND_SOC_NOPM, 0, 0,
  599. rt715_sdca_pde23_24_event,
  600. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  601. SND_SOC_DAPM_ADC("ADC 07", NULL, SND_SOC_NOPM, 4, 0),
  602. SND_SOC_DAPM_ADC("ADC 08", NULL, SND_SOC_NOPM, 4, 0),
  603. SND_SOC_DAPM_ADC("ADC 09", NULL, SND_SOC_NOPM, 4, 0),
  604. SND_SOC_DAPM_ADC("ADC 27", NULL, SND_SOC_NOPM, 4, 0),
  605. SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
  606. &rt715_adc22_mux),
  607. SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
  608. &rt715_adc23_mux),
  609. SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
  610. &rt715_adc24_mux),
  611. SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
  612. &rt715_adc25_mux),
  613. SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
  614. SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
  615. };
  616. static const struct snd_soc_dapm_route rt715_sdca_audio_map[] = {
  617. {"DP6TX", NULL, "ADC 09"},
  618. {"DP6TX", NULL, "ADC 08"},
  619. {"DP4TX", NULL, "ADC 07"},
  620. {"DP4TX", NULL, "ADC 27"},
  621. {"DP4TX", NULL, "ADC 09"},
  622. {"DP4TX", NULL, "ADC 08"},
  623. {"LINE1", NULL, "PDE23_24"},
  624. {"LINE2", NULL, "PDE23_24"},
  625. {"MIC1", NULL, "PDE23_24"},
  626. {"MIC2", NULL, "PDE23_24"},
  627. {"DMIC1", NULL, "PDE23_24"},
  628. {"DMIC2", NULL, "PDE23_24"},
  629. {"DMIC3", NULL, "PDE23_24"},
  630. {"DMIC4", NULL, "PDE23_24"},
  631. {"ADC 09", NULL, "ADC 22 Mux"},
  632. {"ADC 08", NULL, "ADC 23 Mux"},
  633. {"ADC 07", NULL, "ADC 24 Mux"},
  634. {"ADC 27", NULL, "ADC 25 Mux"},
  635. {"ADC 22 Mux", "MIC1", "MIC1"},
  636. {"ADC 22 Mux", "MIC2", "MIC2"},
  637. {"ADC 22 Mux", "LINE1", "LINE1"},
  638. {"ADC 22 Mux", "LINE2", "LINE2"},
  639. {"ADC 22 Mux", "DMIC1", "DMIC1"},
  640. {"ADC 22 Mux", "DMIC2", "DMIC2"},
  641. {"ADC 22 Mux", "DMIC3", "DMIC3"},
  642. {"ADC 22 Mux", "DMIC4", "DMIC4"},
  643. {"ADC 23 Mux", "MIC1", "MIC1"},
  644. {"ADC 23 Mux", "MIC2", "MIC2"},
  645. {"ADC 23 Mux", "LINE1", "LINE1"},
  646. {"ADC 23 Mux", "LINE2", "LINE2"},
  647. {"ADC 23 Mux", "DMIC1", "DMIC1"},
  648. {"ADC 23 Mux", "DMIC2", "DMIC2"},
  649. {"ADC 23 Mux", "DMIC3", "DMIC3"},
  650. {"ADC 23 Mux", "DMIC4", "DMIC4"},
  651. {"ADC 24 Mux", "MIC2", "MIC2"},
  652. {"ADC 24 Mux", "DMIC1", "DMIC1"},
  653. {"ADC 24 Mux", "DMIC2", "DMIC2"},
  654. {"ADC 24 Mux", "DMIC3", "DMIC3"},
  655. {"ADC 24 Mux", "DMIC4", "DMIC4"},
  656. {"ADC 25 Mux", "MIC1", "MIC1"},
  657. {"ADC 25 Mux", "DMIC1", "DMIC1"},
  658. {"ADC 25 Mux", "DMIC2", "DMIC2"},
  659. {"ADC 25 Mux", "DMIC3", "DMIC3"},
  660. {"ADC 25 Mux", "DMIC4", "DMIC4"},
  661. };
  662. static int rt715_sdca_probe(struct snd_soc_component *component)
  663. {
  664. int ret;
  665. ret = pm_runtime_resume(component->dev);
  666. if (ret < 0 && ret != -EACCES)
  667. return ret;
  668. return 0;
  669. }
  670. static const struct snd_soc_component_driver soc_codec_dev_rt715_sdca = {
  671. .probe = rt715_sdca_probe,
  672. .controls = rt715_sdca_snd_controls,
  673. .num_controls = ARRAY_SIZE(rt715_sdca_snd_controls),
  674. .dapm_widgets = rt715_sdca_dapm_widgets,
  675. .num_dapm_widgets = ARRAY_SIZE(rt715_sdca_dapm_widgets),
  676. .dapm_routes = rt715_sdca_audio_map,
  677. .num_dapm_routes = ARRAY_SIZE(rt715_sdca_audio_map),
  678. .endianness = 1,
  679. };
  680. static int rt715_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
  681. int direction)
  682. {
  683. struct rt715_sdw_stream_data *stream;
  684. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  685. if (!stream)
  686. return -ENOMEM;
  687. stream->sdw_stream = sdw_stream;
  688. /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
  689. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  690. dai->playback_dma_data = stream;
  691. else
  692. dai->capture_dma_data = stream;
  693. return 0;
  694. }
  695. static void rt715_sdca_shutdown(struct snd_pcm_substream *substream,
  696. struct snd_soc_dai *dai)
  697. {
  698. struct rt715_sdw_stream_data *stream;
  699. stream = snd_soc_dai_get_dma_data(dai, substream);
  700. if (!stream)
  701. return;
  702. snd_soc_dai_set_dma_data(dai, substream, NULL);
  703. kfree(stream);
  704. }
  705. static int rt715_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
  706. struct snd_pcm_hw_params *params,
  707. struct snd_soc_dai *dai)
  708. {
  709. struct snd_soc_component *component = dai->component;
  710. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  711. struct sdw_stream_config stream_config;
  712. struct sdw_port_config port_config;
  713. enum sdw_data_direction direction;
  714. struct rt715_sdw_stream_data *stream;
  715. int retval, port, num_channels;
  716. unsigned int val;
  717. stream = snd_soc_dai_get_dma_data(dai, substream);
  718. if (!stream)
  719. return -EINVAL;
  720. if (!rt715->slave)
  721. return -EINVAL;
  722. switch (dai->id) {
  723. case RT715_AIF1:
  724. direction = SDW_DATA_DIR_TX;
  725. port = 6;
  726. rt715_sdca_index_write(rt715, RT715_VENDOR_REG, RT715_SDW_INPUT_SEL,
  727. 0xa500);
  728. break;
  729. case RT715_AIF2:
  730. direction = SDW_DATA_DIR_TX;
  731. port = 4;
  732. rt715_sdca_index_write(rt715, RT715_VENDOR_REG, RT715_SDW_INPUT_SEL,
  733. 0xaf00);
  734. break;
  735. default:
  736. dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
  737. return -EINVAL;
  738. }
  739. stream_config.frame_rate = params_rate(params);
  740. stream_config.ch_count = params_channels(params);
  741. stream_config.bps = snd_pcm_format_width(params_format(params));
  742. stream_config.direction = direction;
  743. num_channels = params_channels(params);
  744. port_config.ch_mask = GENMASK(num_channels - 1, 0);
  745. port_config.num = port;
  746. retval = sdw_stream_add_slave(rt715->slave, &stream_config,
  747. &port_config, 1, stream->sdw_stream);
  748. if (retval) {
  749. dev_err(component->dev, "Unable to configure port, retval:%d\n",
  750. retval);
  751. return retval;
  752. }
  753. switch (params_rate(params)) {
  754. case 8000:
  755. val = 0x1;
  756. break;
  757. case 11025:
  758. val = 0x2;
  759. break;
  760. case 12000:
  761. val = 0x3;
  762. break;
  763. case 16000:
  764. val = 0x4;
  765. break;
  766. case 22050:
  767. val = 0x5;
  768. break;
  769. case 24000:
  770. val = 0x6;
  771. break;
  772. case 32000:
  773. val = 0x7;
  774. break;
  775. case 44100:
  776. val = 0x8;
  777. break;
  778. case 48000:
  779. val = 0x9;
  780. break;
  781. case 88200:
  782. val = 0xa;
  783. break;
  784. case 96000:
  785. val = 0xb;
  786. break;
  787. case 176400:
  788. val = 0xc;
  789. break;
  790. case 192000:
  791. val = 0xd;
  792. break;
  793. case 384000:
  794. val = 0xe;
  795. break;
  796. case 768000:
  797. val = 0xf;
  798. break;
  799. default:
  800. dev_err(component->dev, "Unsupported sample rate %d\n",
  801. params_rate(params));
  802. return -EINVAL;
  803. }
  804. regmap_write(rt715->regmap,
  805. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CS_FREQ_IND_EN,
  806. RT715_SDCA_FREQ_IND_CTRL, CH_00), val);
  807. return 0;
  808. }
  809. static int rt715_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
  810. struct snd_soc_dai *dai)
  811. {
  812. struct snd_soc_component *component = dai->component;
  813. struct rt715_sdca_priv *rt715 = snd_soc_component_get_drvdata(component);
  814. struct rt715_sdw_stream_data *stream =
  815. snd_soc_dai_get_dma_data(dai, substream);
  816. if (!rt715->slave)
  817. return -EINVAL;
  818. sdw_stream_remove_slave(rt715->slave, stream->sdw_stream);
  819. return 0;
  820. }
  821. #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  822. #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  823. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  824. static const struct snd_soc_dai_ops rt715_sdca_ops = {
  825. .hw_params = rt715_sdca_pcm_hw_params,
  826. .hw_free = rt715_sdca_pcm_hw_free,
  827. .set_stream = rt715_sdca_set_sdw_stream,
  828. .shutdown = rt715_sdca_shutdown,
  829. };
  830. static struct snd_soc_dai_driver rt715_sdca_dai[] = {
  831. {
  832. .name = "rt715-aif1",
  833. .id = RT715_AIF1,
  834. .capture = {
  835. .stream_name = "DP6 Capture",
  836. .channels_min = 1,
  837. .channels_max = 2,
  838. .rates = RT715_STEREO_RATES,
  839. .formats = RT715_FORMATS,
  840. },
  841. .ops = &rt715_sdca_ops,
  842. },
  843. {
  844. .name = "rt715-aif2",
  845. .id = RT715_AIF2,
  846. .capture = {
  847. .stream_name = "DP4 Capture",
  848. .channels_min = 1,
  849. .channels_max = 2,
  850. .rates = RT715_STEREO_RATES,
  851. .formats = RT715_FORMATS,
  852. },
  853. .ops = &rt715_sdca_ops,
  854. },
  855. };
  856. /* Bus clock frequency */
  857. #define RT715_CLK_FREQ_9600000HZ 9600000
  858. #define RT715_CLK_FREQ_12000000HZ 12000000
  859. #define RT715_CLK_FREQ_6000000HZ 6000000
  860. #define RT715_CLK_FREQ_4800000HZ 4800000
  861. #define RT715_CLK_FREQ_2400000HZ 2400000
  862. #define RT715_CLK_FREQ_12288000HZ 12288000
  863. int rt715_sdca_init(struct device *dev, struct regmap *mbq_regmap,
  864. struct regmap *regmap, struct sdw_slave *slave)
  865. {
  866. struct rt715_sdca_priv *rt715;
  867. int ret;
  868. rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
  869. if (!rt715)
  870. return -ENOMEM;
  871. dev_set_drvdata(dev, rt715);
  872. rt715->slave = slave;
  873. rt715->regmap = regmap;
  874. rt715->mbq_regmap = mbq_regmap;
  875. rt715->hw_sdw_ver = slave->id.sdw_version;
  876. /*
  877. * Mark hw_init to false
  878. * HW init will be performed when device reports present
  879. */
  880. rt715->hw_init = false;
  881. rt715->first_hw_init = false;
  882. ret = devm_snd_soc_register_component(dev,
  883. &soc_codec_dev_rt715_sdca,
  884. rt715_sdca_dai,
  885. ARRAY_SIZE(rt715_sdca_dai));
  886. return ret;
  887. }
  888. int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave)
  889. {
  890. struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
  891. unsigned int hw_ver;
  892. if (rt715->hw_init)
  893. return 0;
  894. /*
  895. * PM runtime is only enabled when a Slave reports as Attached
  896. */
  897. if (!rt715->first_hw_init) {
  898. /* set autosuspend parameters */
  899. pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
  900. pm_runtime_use_autosuspend(&slave->dev);
  901. /* update count of parent 'active' children */
  902. pm_runtime_set_active(&slave->dev);
  903. /* make sure the device does not suspend immediately */
  904. pm_runtime_mark_last_busy(&slave->dev);
  905. pm_runtime_enable(&slave->dev);
  906. rt715->first_hw_init = true;
  907. }
  908. pm_runtime_get_noresume(&slave->dev);
  909. rt715_sdca_index_read(rt715, RT715_VENDOR_REG,
  910. RT715_PRODUCT_NUM, &hw_ver);
  911. hw_ver = hw_ver & 0x000f;
  912. /* set clock selector = external */
  913. regmap_write(rt715->regmap,
  914. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_CX_CLK_SEL_EN,
  915. RT715_SDCA_CX_CLK_SEL_CTRL, CH_00), 0x1);
  916. /* set GPIO_4/5/6 to be 3rd/4th DMIC usage */
  917. if (hw_ver == 0x0)
  918. rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
  919. RT715_AD_FUNC_EN, 0x54, 0x54);
  920. else if (hw_ver == 0x1) {
  921. rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
  922. RT715_AD_FUNC_EN, 0x55, 0x55);
  923. rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
  924. RT715_REV_1, 0x40, 0x40);
  925. }
  926. /* DFLL Calibration trigger */
  927. rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
  928. RT715_DFLL_VAD, 0x1, 0x1);
  929. /* trigger mode = VAD enable */
  930. regmap_write(rt715->regmap,
  931. SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
  932. RT715_SDCA_SMPU_TRIG_EN_CTRL, CH_00), 0x2);
  933. /* SMPU-1 interrupt enable mask */
  934. regmap_update_bits(rt715->regmap, RT715_INT_MASK, 0x1, 0x1);
  935. /* Mark Slave initialization complete */
  936. rt715->hw_init = true;
  937. pm_runtime_mark_last_busy(&slave->dev);
  938. pm_runtime_put_autosuspend(&slave->dev);
  939. return 0;
  940. }
  941. MODULE_DESCRIPTION("ASoC rt715 driver SDW SDCA");
  942. MODULE_AUTHOR("Jack Yu <[email protected]>");
  943. MODULE_LICENSE("GPL v2");