max9860.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Driver for the MAX9860 Mono Audio Voice Codec
  4. //
  5. // https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf
  6. //
  7. // The driver does not support sidetone since the DVST register field is
  8. // backwards with the mute near the maximum level instead of the minimum.
  9. //
  10. // Author: Peter Rosin <[email protected]>
  11. // Copyright 2016 Axentia Technologies
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/clk.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/regmap.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <sound/soc.h>
  21. #include <sound/soc-dapm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/tlv.h>
  24. #include "max9860.h"
  25. struct max9860_priv {
  26. struct regmap *regmap;
  27. struct regulator *dvddio;
  28. struct notifier_block dvddio_nb;
  29. u8 psclk;
  30. unsigned long pclk_rate;
  31. int fmt;
  32. };
  33. static int max9860_dvddio_event(struct notifier_block *nb,
  34. unsigned long event, void *data)
  35. {
  36. struct max9860_priv *max9860 = container_of(nb, struct max9860_priv,
  37. dvddio_nb);
  38. if (event & REGULATOR_EVENT_DISABLE) {
  39. regcache_mark_dirty(max9860->regmap);
  40. regcache_cache_only(max9860->regmap, true);
  41. }
  42. return 0;
  43. }
  44. static const struct reg_default max9860_reg_defaults[] = {
  45. { MAX9860_PWRMAN, 0x00 },
  46. { MAX9860_INTEN, 0x00 },
  47. { MAX9860_SYSCLK, 0x00 },
  48. { MAX9860_AUDIOCLKHIGH, 0x00 },
  49. { MAX9860_AUDIOCLKLOW, 0x00 },
  50. { MAX9860_IFC1A, 0x00 },
  51. { MAX9860_IFC1B, 0x00 },
  52. { MAX9860_VOICEFLTR, 0x00 },
  53. { MAX9860_DACATTN, 0x00 },
  54. { MAX9860_ADCLEVEL, 0x00 },
  55. { MAX9860_DACGAIN, 0x00 },
  56. { MAX9860_MICGAIN, 0x00 },
  57. { MAX9860_MICADC, 0x00 },
  58. { MAX9860_NOISEGATE, 0x00 },
  59. };
  60. static bool max9860_readable(struct device *dev, unsigned int reg)
  61. {
  62. switch (reg) {
  63. case MAX9860_INTRSTATUS ... MAX9860_MICGAIN:
  64. case MAX9860_MICADC ... MAX9860_PWRMAN:
  65. case MAX9860_REVISION:
  66. return true;
  67. }
  68. return false;
  69. }
  70. static bool max9860_writeable(struct device *dev, unsigned int reg)
  71. {
  72. switch (reg) {
  73. case MAX9860_INTEN ... MAX9860_MICGAIN:
  74. case MAX9860_MICADC ... MAX9860_PWRMAN:
  75. return true;
  76. }
  77. return false;
  78. }
  79. static bool max9860_volatile(struct device *dev, unsigned int reg)
  80. {
  81. switch (reg) {
  82. case MAX9860_INTRSTATUS:
  83. case MAX9860_MICREADBACK:
  84. return true;
  85. }
  86. return false;
  87. }
  88. static bool max9860_precious(struct device *dev, unsigned int reg)
  89. {
  90. switch (reg) {
  91. case MAX9860_INTRSTATUS:
  92. return true;
  93. }
  94. return false;
  95. }
  96. static const struct regmap_config max9860_regmap = {
  97. .reg_bits = 8,
  98. .val_bits = 8,
  99. .readable_reg = max9860_readable,
  100. .writeable_reg = max9860_writeable,
  101. .volatile_reg = max9860_volatile,
  102. .precious_reg = max9860_precious,
  103. .max_register = MAX9860_MAX_REGISTER,
  104. .reg_defaults = max9860_reg_defaults,
  105. .num_reg_defaults = ARRAY_SIZE(max9860_reg_defaults),
  106. .cache_type = REGCACHE_RBTREE,
  107. };
  108. static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
  109. static const DECLARE_TLV_DB_SCALE(dvg_tlv, 0, 600, 0);
  110. static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
  111. static const DECLARE_TLV_DB_RANGE(pam_tlv,
  112. 0, MAX9860_PAM_MAX - 1, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
  113. MAX9860_PAM_MAX, MAX9860_PAM_MAX, TLV_DB_SCALE_ITEM(3000, 0, 0));
  114. static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
  115. static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
  116. static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
  117. static const char * const agchld_text[] = {
  118. "AGC Disabled", "50ms", "100ms", "400ms"
  119. };
  120. static SOC_ENUM_SINGLE_DECL(agchld_enum, MAX9860_MICADC,
  121. MAX9860_AGCHLD_SHIFT, agchld_text);
  122. static const char * const agcsrc_text[] = {
  123. "Left ADC", "Left/Right ADC"
  124. };
  125. static SOC_ENUM_SINGLE_DECL(agcsrc_enum, MAX9860_MICADC,
  126. MAX9860_AGCSRC_SHIFT, agcsrc_text);
  127. static const char * const agcatk_text[] = {
  128. "3ms", "12ms", "50ms", "200ms"
  129. };
  130. static SOC_ENUM_SINGLE_DECL(agcatk_enum, MAX9860_MICADC,
  131. MAX9860_AGCATK_SHIFT, agcatk_text);
  132. static const char * const agcrls_text[] = {
  133. "78ms", "156ms", "312ms", "625ms",
  134. "1.25s", "2.5s", "5s", "10s"
  135. };
  136. static SOC_ENUM_SINGLE_DECL(agcrls_enum, MAX9860_MICADC,
  137. MAX9860_AGCRLS_SHIFT, agcrls_text);
  138. static const char * const filter_text[] = {
  139. "Disabled",
  140. "Elliptical HP 217Hz notch (16kHz)",
  141. "Butterworth HP 500Hz (16kHz)",
  142. "Elliptical HP 217Hz notch (8kHz)",
  143. "Butterworth HP 500Hz (8kHz)",
  144. "Butterworth HP 200Hz (48kHz)"
  145. };
  146. static SOC_ENUM_SINGLE_DECL(avflt_enum, MAX9860_VOICEFLTR,
  147. MAX9860_AVFLT_SHIFT, filter_text);
  148. static SOC_ENUM_SINGLE_DECL(dvflt_enum, MAX9860_VOICEFLTR,
  149. MAX9860_DVFLT_SHIFT, filter_text);
  150. static const struct snd_kcontrol_new max9860_controls[] = {
  151. SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
  152. MAX9860_DVA_SHIFT, MAX9860_DVA_MUTE, 1, dva_tlv),
  153. SOC_SINGLE_TLV("DAC Gain Volume", MAX9860_DACGAIN,
  154. MAX9860_DVG_SHIFT, MAX9860_DVG_MAX, 0, dvg_tlv),
  155. SOC_DOUBLE_TLV("Line Capture Volume", MAX9860_ADCLEVEL,
  156. MAX9860_ADCLL_SHIFT, MAX9860_ADCRL_SHIFT, MAX9860_ADCxL_MIN, 1,
  157. adc_tlv),
  158. SOC_ENUM("AGC Hold Time", agchld_enum),
  159. SOC_ENUM("AGC/Noise Gate Source", agcsrc_enum),
  160. SOC_ENUM("AGC Attack Time", agcatk_enum),
  161. SOC_ENUM("AGC Release Time", agcrls_enum),
  162. SOC_SINGLE_TLV("Noise Gate Threshold Volume", MAX9860_NOISEGATE,
  163. MAX9860_ANTH_SHIFT, MAX9860_ANTH_MAX, 0, anth_tlv),
  164. SOC_SINGLE_TLV("AGC Signal Threshold Volume", MAX9860_NOISEGATE,
  165. MAX9860_AGCTH_SHIFT, MAX9860_AGCTH_MIN, 1, agcth_tlv),
  166. SOC_SINGLE_TLV("Mic PGA Volume", MAX9860_MICGAIN,
  167. MAX9860_PGAM_SHIFT, MAX9860_PGAM_MIN, 1, pgam_tlv),
  168. SOC_SINGLE_TLV("Mic Preamp Volume", MAX9860_MICGAIN,
  169. MAX9860_PAM_SHIFT, MAX9860_PAM_MAX, 0, pam_tlv),
  170. SOC_ENUM("ADC Filter", avflt_enum),
  171. SOC_ENUM("DAC Filter", dvflt_enum),
  172. };
  173. static const struct snd_soc_dapm_widget max9860_dapm_widgets[] = {
  174. SND_SOC_DAPM_INPUT("MICL"),
  175. SND_SOC_DAPM_INPUT("MICR"),
  176. SND_SOC_DAPM_ADC("ADCL", NULL, MAX9860_PWRMAN, MAX9860_ADCLEN_SHIFT, 0),
  177. SND_SOC_DAPM_ADC("ADCR", NULL, MAX9860_PWRMAN, MAX9860_ADCREN_SHIFT, 0),
  178. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  179. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  180. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  181. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  182. SND_SOC_DAPM_DAC("DAC", NULL, MAX9860_PWRMAN, MAX9860_DACEN_SHIFT, 0),
  183. SND_SOC_DAPM_OUTPUT("OUT"),
  184. SND_SOC_DAPM_SUPPLY("Supply", SND_SOC_NOPM, 0, 0,
  185. NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  186. SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 0, 0),
  187. SND_SOC_DAPM_REGULATOR_SUPPLY("DVDD", 0, 0),
  188. SND_SOC_DAPM_CLOCK_SUPPLY("mclk"),
  189. };
  190. static const struct snd_soc_dapm_route max9860_dapm_routes[] = {
  191. { "ADCL", NULL, "MICL" },
  192. { "ADCR", NULL, "MICR" },
  193. { "AIFOUTL", NULL, "ADCL" },
  194. { "AIFOUTR", NULL, "ADCR" },
  195. { "DAC", NULL, "AIFINL" },
  196. { "DAC", NULL, "AIFINR" },
  197. { "OUT", NULL, "DAC" },
  198. { "Supply", NULL, "AVDD" },
  199. { "Supply", NULL, "DVDD" },
  200. { "Supply", NULL, "mclk" },
  201. { "DAC", NULL, "Supply" },
  202. { "ADCL", NULL, "Supply" },
  203. { "ADCR", NULL, "Supply" },
  204. };
  205. static int max9860_hw_params(struct snd_pcm_substream *substream,
  206. struct snd_pcm_hw_params *params,
  207. struct snd_soc_dai *dai)
  208. {
  209. struct snd_soc_component *component = dai->component;
  210. struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
  211. u8 master;
  212. u8 ifc1a = 0;
  213. u8 ifc1b = 0;
  214. u8 sysclk = 0;
  215. unsigned long n;
  216. int ret;
  217. dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
  218. params_rate(params),
  219. params_channels(params));
  220. if (params_channels(params) == 2)
  221. ifc1b |= MAX9860_ST;
  222. switch (max9860->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  223. case SND_SOC_DAIFMT_CBC_CFC:
  224. master = 0;
  225. break;
  226. case SND_SOC_DAIFMT_CBP_CFP:
  227. master = MAX9860_MASTER;
  228. break;
  229. default:
  230. return -EINVAL;
  231. }
  232. ifc1a |= master;
  233. if (master) {
  234. if (params_width(params) * params_channels(params) > 48)
  235. ifc1b |= MAX9860_BSEL_64X;
  236. else
  237. ifc1b |= MAX9860_BSEL_48X;
  238. }
  239. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  240. case SND_SOC_DAIFMT_I2S:
  241. ifc1a |= MAX9860_DDLY;
  242. ifc1b |= MAX9860_ADLY;
  243. break;
  244. case SND_SOC_DAIFMT_LEFT_J:
  245. ifc1a |= MAX9860_WCI;
  246. break;
  247. case SND_SOC_DAIFMT_DSP_A:
  248. if (params_width(params) != 16) {
  249. dev_err(component->dev,
  250. "DSP_A works for 16 bits per sample only.\n");
  251. return -EINVAL;
  252. }
  253. ifc1a |= MAX9860_DDLY | MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
  254. ifc1b |= MAX9860_ADLY;
  255. break;
  256. case SND_SOC_DAIFMT_DSP_B:
  257. if (params_width(params) != 16) {
  258. dev_err(component->dev,
  259. "DSP_B works for 16 bits per sample only.\n");
  260. return -EINVAL;
  261. }
  262. ifc1a |= MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
  263. break;
  264. default:
  265. return -EINVAL;
  266. }
  267. switch (max9860->fmt & SND_SOC_DAIFMT_INV_MASK) {
  268. case SND_SOC_DAIFMT_NB_NF:
  269. break;
  270. case SND_SOC_DAIFMT_NB_IF:
  271. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  272. case SND_SOC_DAIFMT_DSP_A:
  273. case SND_SOC_DAIFMT_DSP_B:
  274. return -EINVAL;
  275. }
  276. ifc1a ^= MAX9860_WCI;
  277. break;
  278. case SND_SOC_DAIFMT_IB_IF:
  279. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  280. case SND_SOC_DAIFMT_DSP_A:
  281. case SND_SOC_DAIFMT_DSP_B:
  282. return -EINVAL;
  283. }
  284. ifc1a ^= MAX9860_WCI;
  285. fallthrough;
  286. case SND_SOC_DAIFMT_IB_NF:
  287. ifc1a ^= MAX9860_DBCI;
  288. ifc1b ^= MAX9860_ABCI;
  289. break;
  290. default:
  291. return -EINVAL;
  292. }
  293. dev_dbg(component->dev, "IFC1A %02x\n", ifc1a);
  294. ret = regmap_write(max9860->regmap, MAX9860_IFC1A, ifc1a);
  295. if (ret) {
  296. dev_err(component->dev, "Failed to set IFC1A: %d\n", ret);
  297. return ret;
  298. }
  299. dev_dbg(component->dev, "IFC1B %02x\n", ifc1b);
  300. ret = regmap_write(max9860->regmap, MAX9860_IFC1B, ifc1b);
  301. if (ret) {
  302. dev_err(component->dev, "Failed to set IFC1B: %d\n", ret);
  303. return ret;
  304. }
  305. /*
  306. * Check if Integer Clock Mode is possible, but avoid it in slave mode
  307. * since we then do not know if lrclk is derived from pclk and the
  308. * datasheet mentions that the frequencies have to match exactly in
  309. * order for this to work.
  310. */
  311. if (params_rate(params) == 8000 || params_rate(params) == 16000) {
  312. if (master) {
  313. switch (max9860->pclk_rate) {
  314. case 12000000:
  315. sysclk = MAX9860_FREQ_12MHZ;
  316. break;
  317. case 13000000:
  318. sysclk = MAX9860_FREQ_13MHZ;
  319. break;
  320. case 19200000:
  321. sysclk = MAX9860_FREQ_19_2MHZ;
  322. break;
  323. default:
  324. /*
  325. * Integer Clock Mode not possible. Leave
  326. * sysclk at zero and fall through to the
  327. * code below for PLL mode.
  328. */
  329. break;
  330. }
  331. if (sysclk && params_rate(params) == 16000)
  332. sysclk |= MAX9860_16KHZ;
  333. }
  334. }
  335. /*
  336. * Largest possible n:
  337. * 65536 * 96 * 48kHz / 10MHz -> 30199
  338. * Smallest possible n:
  339. * 65536 * 96 * 8kHz / 20MHz -> 2517
  340. * Both fit nicely in the available 15 bits, no need to apply any mask.
  341. */
  342. n = DIV_ROUND_CLOSEST_ULL(65536ULL * 96 * params_rate(params),
  343. max9860->pclk_rate);
  344. if (!sysclk) {
  345. /* PLL mode */
  346. if (params_rate(params) > 24000)
  347. sysclk |= MAX9860_16KHZ;
  348. if (!master)
  349. n |= 1; /* trigger rapid pll lock mode */
  350. }
  351. sysclk |= max9860->psclk;
  352. dev_dbg(component->dev, "SYSCLK %02x\n", sysclk);
  353. ret = regmap_write(max9860->regmap,
  354. MAX9860_SYSCLK, sysclk);
  355. if (ret) {
  356. dev_err(component->dev, "Failed to set SYSCLK: %d\n", ret);
  357. return ret;
  358. }
  359. dev_dbg(component->dev, "N %lu\n", n);
  360. ret = regmap_write(max9860->regmap,
  361. MAX9860_AUDIOCLKHIGH, n >> 8);
  362. if (ret) {
  363. dev_err(component->dev, "Failed to set NHI: %d\n", ret);
  364. return ret;
  365. }
  366. ret = regmap_write(max9860->regmap,
  367. MAX9860_AUDIOCLKLOW, n & 0xff);
  368. if (ret) {
  369. dev_err(component->dev, "Failed to set NLO: %d\n", ret);
  370. return ret;
  371. }
  372. if (!master) {
  373. dev_dbg(component->dev, "Enable PLL\n");
  374. ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH,
  375. MAX9860_PLL, MAX9860_PLL);
  376. if (ret) {
  377. dev_err(component->dev, "Failed to enable PLL: %d\n",
  378. ret);
  379. return ret;
  380. }
  381. }
  382. return 0;
  383. }
  384. static int max9860_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  385. {
  386. struct snd_soc_component *component = dai->component;
  387. struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
  388. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  389. case SND_SOC_DAIFMT_CBP_CFP:
  390. case SND_SOC_DAIFMT_CBC_CFC:
  391. max9860->fmt = fmt;
  392. return 0;
  393. default:
  394. return -EINVAL;
  395. }
  396. }
  397. static const struct snd_soc_dai_ops max9860_dai_ops = {
  398. .hw_params = max9860_hw_params,
  399. .set_fmt = max9860_set_fmt,
  400. };
  401. static struct snd_soc_dai_driver max9860_dai = {
  402. .name = "max9860-hifi",
  403. .playback = {
  404. .stream_name = "Playback",
  405. .channels_min = 1,
  406. .channels_max = 2,
  407. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  408. .rate_min = 8000,
  409. .rate_max = 48000,
  410. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  411. SNDRV_PCM_FMTBIT_S24_LE |
  412. SNDRV_PCM_FMTBIT_S32_LE,
  413. },
  414. .capture = {
  415. .stream_name = "Capture",
  416. .channels_min = 1,
  417. .channels_max = 2,
  418. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  419. .rate_min = 8000,
  420. .rate_max = 48000,
  421. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  422. SNDRV_PCM_FMTBIT_S24_LE |
  423. SNDRV_PCM_FMTBIT_S32_LE,
  424. },
  425. .ops = &max9860_dai_ops,
  426. .symmetric_rate = 1,
  427. };
  428. static int max9860_set_bias_level(struct snd_soc_component *component,
  429. enum snd_soc_bias_level level)
  430. {
  431. struct max9860_priv *max9860 = dev_get_drvdata(component->dev);
  432. int ret;
  433. switch (level) {
  434. case SND_SOC_BIAS_ON:
  435. case SND_SOC_BIAS_PREPARE:
  436. break;
  437. case SND_SOC_BIAS_STANDBY:
  438. ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
  439. MAX9860_SHDN, MAX9860_SHDN);
  440. if (ret) {
  441. dev_err(component->dev, "Failed to remove SHDN: %d\n",
  442. ret);
  443. return ret;
  444. }
  445. break;
  446. case SND_SOC_BIAS_OFF:
  447. ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
  448. MAX9860_SHDN, 0);
  449. if (ret) {
  450. dev_err(component->dev, "Failed to request SHDN: %d\n",
  451. ret);
  452. return ret;
  453. }
  454. break;
  455. }
  456. return 0;
  457. }
  458. static const struct snd_soc_component_driver max9860_component_driver = {
  459. .set_bias_level = max9860_set_bias_level,
  460. .controls = max9860_controls,
  461. .num_controls = ARRAY_SIZE(max9860_controls),
  462. .dapm_widgets = max9860_dapm_widgets,
  463. .num_dapm_widgets = ARRAY_SIZE(max9860_dapm_widgets),
  464. .dapm_routes = max9860_dapm_routes,
  465. .num_dapm_routes = ARRAY_SIZE(max9860_dapm_routes),
  466. .use_pmdown_time = 1,
  467. .endianness = 1,
  468. };
  469. #ifdef CONFIG_PM
  470. static int max9860_suspend(struct device *dev)
  471. {
  472. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  473. int ret;
  474. ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
  475. MAX9860_PSCLK, MAX9860_PSCLK_OFF);
  476. if (ret) {
  477. dev_err(dev, "Failed to disable clock: %d\n", ret);
  478. return ret;
  479. }
  480. regulator_disable(max9860->dvddio);
  481. return 0;
  482. }
  483. static int max9860_resume(struct device *dev)
  484. {
  485. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  486. int ret;
  487. ret = regulator_enable(max9860->dvddio);
  488. if (ret) {
  489. dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
  490. return ret;
  491. }
  492. regcache_cache_only(max9860->regmap, false);
  493. ret = regcache_sync(max9860->regmap);
  494. if (ret) {
  495. dev_err(dev, "Failed to sync cache: %d\n", ret);
  496. return ret;
  497. }
  498. ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
  499. MAX9860_PSCLK, max9860->psclk);
  500. if (ret) {
  501. dev_err(dev, "Failed to enable clock: %d\n", ret);
  502. return ret;
  503. }
  504. return 0;
  505. }
  506. #endif
  507. static const struct dev_pm_ops max9860_pm_ops = {
  508. SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL)
  509. };
  510. static int max9860_probe(struct i2c_client *i2c)
  511. {
  512. struct device *dev = &i2c->dev;
  513. struct max9860_priv *max9860;
  514. int ret;
  515. struct clk *mclk;
  516. unsigned long mclk_rate;
  517. int i;
  518. int intr;
  519. max9860 = devm_kzalloc(dev, sizeof(struct max9860_priv), GFP_KERNEL);
  520. if (!max9860)
  521. return -ENOMEM;
  522. max9860->dvddio = devm_regulator_get(dev, "DVDDIO");
  523. if (IS_ERR(max9860->dvddio))
  524. return dev_err_probe(dev, PTR_ERR(max9860->dvddio),
  525. "Failed to get DVDDIO supply\n");
  526. max9860->dvddio_nb.notifier_call = max9860_dvddio_event;
  527. ret = devm_regulator_register_notifier(max9860->dvddio,
  528. &max9860->dvddio_nb);
  529. if (ret)
  530. dev_err(dev, "Failed to register DVDDIO notifier: %d\n", ret);
  531. ret = regulator_enable(max9860->dvddio);
  532. if (ret != 0) {
  533. dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
  534. return ret;
  535. }
  536. max9860->regmap = devm_regmap_init_i2c(i2c, &max9860_regmap);
  537. if (IS_ERR(max9860->regmap)) {
  538. ret = PTR_ERR(max9860->regmap);
  539. goto err_regulator;
  540. }
  541. dev_set_drvdata(dev, max9860);
  542. /*
  543. * mclk has to be in the 10MHz to 60MHz range.
  544. * psclk is used to scale mclk into pclk so that
  545. * pclk is in the 10MHz to 20MHz range.
  546. */
  547. mclk = clk_get(dev, "mclk");
  548. if (IS_ERR(mclk)) {
  549. ret = PTR_ERR(mclk);
  550. dev_err_probe(dev, ret, "Failed to get MCLK\n");
  551. goto err_regulator;
  552. }
  553. mclk_rate = clk_get_rate(mclk);
  554. clk_put(mclk);
  555. if (mclk_rate > 60000000 || mclk_rate < 10000000) {
  556. dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
  557. mclk_rate);
  558. ret = -EINVAL;
  559. goto err_regulator;
  560. }
  561. if (mclk_rate >= 40000000)
  562. max9860->psclk = 3;
  563. else if (mclk_rate >= 20000000)
  564. max9860->psclk = 2;
  565. else
  566. max9860->psclk = 1;
  567. max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
  568. max9860->psclk <<= MAX9860_PSCLK_SHIFT;
  569. dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);
  570. regcache_cache_bypass(max9860->regmap, true);
  571. for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
  572. ret = regmap_write(max9860->regmap,
  573. max9860_regmap.reg_defaults[i].reg,
  574. max9860_regmap.reg_defaults[i].def);
  575. if (ret) {
  576. dev_err(dev, "Failed to initialize register %u: %d\n",
  577. max9860_regmap.reg_defaults[i].reg, ret);
  578. goto err_regulator;
  579. }
  580. }
  581. regcache_cache_bypass(max9860->regmap, false);
  582. ret = regmap_read(max9860->regmap, MAX9860_INTRSTATUS, &intr);
  583. if (ret) {
  584. dev_err(dev, "Failed to clear INTRSTATUS: %d\n", ret);
  585. goto err_regulator;
  586. }
  587. pm_runtime_set_active(dev);
  588. pm_runtime_enable(dev);
  589. pm_runtime_idle(dev);
  590. ret = devm_snd_soc_register_component(dev, &max9860_component_driver,
  591. &max9860_dai, 1);
  592. if (ret) {
  593. dev_err(dev, "Failed to register CODEC: %d\n", ret);
  594. goto err_pm;
  595. }
  596. return 0;
  597. err_pm:
  598. pm_runtime_disable(dev);
  599. err_regulator:
  600. regulator_disable(max9860->dvddio);
  601. return ret;
  602. }
  603. static void max9860_remove(struct i2c_client *i2c)
  604. {
  605. struct device *dev = &i2c->dev;
  606. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  607. pm_runtime_disable(dev);
  608. regulator_disable(max9860->dvddio);
  609. }
  610. static const struct i2c_device_id max9860_i2c_id[] = {
  611. { "max9860", },
  612. { }
  613. };
  614. MODULE_DEVICE_TABLE(i2c, max9860_i2c_id);
  615. static const struct of_device_id max9860_of_match[] = {
  616. { .compatible = "maxim,max9860", },
  617. { }
  618. };
  619. MODULE_DEVICE_TABLE(of, max9860_of_match);
  620. static struct i2c_driver max9860_i2c_driver = {
  621. .probe_new = max9860_probe,
  622. .remove = max9860_remove,
  623. .id_table = max9860_i2c_id,
  624. .driver = {
  625. .name = "max9860",
  626. .of_match_table = max9860_of_match,
  627. .pm = &max9860_pm_ops,
  628. },
  629. };
  630. module_i2c_driver(max9860_i2c_driver);
  631. MODULE_DESCRIPTION("ASoC MAX9860 Mono Audio Voice Codec driver");
  632. MODULE_AUTHOR("Peter Rosin <[email protected]>");
  633. MODULE_LICENSE("GPL v2");