adau1701.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ADAU1701 SigmaDSP processor
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <[email protected]>
  7. * based on an inital version by Cliff Cai <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/i2c.h>
  12. #include <linux/delay.h>
  13. #include <linux/slab.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/gpio/consumer.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/regmap.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <asm/unaligned.h>
  24. #include "sigmadsp.h"
  25. #include "adau1701.h"
  26. #define ADAU1701_SAFELOAD_DATA(i) (0x0810 + (i))
  27. #define ADAU1701_SAFELOAD_ADDR(i) (0x0815 + (i))
  28. #define ADAU1701_DSPCTRL 0x081c
  29. #define ADAU1701_SEROCTL 0x081e
  30. #define ADAU1701_SERICTL 0x081f
  31. #define ADAU1701_AUXNPOW 0x0822
  32. #define ADAU1701_PINCONF_0 0x0820
  33. #define ADAU1701_PINCONF_1 0x0821
  34. #define ADAU1701_AUXNPOW 0x0822
  35. #define ADAU1701_OSCIPOW 0x0826
  36. #define ADAU1701_DACSET 0x0827
  37. #define ADAU1701_MAX_REGISTER 0x0828
  38. #define ADAU1701_DSPCTRL_CR (1 << 2)
  39. #define ADAU1701_DSPCTRL_DAM (1 << 3)
  40. #define ADAU1701_DSPCTRL_ADM (1 << 4)
  41. #define ADAU1701_DSPCTRL_IST (1 << 5)
  42. #define ADAU1701_DSPCTRL_SR_48 0x00
  43. #define ADAU1701_DSPCTRL_SR_96 0x01
  44. #define ADAU1701_DSPCTRL_SR_192 0x02
  45. #define ADAU1701_DSPCTRL_SR_MASK 0x03
  46. #define ADAU1701_SEROCTL_INV_LRCLK 0x2000
  47. #define ADAU1701_SEROCTL_INV_BCLK 0x1000
  48. #define ADAU1701_SEROCTL_MASTER 0x0800
  49. #define ADAU1701_SEROCTL_OBF16 0x0000
  50. #define ADAU1701_SEROCTL_OBF8 0x0200
  51. #define ADAU1701_SEROCTL_OBF4 0x0400
  52. #define ADAU1701_SEROCTL_OBF2 0x0600
  53. #define ADAU1701_SEROCTL_OBF_MASK 0x0600
  54. #define ADAU1701_SEROCTL_OLF1024 0x0000
  55. #define ADAU1701_SEROCTL_OLF512 0x0080
  56. #define ADAU1701_SEROCTL_OLF256 0x0100
  57. #define ADAU1701_SEROCTL_OLF_MASK 0x0180
  58. #define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
  59. #define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
  60. #define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
  61. #define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
  62. #define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
  63. #define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
  64. #define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
  65. #define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
  66. #define ADAU1701_SEROCTL_WORD_LEN_16 0x0002
  67. #define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
  68. #define ADAU1701_AUXNPOW_VBPD 0x40
  69. #define ADAU1701_AUXNPOW_VRPD 0x20
  70. #define ADAU1701_SERICTL_I2S 0
  71. #define ADAU1701_SERICTL_LEFTJ 1
  72. #define ADAU1701_SERICTL_TDM 2
  73. #define ADAU1701_SERICTL_RIGHTJ_24 3
  74. #define ADAU1701_SERICTL_RIGHTJ_20 4
  75. #define ADAU1701_SERICTL_RIGHTJ_18 5
  76. #define ADAU1701_SERICTL_RIGHTJ_16 6
  77. #define ADAU1701_SERICTL_MODE_MASK 7
  78. #define ADAU1701_SERICTL_INV_BCLK BIT(3)
  79. #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
  80. #define ADAU1701_OSCIPOW_OPD 0x04
  81. #define ADAU1701_DACSET_DACINIT 1
  82. #define ADAU1707_CLKDIV_UNSET (-1U)
  83. #define ADAU1701_FIRMWARE "adau1701.bin"
  84. static const char * const supply_names[] = {
  85. "dvdd", "avdd"
  86. };
  87. struct adau1701 {
  88. struct gpio_desc *gpio_nreset;
  89. struct gpio_descs *gpio_pll_mode;
  90. unsigned int dai_fmt;
  91. unsigned int pll_clkdiv;
  92. unsigned int sysclk;
  93. struct regmap *regmap;
  94. struct i2c_client *client;
  95. u8 pin_config[12];
  96. struct sigmadsp *sigmadsp;
  97. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  98. };
  99. static const struct snd_kcontrol_new adau1701_controls[] = {
  100. SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
  101. };
  102. static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
  103. SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
  104. SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
  105. SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
  106. SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
  107. SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
  108. SND_SOC_DAPM_OUTPUT("OUT0"),
  109. SND_SOC_DAPM_OUTPUT("OUT1"),
  110. SND_SOC_DAPM_OUTPUT("OUT2"),
  111. SND_SOC_DAPM_OUTPUT("OUT3"),
  112. SND_SOC_DAPM_INPUT("IN0"),
  113. SND_SOC_DAPM_INPUT("IN1"),
  114. };
  115. static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
  116. { "OUT0", NULL, "DAC0" },
  117. { "OUT1", NULL, "DAC1" },
  118. { "OUT2", NULL, "DAC2" },
  119. { "OUT3", NULL, "DAC3" },
  120. { "ADC", NULL, "IN0" },
  121. { "ADC", NULL, "IN1" },
  122. };
  123. static unsigned int adau1701_register_size(struct device *dev,
  124. unsigned int reg)
  125. {
  126. switch (reg) {
  127. case ADAU1701_PINCONF_0:
  128. case ADAU1701_PINCONF_1:
  129. return 3;
  130. case ADAU1701_DSPCTRL:
  131. case ADAU1701_SEROCTL:
  132. case ADAU1701_AUXNPOW:
  133. case ADAU1701_OSCIPOW:
  134. case ADAU1701_DACSET:
  135. return 2;
  136. case ADAU1701_SERICTL:
  137. return 1;
  138. }
  139. dev_err(dev, "Unsupported register address: %d\n", reg);
  140. return 0;
  141. }
  142. static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
  143. {
  144. switch (reg) {
  145. case ADAU1701_DACSET:
  146. case ADAU1701_DSPCTRL:
  147. return true;
  148. default:
  149. return false;
  150. }
  151. }
  152. static int adau1701_reg_write(void *context, unsigned int reg,
  153. unsigned int value)
  154. {
  155. struct i2c_client *client = context;
  156. unsigned int i;
  157. unsigned int size;
  158. uint8_t buf[5];
  159. int ret;
  160. size = adau1701_register_size(&client->dev, reg);
  161. if (size == 0)
  162. return -EINVAL;
  163. buf[0] = reg >> 8;
  164. buf[1] = reg & 0xff;
  165. for (i = size + 1; i >= 2; --i) {
  166. buf[i] = value;
  167. value >>= 8;
  168. }
  169. ret = i2c_master_send(client, buf, size + 2);
  170. if (ret == size + 2)
  171. return 0;
  172. else if (ret < 0)
  173. return ret;
  174. else
  175. return -EIO;
  176. }
  177. static int adau1701_reg_read(void *context, unsigned int reg,
  178. unsigned int *value)
  179. {
  180. int ret;
  181. unsigned int i;
  182. unsigned int size;
  183. uint8_t send_buf[2], recv_buf[3];
  184. struct i2c_client *client = context;
  185. struct i2c_msg msgs[2];
  186. size = adau1701_register_size(&client->dev, reg);
  187. if (size == 0)
  188. return -EINVAL;
  189. send_buf[0] = reg >> 8;
  190. send_buf[1] = reg & 0xff;
  191. msgs[0].addr = client->addr;
  192. msgs[0].len = sizeof(send_buf);
  193. msgs[0].buf = send_buf;
  194. msgs[0].flags = 0;
  195. msgs[1].addr = client->addr;
  196. msgs[1].len = size;
  197. msgs[1].buf = recv_buf;
  198. msgs[1].flags = I2C_M_RD;
  199. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  200. if (ret < 0)
  201. return ret;
  202. else if (ret != ARRAY_SIZE(msgs))
  203. return -EIO;
  204. *value = 0;
  205. for (i = 0; i < size; i++) {
  206. *value <<= 8;
  207. *value |= recv_buf[i];
  208. }
  209. return 0;
  210. }
  211. static int adau1701_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
  212. const uint8_t bytes[], size_t len)
  213. {
  214. struct i2c_client *client = to_i2c_client(sigmadsp->dev);
  215. struct adau1701 *adau1701 = i2c_get_clientdata(client);
  216. unsigned int val;
  217. unsigned int i;
  218. uint8_t buf[10];
  219. int ret;
  220. ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val);
  221. if (ret)
  222. return ret;
  223. if (val & ADAU1701_DSPCTRL_IST)
  224. msleep(50);
  225. for (i = 0; i < len / 4; i++) {
  226. put_unaligned_le16(ADAU1701_SAFELOAD_DATA(i), buf);
  227. buf[2] = 0x00;
  228. memcpy(buf + 3, bytes + i * 4, 4);
  229. ret = i2c_master_send(client, buf, 7);
  230. if (ret < 0)
  231. return ret;
  232. else if (ret != 7)
  233. return -EIO;
  234. put_unaligned_le16(ADAU1701_SAFELOAD_ADDR(i), buf);
  235. put_unaligned_le16(addr + i, buf + 2);
  236. ret = i2c_master_send(client, buf, 4);
  237. if (ret < 0)
  238. return ret;
  239. else if (ret != 4)
  240. return -EIO;
  241. }
  242. return regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  243. ADAU1701_DSPCTRL_IST, ADAU1701_DSPCTRL_IST);
  244. }
  245. static const struct sigmadsp_ops adau1701_sigmadsp_ops = {
  246. .safeload = adau1701_safeload,
  247. };
  248. static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv,
  249. unsigned int rate)
  250. {
  251. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  252. int ret;
  253. DECLARE_BITMAP(values, 2);
  254. sigmadsp_reset(adau1701->sigmadsp);
  255. if (clkdiv != ADAU1707_CLKDIV_UNSET && adau1701->gpio_pll_mode) {
  256. switch (clkdiv) {
  257. case 64:
  258. __assign_bit(0, values, 0);
  259. __assign_bit(1, values, 0);
  260. break;
  261. case 256:
  262. __assign_bit(0, values, 0);
  263. __assign_bit(1, values, 1);
  264. break;
  265. case 384:
  266. __assign_bit(0, values, 1);
  267. __assign_bit(1, values, 0);
  268. break;
  269. case 0: /* fallback */
  270. case 512:
  271. __assign_bit(0, values, 1);
  272. __assign_bit(1, values, 1);
  273. break;
  274. }
  275. gpiod_set_array_value_cansleep(adau1701->gpio_pll_mode->ndescs,
  276. adau1701->gpio_pll_mode->desc, adau1701->gpio_pll_mode->info,
  277. values);
  278. }
  279. adau1701->pll_clkdiv = clkdiv;
  280. if (adau1701->gpio_nreset) {
  281. gpiod_set_value_cansleep(adau1701->gpio_nreset, 0);
  282. /* minimum reset time is 20ns */
  283. udelay(1);
  284. gpiod_set_value_cansleep(adau1701->gpio_nreset, 1);
  285. /* power-up time may be as long as 85ms */
  286. mdelay(85);
  287. }
  288. /*
  289. * Postpone the firmware download to a point in time when we
  290. * know the correct PLL setup
  291. */
  292. if (clkdiv != ADAU1707_CLKDIV_UNSET) {
  293. ret = sigmadsp_setup(adau1701->sigmadsp, rate);
  294. if (ret) {
  295. dev_warn(component->dev, "Failed to load firmware\n");
  296. return ret;
  297. }
  298. }
  299. regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
  300. regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
  301. regcache_mark_dirty(adau1701->regmap);
  302. regcache_sync(adau1701->regmap);
  303. return 0;
  304. }
  305. static int adau1701_set_capture_pcm_format(struct snd_soc_component *component,
  306. struct snd_pcm_hw_params *params)
  307. {
  308. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  309. unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
  310. unsigned int val;
  311. switch (params_width(params)) {
  312. case 16:
  313. val = ADAU1701_SEROCTL_WORD_LEN_16;
  314. break;
  315. case 20:
  316. val = ADAU1701_SEROCTL_WORD_LEN_20;
  317. break;
  318. case 24:
  319. val = ADAU1701_SEROCTL_WORD_LEN_24;
  320. break;
  321. default:
  322. return -EINVAL;
  323. }
  324. if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
  325. switch (params_width(params)) {
  326. case 16:
  327. val |= ADAU1701_SEROCTL_MSB_DEALY16;
  328. break;
  329. case 20:
  330. val |= ADAU1701_SEROCTL_MSB_DEALY12;
  331. break;
  332. case 24:
  333. val |= ADAU1701_SEROCTL_MSB_DEALY8;
  334. break;
  335. }
  336. mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
  337. }
  338. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
  339. return 0;
  340. }
  341. static int adau1701_set_playback_pcm_format(struct snd_soc_component *component,
  342. struct snd_pcm_hw_params *params)
  343. {
  344. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  345. unsigned int val;
  346. if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
  347. return 0;
  348. switch (params_width(params)) {
  349. case 16:
  350. val = ADAU1701_SERICTL_RIGHTJ_16;
  351. break;
  352. case 20:
  353. val = ADAU1701_SERICTL_RIGHTJ_20;
  354. break;
  355. case 24:
  356. val = ADAU1701_SERICTL_RIGHTJ_24;
  357. break;
  358. default:
  359. return -EINVAL;
  360. }
  361. regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
  362. ADAU1701_SERICTL_MODE_MASK, val);
  363. return 0;
  364. }
  365. static int adau1701_hw_params(struct snd_pcm_substream *substream,
  366. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  367. {
  368. struct snd_soc_component *component = dai->component;
  369. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  370. unsigned int clkdiv = adau1701->sysclk / params_rate(params);
  371. unsigned int val;
  372. int ret;
  373. /*
  374. * If the mclk/lrclk ratio changes, the chip needs updated PLL
  375. * mode GPIO settings, and a full reset cycle, including a new
  376. * firmware upload.
  377. */
  378. if (clkdiv != adau1701->pll_clkdiv) {
  379. ret = adau1701_reset(component, clkdiv, params_rate(params));
  380. if (ret < 0)
  381. return ret;
  382. }
  383. switch (params_rate(params)) {
  384. case 192000:
  385. val = ADAU1701_DSPCTRL_SR_192;
  386. break;
  387. case 96000:
  388. val = ADAU1701_DSPCTRL_SR_96;
  389. break;
  390. case 48000:
  391. val = ADAU1701_DSPCTRL_SR_48;
  392. break;
  393. default:
  394. return -EINVAL;
  395. }
  396. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  397. ADAU1701_DSPCTRL_SR_MASK, val);
  398. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  399. return adau1701_set_playback_pcm_format(component, params);
  400. else
  401. return adau1701_set_capture_pcm_format(component, params);
  402. }
  403. static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
  404. unsigned int fmt)
  405. {
  406. struct snd_soc_component *component = codec_dai->component;
  407. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  408. unsigned int serictl = 0x00, seroctl = 0x00;
  409. bool invert_lrclk;
  410. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  411. case SND_SOC_DAIFMT_CBP_CFP:
  412. /* master, 64-bits per sample, 1 frame per sample */
  413. seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
  414. | ADAU1701_SEROCTL_OLF1024;
  415. break;
  416. case SND_SOC_DAIFMT_CBC_CFC:
  417. break;
  418. default:
  419. return -EINVAL;
  420. }
  421. /* clock inversion */
  422. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  423. case SND_SOC_DAIFMT_NB_NF:
  424. invert_lrclk = false;
  425. break;
  426. case SND_SOC_DAIFMT_NB_IF:
  427. invert_lrclk = true;
  428. break;
  429. case SND_SOC_DAIFMT_IB_NF:
  430. invert_lrclk = false;
  431. serictl |= ADAU1701_SERICTL_INV_BCLK;
  432. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  433. break;
  434. case SND_SOC_DAIFMT_IB_IF:
  435. invert_lrclk = true;
  436. serictl |= ADAU1701_SERICTL_INV_BCLK;
  437. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  438. break;
  439. default:
  440. return -EINVAL;
  441. }
  442. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  443. case SND_SOC_DAIFMT_I2S:
  444. break;
  445. case SND_SOC_DAIFMT_LEFT_J:
  446. serictl |= ADAU1701_SERICTL_LEFTJ;
  447. seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
  448. invert_lrclk = !invert_lrclk;
  449. break;
  450. case SND_SOC_DAIFMT_RIGHT_J:
  451. serictl |= ADAU1701_SERICTL_RIGHTJ_24;
  452. seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
  453. invert_lrclk = !invert_lrclk;
  454. break;
  455. default:
  456. return -EINVAL;
  457. }
  458. if (invert_lrclk) {
  459. seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
  460. serictl |= ADAU1701_SERICTL_INV_LRCLK;
  461. }
  462. adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  463. regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
  464. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
  465. ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
  466. return 0;
  467. }
  468. static int adau1701_set_bias_level(struct snd_soc_component *component,
  469. enum snd_soc_bias_level level)
  470. {
  471. unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
  472. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  473. switch (level) {
  474. case SND_SOC_BIAS_ON:
  475. break;
  476. case SND_SOC_BIAS_PREPARE:
  477. break;
  478. case SND_SOC_BIAS_STANDBY:
  479. /* Enable VREF and VREF buffer */
  480. regmap_update_bits(adau1701->regmap,
  481. ADAU1701_AUXNPOW, mask, 0x00);
  482. break;
  483. case SND_SOC_BIAS_OFF:
  484. /* Disable VREF and VREF buffer */
  485. regmap_update_bits(adau1701->regmap,
  486. ADAU1701_AUXNPOW, mask, mask);
  487. break;
  488. }
  489. return 0;
  490. }
  491. static int adau1701_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
  492. {
  493. struct snd_soc_component *component = dai->component;
  494. unsigned int mask = ADAU1701_DSPCTRL_DAM;
  495. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  496. unsigned int val;
  497. if (mute)
  498. val = 0;
  499. else
  500. val = mask;
  501. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
  502. return 0;
  503. }
  504. static int adau1701_set_sysclk(struct snd_soc_component *component, int clk_id,
  505. int source, unsigned int freq, int dir)
  506. {
  507. unsigned int val;
  508. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  509. switch (clk_id) {
  510. case ADAU1701_CLK_SRC_OSC:
  511. val = 0x0;
  512. break;
  513. case ADAU1701_CLK_SRC_MCLK:
  514. val = ADAU1701_OSCIPOW_OPD;
  515. break;
  516. default:
  517. return -EINVAL;
  518. }
  519. regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
  520. ADAU1701_OSCIPOW_OPD, val);
  521. adau1701->sysclk = freq;
  522. return 0;
  523. }
  524. static int adau1701_startup(struct snd_pcm_substream *substream,
  525. struct snd_soc_dai *dai)
  526. {
  527. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(dai->component);
  528. return sigmadsp_restrict_params(adau1701->sigmadsp, substream);
  529. }
  530. #define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
  531. SNDRV_PCM_RATE_192000)
  532. #define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  533. SNDRV_PCM_FMTBIT_S24_LE)
  534. static const struct snd_soc_dai_ops adau1701_dai_ops = {
  535. .set_fmt = adau1701_set_dai_fmt,
  536. .hw_params = adau1701_hw_params,
  537. .mute_stream = adau1701_mute_stream,
  538. .startup = adau1701_startup,
  539. .no_capture_mute = 1,
  540. };
  541. static struct snd_soc_dai_driver adau1701_dai = {
  542. .name = "adau1701",
  543. .playback = {
  544. .stream_name = "Playback",
  545. .channels_min = 2,
  546. .channels_max = 8,
  547. .rates = ADAU1701_RATES,
  548. .formats = ADAU1701_FORMATS,
  549. },
  550. .capture = {
  551. .stream_name = "Capture",
  552. .channels_min = 2,
  553. .channels_max = 8,
  554. .rates = ADAU1701_RATES,
  555. .formats = ADAU1701_FORMATS,
  556. },
  557. .ops = &adau1701_dai_ops,
  558. .symmetric_rate = 1,
  559. };
  560. #ifdef CONFIG_OF
  561. static const struct of_device_id adau1701_dt_ids[] = {
  562. { .compatible = "adi,adau1701", },
  563. { }
  564. };
  565. MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
  566. #endif
  567. static int adau1701_probe(struct snd_soc_component *component)
  568. {
  569. int i, ret;
  570. unsigned int val;
  571. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  572. ret = sigmadsp_attach(adau1701->sigmadsp, component);
  573. if (ret)
  574. return ret;
  575. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  576. adau1701->supplies);
  577. if (ret < 0) {
  578. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  579. return ret;
  580. }
  581. /*
  582. * Let the pll_clkdiv variable default to something that won't happen
  583. * at runtime. That way, we can postpone the firmware download from
  584. * adau1701_reset() to a point in time when we know the correct PLL
  585. * mode parameters.
  586. */
  587. adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
  588. /* initalize with pre-configured pll mode settings */
  589. ret = adau1701_reset(component, adau1701->pll_clkdiv, 0);
  590. if (ret < 0)
  591. goto exit_regulators_disable;
  592. /* set up pin config */
  593. val = 0;
  594. for (i = 0; i < 6; i++)
  595. val |= adau1701->pin_config[i] << (i * 4);
  596. regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
  597. val = 0;
  598. for (i = 0; i < 6; i++)
  599. val |= adau1701->pin_config[i + 6] << (i * 4);
  600. regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
  601. return 0;
  602. exit_regulators_disable:
  603. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  604. return ret;
  605. }
  606. static void adau1701_remove(struct snd_soc_component *component)
  607. {
  608. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  609. if (adau1701->gpio_nreset)
  610. gpiod_set_value_cansleep(adau1701->gpio_nreset, 0);
  611. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  612. }
  613. #ifdef CONFIG_PM
  614. static int adau1701_suspend(struct snd_soc_component *component)
  615. {
  616. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  617. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies),
  618. adau1701->supplies);
  619. return 0;
  620. }
  621. static int adau1701_resume(struct snd_soc_component *component)
  622. {
  623. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  624. int ret;
  625. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  626. adau1701->supplies);
  627. if (ret < 0) {
  628. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  629. return ret;
  630. }
  631. return adau1701_reset(component, adau1701->pll_clkdiv, 0);
  632. }
  633. #else
  634. #define adau1701_resume NULL
  635. #define adau1701_suspend NULL
  636. #endif /* CONFIG_PM */
  637. static const struct snd_soc_component_driver adau1701_component_drv = {
  638. .probe = adau1701_probe,
  639. .remove = adau1701_remove,
  640. .resume = adau1701_resume,
  641. .suspend = adau1701_suspend,
  642. .set_bias_level = adau1701_set_bias_level,
  643. .controls = adau1701_controls,
  644. .num_controls = ARRAY_SIZE(adau1701_controls),
  645. .dapm_widgets = adau1701_dapm_widgets,
  646. .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
  647. .dapm_routes = adau1701_dapm_routes,
  648. .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
  649. .set_sysclk = adau1701_set_sysclk,
  650. .use_pmdown_time = 1,
  651. .endianness = 1,
  652. };
  653. static const struct regmap_config adau1701_regmap = {
  654. .reg_bits = 16,
  655. .val_bits = 32,
  656. .max_register = ADAU1701_MAX_REGISTER,
  657. .cache_type = REGCACHE_RBTREE,
  658. .volatile_reg = adau1701_volatile_reg,
  659. .reg_write = adau1701_reg_write,
  660. .reg_read = adau1701_reg_read,
  661. };
  662. static int adau1701_i2c_probe(struct i2c_client *client)
  663. {
  664. struct adau1701 *adau1701;
  665. struct device *dev = &client->dev;
  666. int ret, i;
  667. adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
  668. if (!adau1701)
  669. return -ENOMEM;
  670. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  671. adau1701->supplies[i].supply = supply_names[i];
  672. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(adau1701->supplies),
  673. adau1701->supplies);
  674. if (ret < 0) {
  675. dev_err(dev, "Failed to get regulators: %d\n", ret);
  676. return ret;
  677. }
  678. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  679. adau1701->supplies);
  680. if (ret < 0) {
  681. dev_err(dev, "Failed to enable regulators: %d\n", ret);
  682. return ret;
  683. }
  684. adau1701->client = client;
  685. adau1701->regmap = devm_regmap_init(dev, NULL, client,
  686. &adau1701_regmap);
  687. if (IS_ERR(adau1701->regmap)) {
  688. ret = PTR_ERR(adau1701->regmap);
  689. goto exit_regulators_disable;
  690. }
  691. if (dev->of_node) {
  692. of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
  693. &adau1701->pll_clkdiv);
  694. of_property_read_u8_array(dev->of_node, "adi,pin-config",
  695. adau1701->pin_config,
  696. ARRAY_SIZE(adau1701->pin_config));
  697. }
  698. adau1701->gpio_nreset = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
  699. if (IS_ERR(adau1701->gpio_nreset)) {
  700. ret = PTR_ERR(adau1701->gpio_nreset);
  701. goto exit_regulators_disable;
  702. }
  703. adau1701->gpio_pll_mode = devm_gpiod_get_array_optional(dev, "adi,pll-mode", GPIOD_OUT_LOW);
  704. if (IS_ERR(adau1701->gpio_pll_mode)) {
  705. ret = PTR_ERR(adau1701->gpio_pll_mode);
  706. goto exit_regulators_disable;
  707. }
  708. i2c_set_clientdata(client, adau1701);
  709. adau1701->sigmadsp = devm_sigmadsp_init_i2c(client,
  710. &adau1701_sigmadsp_ops, ADAU1701_FIRMWARE);
  711. if (IS_ERR(adau1701->sigmadsp)) {
  712. ret = PTR_ERR(adau1701->sigmadsp);
  713. goto exit_regulators_disable;
  714. }
  715. ret = devm_snd_soc_register_component(&client->dev,
  716. &adau1701_component_drv,
  717. &adau1701_dai, 1);
  718. exit_regulators_disable:
  719. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  720. return ret;
  721. }
  722. static const struct i2c_device_id adau1701_i2c_id[] = {
  723. { "adau1401", 0 },
  724. { "adau1401a", 0 },
  725. { "adau1701", 0 },
  726. { "adau1702", 0 },
  727. { }
  728. };
  729. MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
  730. static struct i2c_driver adau1701_i2c_driver = {
  731. .driver = {
  732. .name = "adau1701",
  733. .of_match_table = of_match_ptr(adau1701_dt_ids),
  734. },
  735. .probe_new = adau1701_i2c_probe,
  736. .id_table = adau1701_i2c_id,
  737. };
  738. module_i2c_driver(adau1701_i2c_driver);
  739. MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
  740. MODULE_AUTHOR("Cliff Cai <[email protected]>");
  741. MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
  742. MODULE_LICENSE("GPL");