bt87x.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * bt87x.c - Brooktree Bt878/Bt879 driver for ALSA
  4. *
  5. * Copyright (c) Clemens Ladisch <[email protected]>
  6. *
  7. * based on btaudio.c by Gerd Knorr <[email protected]>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #include <linux/module.h>
  14. #include <linux/bitops.h>
  15. #include <linux/io.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/control.h>
  20. #include <sound/initval.h>
  21. MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
  22. MODULE_DESCRIPTION("Brooktree Bt87x audio driver");
  23. MODULE_LICENSE("GPL");
  24. static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
  25. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  26. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  27. static int digital_rate[SNDRV_CARDS]; /* digital input rate */
  28. static bool load_all; /* allow to load cards not the allowlist */
  29. module_param_array(index, int, NULL, 0444);
  30. MODULE_PARM_DESC(index, "Index value for Bt87x soundcard");
  31. module_param_array(id, charp, NULL, 0444);
  32. MODULE_PARM_DESC(id, "ID string for Bt87x soundcard");
  33. module_param_array(enable, bool, NULL, 0444);
  34. MODULE_PARM_DESC(enable, "Enable Bt87x soundcard");
  35. module_param_array(digital_rate, int, NULL, 0444);
  36. MODULE_PARM_DESC(digital_rate, "Digital input rate for Bt87x soundcard");
  37. module_param(load_all, bool, 0444);
  38. MODULE_PARM_DESC(load_all, "Allow to load cards not on the allowlist");
  39. /* register offsets */
  40. #define REG_INT_STAT 0x100 /* interrupt status */
  41. #define REG_INT_MASK 0x104 /* interrupt mask */
  42. #define REG_GPIO_DMA_CTL 0x10c /* audio control */
  43. #define REG_PACKET_LEN 0x110 /* audio packet lengths */
  44. #define REG_RISC_STRT_ADD 0x114 /* RISC program start address */
  45. #define REG_RISC_COUNT 0x120 /* RISC program counter */
  46. /* interrupt bits */
  47. #define INT_OFLOW (1 << 3) /* audio A/D overflow */
  48. #define INT_RISCI (1 << 11) /* RISC instruction IRQ bit set */
  49. #define INT_FBUS (1 << 12) /* FIFO overrun due to bus access latency */
  50. #define INT_FTRGT (1 << 13) /* FIFO overrun due to target latency */
  51. #define INT_FDSR (1 << 14) /* FIFO data stream resynchronization */
  52. #define INT_PPERR (1 << 15) /* PCI parity error */
  53. #define INT_RIPERR (1 << 16) /* RISC instruction parity error */
  54. #define INT_PABORT (1 << 17) /* PCI master or target abort */
  55. #define INT_OCERR (1 << 18) /* invalid opcode */
  56. #define INT_SCERR (1 << 19) /* sync counter overflow */
  57. #define INT_RISC_EN (1 << 27) /* DMA controller running */
  58. #define INT_RISCS_SHIFT 28 /* RISC status bits */
  59. /* audio control bits */
  60. #define CTL_FIFO_ENABLE (1 << 0) /* enable audio data FIFO */
  61. #define CTL_RISC_ENABLE (1 << 1) /* enable audio DMA controller */
  62. #define CTL_PKTP_4 (0 << 2) /* packet mode FIFO trigger point - 4 DWORDs */
  63. #define CTL_PKTP_8 (1 << 2) /* 8 DWORDs */
  64. #define CTL_PKTP_16 (2 << 2) /* 16 DWORDs */
  65. #define CTL_ACAP_EN (1 << 4) /* enable audio capture */
  66. #define CTL_DA_APP (1 << 5) /* GPIO input */
  67. #define CTL_DA_IOM_AFE (0 << 6) /* audio A/D input */
  68. #define CTL_DA_IOM_DA (1 << 6) /* digital audio input */
  69. #define CTL_DA_SDR_SHIFT 8 /* DDF first stage decimation rate */
  70. #define CTL_DA_SDR_MASK (0xf<< 8)
  71. #define CTL_DA_LMT (1 << 12) /* limit audio data values */
  72. #define CTL_DA_ES2 (1 << 13) /* enable DDF stage 2 */
  73. #define CTL_DA_SBR (1 << 14) /* samples rounded to 8 bits */
  74. #define CTL_DA_DPM (1 << 15) /* data packet mode */
  75. #define CTL_DA_LRD_SHIFT 16 /* ALRCK delay */
  76. #define CTL_DA_MLB (1 << 21) /* MSB/LSB format */
  77. #define CTL_DA_LRI (1 << 22) /* left/right indication */
  78. #define CTL_DA_SCE (1 << 23) /* sample clock edge */
  79. #define CTL_A_SEL_STV (0 << 24) /* TV tuner audio input */
  80. #define CTL_A_SEL_SFM (1 << 24) /* FM audio input */
  81. #define CTL_A_SEL_SML (2 << 24) /* mic/line audio input */
  82. #define CTL_A_SEL_SMXC (3 << 24) /* MUX bypass */
  83. #define CTL_A_SEL_SHIFT 24
  84. #define CTL_A_SEL_MASK (3 << 24)
  85. #define CTL_A_PWRDN (1 << 26) /* analog audio power-down */
  86. #define CTL_A_G2X (1 << 27) /* audio gain boost */
  87. #define CTL_A_GAIN_SHIFT 28 /* audio input gain */
  88. #define CTL_A_GAIN_MASK (0xf<<28)
  89. /* RISC instruction opcodes */
  90. #define RISC_WRITE (0x1 << 28) /* write FIFO data to memory at address */
  91. #define RISC_WRITEC (0x5 << 28) /* write FIFO data to memory at current address */
  92. #define RISC_SKIP (0x2 << 28) /* skip FIFO data */
  93. #define RISC_JUMP (0x7 << 28) /* jump to address */
  94. #define RISC_SYNC (0x8 << 28) /* synchronize with FIFO */
  95. /* RISC instruction bits */
  96. #define RISC_BYTES_ENABLE (0xf << 12) /* byte enable bits */
  97. #define RISC_RESYNC ( 1 << 15) /* disable FDSR errors */
  98. #define RISC_SET_STATUS_SHIFT 16 /* set status bits */
  99. #define RISC_RESET_STATUS_SHIFT 20 /* clear status bits */
  100. #define RISC_IRQ ( 1 << 24) /* interrupt */
  101. #define RISC_EOL ( 1 << 26) /* end of line */
  102. #define RISC_SOL ( 1 << 27) /* start of line */
  103. /* SYNC status bits values */
  104. #define RISC_SYNC_FM1 0x6
  105. #define RISC_SYNC_VRO 0xc
  106. #define ANALOG_CLOCK 1792000
  107. #ifdef CONFIG_SND_BT87X_OVERCLOCK
  108. #define CLOCK_DIV_MIN 1
  109. #else
  110. #define CLOCK_DIV_MIN 4
  111. #endif
  112. #define CLOCK_DIV_MAX 15
  113. #define ERROR_INTERRUPTS (INT_FBUS | INT_FTRGT | INT_PPERR | \
  114. INT_RIPERR | INT_PABORT | INT_OCERR)
  115. #define MY_INTERRUPTS (INT_RISCI | ERROR_INTERRUPTS)
  116. /* SYNC, one WRITE per line, one extra WRITE per page boundary, SYNC, JUMP */
  117. #define MAX_RISC_SIZE ((1 + 255 + (PAGE_ALIGN(255 * 4092) / PAGE_SIZE - 1) + 1 + 1) * 8)
  118. /* Cards with configuration information */
  119. enum snd_bt87x_boardid {
  120. SND_BT87X_BOARD_UNKNOWN,
  121. SND_BT87X_BOARD_GENERIC, /* both an & dig interfaces, 32kHz */
  122. SND_BT87X_BOARD_ANALOG, /* board with no external A/D */
  123. SND_BT87X_BOARD_OSPREY2x0,
  124. SND_BT87X_BOARD_OSPREY440,
  125. SND_BT87X_BOARD_AVPHONE98,
  126. };
  127. /* Card configuration */
  128. struct snd_bt87x_board {
  129. int dig_rate; /* Digital input sampling rate */
  130. u32 digital_fmt; /* Register settings for digital input */
  131. unsigned no_analog:1; /* No analog input */
  132. unsigned no_digital:1; /* No digital input */
  133. };
  134. static const struct snd_bt87x_board snd_bt87x_boards[] = {
  135. [SND_BT87X_BOARD_UNKNOWN] = {
  136. .dig_rate = 32000, /* just a guess */
  137. },
  138. [SND_BT87X_BOARD_GENERIC] = {
  139. .dig_rate = 32000,
  140. },
  141. [SND_BT87X_BOARD_ANALOG] = {
  142. .no_digital = 1,
  143. },
  144. [SND_BT87X_BOARD_OSPREY2x0] = {
  145. .dig_rate = 44100,
  146. .digital_fmt = CTL_DA_LRI | (1 << CTL_DA_LRD_SHIFT),
  147. },
  148. [SND_BT87X_BOARD_OSPREY440] = {
  149. .dig_rate = 32000,
  150. .digital_fmt = CTL_DA_LRI | (1 << CTL_DA_LRD_SHIFT),
  151. .no_analog = 1,
  152. },
  153. [SND_BT87X_BOARD_AVPHONE98] = {
  154. .dig_rate = 48000,
  155. },
  156. };
  157. struct snd_bt87x {
  158. struct snd_card *card;
  159. struct pci_dev *pci;
  160. struct snd_bt87x_board board;
  161. void __iomem *mmio;
  162. int irq;
  163. spinlock_t reg_lock;
  164. unsigned long opened;
  165. struct snd_pcm_substream *substream;
  166. struct snd_dma_buffer dma_risc;
  167. unsigned int line_bytes;
  168. unsigned int lines;
  169. u32 reg_control;
  170. u32 interrupt_mask;
  171. int current_line;
  172. int pci_parity_errors;
  173. };
  174. enum { DEVICE_DIGITAL, DEVICE_ANALOG };
  175. static inline u32 snd_bt87x_readl(struct snd_bt87x *chip, u32 reg)
  176. {
  177. return readl(chip->mmio + reg);
  178. }
  179. static inline void snd_bt87x_writel(struct snd_bt87x *chip, u32 reg, u32 value)
  180. {
  181. writel(value, chip->mmio + reg);
  182. }
  183. static int snd_bt87x_create_risc(struct snd_bt87x *chip, struct snd_pcm_substream *substream,
  184. unsigned int periods, unsigned int period_bytes)
  185. {
  186. unsigned int i, offset;
  187. __le32 *risc;
  188. if (chip->dma_risc.area == NULL) {
  189. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  190. PAGE_ALIGN(MAX_RISC_SIZE), &chip->dma_risc) < 0)
  191. return -ENOMEM;
  192. }
  193. risc = (__le32 *)chip->dma_risc.area;
  194. offset = 0;
  195. *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_FM1);
  196. *risc++ = cpu_to_le32(0);
  197. for (i = 0; i < periods; ++i) {
  198. u32 rest;
  199. rest = period_bytes;
  200. do {
  201. u32 cmd, len;
  202. unsigned int addr;
  203. len = PAGE_SIZE - (offset % PAGE_SIZE);
  204. if (len > rest)
  205. len = rest;
  206. cmd = RISC_WRITE | len;
  207. if (rest == period_bytes) {
  208. u32 block = i * 16 / periods;
  209. cmd |= RISC_SOL;
  210. cmd |= block << RISC_SET_STATUS_SHIFT;
  211. cmd |= (~block & 0xf) << RISC_RESET_STATUS_SHIFT;
  212. }
  213. if (len == rest)
  214. cmd |= RISC_EOL | RISC_IRQ;
  215. *risc++ = cpu_to_le32(cmd);
  216. addr = snd_pcm_sgbuf_get_addr(substream, offset);
  217. *risc++ = cpu_to_le32(addr);
  218. offset += len;
  219. rest -= len;
  220. } while (rest > 0);
  221. }
  222. *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_VRO);
  223. *risc++ = cpu_to_le32(0);
  224. *risc++ = cpu_to_le32(RISC_JUMP);
  225. *risc++ = cpu_to_le32(chip->dma_risc.addr);
  226. chip->line_bytes = period_bytes;
  227. chip->lines = periods;
  228. return 0;
  229. }
  230. static void snd_bt87x_free_risc(struct snd_bt87x *chip)
  231. {
  232. if (chip->dma_risc.area) {
  233. snd_dma_free_pages(&chip->dma_risc);
  234. chip->dma_risc.area = NULL;
  235. }
  236. }
  237. static void snd_bt87x_pci_error(struct snd_bt87x *chip, unsigned int status)
  238. {
  239. int pci_status = pci_status_get_and_clear_errors(chip->pci);
  240. if (pci_status != PCI_STATUS_DETECTED_PARITY)
  241. dev_err(chip->card->dev,
  242. "Aieee - PCI error! status %#08x, PCI status %#04x\n",
  243. status & ERROR_INTERRUPTS, pci_status);
  244. else {
  245. dev_err(chip->card->dev,
  246. "Aieee - PCI parity error detected!\n");
  247. /* error 'handling' similar to aic7xxx_pci.c: */
  248. chip->pci_parity_errors++;
  249. if (chip->pci_parity_errors > 20) {
  250. dev_err(chip->card->dev,
  251. "Too many PCI parity errors observed.\n");
  252. dev_err(chip->card->dev,
  253. "Some device on this bus is generating bad parity.\n");
  254. dev_err(chip->card->dev,
  255. "This is an error *observed by*, not *generated by*, this card.\n");
  256. dev_err(chip->card->dev,
  257. "PCI parity error checking has been disabled.\n");
  258. chip->interrupt_mask &= ~(INT_PPERR | INT_RIPERR);
  259. snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
  260. }
  261. }
  262. }
  263. static irqreturn_t snd_bt87x_interrupt(int irq, void *dev_id)
  264. {
  265. struct snd_bt87x *chip = dev_id;
  266. unsigned int status, irq_status;
  267. status = snd_bt87x_readl(chip, REG_INT_STAT);
  268. irq_status = status & chip->interrupt_mask;
  269. if (!irq_status)
  270. return IRQ_NONE;
  271. snd_bt87x_writel(chip, REG_INT_STAT, irq_status);
  272. if (irq_status & ERROR_INTERRUPTS) {
  273. if (irq_status & (INT_FBUS | INT_FTRGT))
  274. dev_warn(chip->card->dev,
  275. "FIFO overrun, status %#08x\n", status);
  276. if (irq_status & INT_OCERR)
  277. dev_err(chip->card->dev,
  278. "internal RISC error, status %#08x\n", status);
  279. if (irq_status & (INT_PPERR | INT_RIPERR | INT_PABORT))
  280. snd_bt87x_pci_error(chip, irq_status);
  281. }
  282. if ((irq_status & INT_RISCI) && (chip->reg_control & CTL_ACAP_EN)) {
  283. int current_block, irq_block;
  284. /* assume that exactly one line has been recorded */
  285. chip->current_line = (chip->current_line + 1) % chip->lines;
  286. /* but check if some interrupts have been skipped */
  287. current_block = chip->current_line * 16 / chip->lines;
  288. irq_block = status >> INT_RISCS_SHIFT;
  289. if (current_block != irq_block)
  290. chip->current_line = DIV_ROUND_UP(irq_block * chip->lines,
  291. 16);
  292. snd_pcm_period_elapsed(chip->substream);
  293. }
  294. return IRQ_HANDLED;
  295. }
  296. static const struct snd_pcm_hardware snd_bt87x_digital_hw = {
  297. .info = SNDRV_PCM_INFO_MMAP |
  298. SNDRV_PCM_INFO_INTERLEAVED |
  299. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  300. SNDRV_PCM_INFO_MMAP_VALID |
  301. SNDRV_PCM_INFO_BATCH,
  302. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  303. .rates = 0, /* set at runtime */
  304. .channels_min = 2,
  305. .channels_max = 2,
  306. .buffer_bytes_max = 255 * 4092,
  307. .period_bytes_min = 32,
  308. .period_bytes_max = 4092,
  309. .periods_min = 2,
  310. .periods_max = 255,
  311. };
  312. static const struct snd_pcm_hardware snd_bt87x_analog_hw = {
  313. .info = SNDRV_PCM_INFO_MMAP |
  314. SNDRV_PCM_INFO_INTERLEAVED |
  315. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  316. SNDRV_PCM_INFO_MMAP_VALID |
  317. SNDRV_PCM_INFO_BATCH,
  318. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  319. .rates = SNDRV_PCM_RATE_KNOT,
  320. .rate_min = ANALOG_CLOCK / CLOCK_DIV_MAX,
  321. .rate_max = ANALOG_CLOCK / CLOCK_DIV_MIN,
  322. .channels_min = 1,
  323. .channels_max = 1,
  324. .buffer_bytes_max = 255 * 4092,
  325. .period_bytes_min = 32,
  326. .period_bytes_max = 4092,
  327. .periods_min = 2,
  328. .periods_max = 255,
  329. };
  330. static int snd_bt87x_set_digital_hw(struct snd_bt87x *chip, struct snd_pcm_runtime *runtime)
  331. {
  332. chip->reg_control |= CTL_DA_IOM_DA | CTL_A_PWRDN;
  333. runtime->hw = snd_bt87x_digital_hw;
  334. runtime->hw.rates = snd_pcm_rate_to_rate_bit(chip->board.dig_rate);
  335. runtime->hw.rate_min = chip->board.dig_rate;
  336. runtime->hw.rate_max = chip->board.dig_rate;
  337. return 0;
  338. }
  339. static int snd_bt87x_set_analog_hw(struct snd_bt87x *chip, struct snd_pcm_runtime *runtime)
  340. {
  341. static const struct snd_ratnum analog_clock = {
  342. .num = ANALOG_CLOCK,
  343. .den_min = CLOCK_DIV_MIN,
  344. .den_max = CLOCK_DIV_MAX,
  345. .den_step = 1
  346. };
  347. static const struct snd_pcm_hw_constraint_ratnums constraint_rates = {
  348. .nrats = 1,
  349. .rats = &analog_clock
  350. };
  351. chip->reg_control &= ~(CTL_DA_IOM_DA | CTL_A_PWRDN);
  352. runtime->hw = snd_bt87x_analog_hw;
  353. return snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  354. &constraint_rates);
  355. }
  356. static int snd_bt87x_pcm_open(struct snd_pcm_substream *substream)
  357. {
  358. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  359. struct snd_pcm_runtime *runtime = substream->runtime;
  360. int err;
  361. if (test_and_set_bit(0, &chip->opened))
  362. return -EBUSY;
  363. if (substream->pcm->device == DEVICE_DIGITAL)
  364. err = snd_bt87x_set_digital_hw(chip, runtime);
  365. else
  366. err = snd_bt87x_set_analog_hw(chip, runtime);
  367. if (err < 0)
  368. goto _error;
  369. err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  370. if (err < 0)
  371. goto _error;
  372. chip->substream = substream;
  373. return 0;
  374. _error:
  375. clear_bit(0, &chip->opened);
  376. smp_mb__after_atomic();
  377. return err;
  378. }
  379. static int snd_bt87x_close(struct snd_pcm_substream *substream)
  380. {
  381. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  382. spin_lock_irq(&chip->reg_lock);
  383. chip->reg_control |= CTL_A_PWRDN;
  384. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  385. spin_unlock_irq(&chip->reg_lock);
  386. chip->substream = NULL;
  387. clear_bit(0, &chip->opened);
  388. smp_mb__after_atomic();
  389. return 0;
  390. }
  391. static int snd_bt87x_hw_params(struct snd_pcm_substream *substream,
  392. struct snd_pcm_hw_params *hw_params)
  393. {
  394. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  395. return snd_bt87x_create_risc(chip, substream,
  396. params_periods(hw_params),
  397. params_period_bytes(hw_params));
  398. }
  399. static int snd_bt87x_hw_free(struct snd_pcm_substream *substream)
  400. {
  401. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  402. snd_bt87x_free_risc(chip);
  403. return 0;
  404. }
  405. static int snd_bt87x_prepare(struct snd_pcm_substream *substream)
  406. {
  407. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  408. struct snd_pcm_runtime *runtime = substream->runtime;
  409. int decimation;
  410. spin_lock_irq(&chip->reg_lock);
  411. chip->reg_control &= ~(CTL_DA_SDR_MASK | CTL_DA_SBR);
  412. decimation = (ANALOG_CLOCK + runtime->rate / 4) / runtime->rate;
  413. chip->reg_control |= decimation << CTL_DA_SDR_SHIFT;
  414. if (runtime->format == SNDRV_PCM_FORMAT_S8)
  415. chip->reg_control |= CTL_DA_SBR;
  416. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  417. spin_unlock_irq(&chip->reg_lock);
  418. return 0;
  419. }
  420. static int snd_bt87x_start(struct snd_bt87x *chip)
  421. {
  422. spin_lock(&chip->reg_lock);
  423. chip->current_line = 0;
  424. chip->reg_control |= CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN;
  425. snd_bt87x_writel(chip, REG_RISC_STRT_ADD, chip->dma_risc.addr);
  426. snd_bt87x_writel(chip, REG_PACKET_LEN,
  427. chip->line_bytes | (chip->lines << 16));
  428. snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
  429. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  430. spin_unlock(&chip->reg_lock);
  431. return 0;
  432. }
  433. static int snd_bt87x_stop(struct snd_bt87x *chip)
  434. {
  435. spin_lock(&chip->reg_lock);
  436. chip->reg_control &= ~(CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN);
  437. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  438. snd_bt87x_writel(chip, REG_INT_MASK, 0);
  439. snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
  440. spin_unlock(&chip->reg_lock);
  441. return 0;
  442. }
  443. static int snd_bt87x_trigger(struct snd_pcm_substream *substream, int cmd)
  444. {
  445. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  446. switch (cmd) {
  447. case SNDRV_PCM_TRIGGER_START:
  448. return snd_bt87x_start(chip);
  449. case SNDRV_PCM_TRIGGER_STOP:
  450. return snd_bt87x_stop(chip);
  451. default:
  452. return -EINVAL;
  453. }
  454. }
  455. static snd_pcm_uframes_t snd_bt87x_pointer(struct snd_pcm_substream *substream)
  456. {
  457. struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
  458. struct snd_pcm_runtime *runtime = substream->runtime;
  459. return (snd_pcm_uframes_t)bytes_to_frames(runtime, chip->current_line * chip->line_bytes);
  460. }
  461. static const struct snd_pcm_ops snd_bt87x_pcm_ops = {
  462. .open = snd_bt87x_pcm_open,
  463. .close = snd_bt87x_close,
  464. .hw_params = snd_bt87x_hw_params,
  465. .hw_free = snd_bt87x_hw_free,
  466. .prepare = snd_bt87x_prepare,
  467. .trigger = snd_bt87x_trigger,
  468. .pointer = snd_bt87x_pointer,
  469. };
  470. static int snd_bt87x_capture_volume_info(struct snd_kcontrol *kcontrol,
  471. struct snd_ctl_elem_info *info)
  472. {
  473. info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  474. info->count = 1;
  475. info->value.integer.min = 0;
  476. info->value.integer.max = 15;
  477. return 0;
  478. }
  479. static int snd_bt87x_capture_volume_get(struct snd_kcontrol *kcontrol,
  480. struct snd_ctl_elem_value *value)
  481. {
  482. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  483. value->value.integer.value[0] = (chip->reg_control & CTL_A_GAIN_MASK) >> CTL_A_GAIN_SHIFT;
  484. return 0;
  485. }
  486. static int snd_bt87x_capture_volume_put(struct snd_kcontrol *kcontrol,
  487. struct snd_ctl_elem_value *value)
  488. {
  489. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  490. u32 old_control;
  491. int changed;
  492. spin_lock_irq(&chip->reg_lock);
  493. old_control = chip->reg_control;
  494. chip->reg_control = (chip->reg_control & ~CTL_A_GAIN_MASK)
  495. | (value->value.integer.value[0] << CTL_A_GAIN_SHIFT);
  496. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  497. changed = old_control != chip->reg_control;
  498. spin_unlock_irq(&chip->reg_lock);
  499. return changed;
  500. }
  501. static const struct snd_kcontrol_new snd_bt87x_capture_volume = {
  502. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  503. .name = "Capture Volume",
  504. .info = snd_bt87x_capture_volume_info,
  505. .get = snd_bt87x_capture_volume_get,
  506. .put = snd_bt87x_capture_volume_put,
  507. };
  508. #define snd_bt87x_capture_boost_info snd_ctl_boolean_mono_info
  509. static int snd_bt87x_capture_boost_get(struct snd_kcontrol *kcontrol,
  510. struct snd_ctl_elem_value *value)
  511. {
  512. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  513. value->value.integer.value[0] = !! (chip->reg_control & CTL_A_G2X);
  514. return 0;
  515. }
  516. static int snd_bt87x_capture_boost_put(struct snd_kcontrol *kcontrol,
  517. struct snd_ctl_elem_value *value)
  518. {
  519. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  520. u32 old_control;
  521. int changed;
  522. spin_lock_irq(&chip->reg_lock);
  523. old_control = chip->reg_control;
  524. chip->reg_control = (chip->reg_control & ~CTL_A_G2X)
  525. | (value->value.integer.value[0] ? CTL_A_G2X : 0);
  526. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  527. changed = chip->reg_control != old_control;
  528. spin_unlock_irq(&chip->reg_lock);
  529. return changed;
  530. }
  531. static const struct snd_kcontrol_new snd_bt87x_capture_boost = {
  532. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  533. .name = "Capture Boost",
  534. .info = snd_bt87x_capture_boost_info,
  535. .get = snd_bt87x_capture_boost_get,
  536. .put = snd_bt87x_capture_boost_put,
  537. };
  538. static int snd_bt87x_capture_source_info(struct snd_kcontrol *kcontrol,
  539. struct snd_ctl_elem_info *info)
  540. {
  541. static const char *const texts[3] = {"TV Tuner", "FM", "Mic/Line"};
  542. return snd_ctl_enum_info(info, 1, 3, texts);
  543. }
  544. static int snd_bt87x_capture_source_get(struct snd_kcontrol *kcontrol,
  545. struct snd_ctl_elem_value *value)
  546. {
  547. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  548. value->value.enumerated.item[0] = (chip->reg_control & CTL_A_SEL_MASK) >> CTL_A_SEL_SHIFT;
  549. return 0;
  550. }
  551. static int snd_bt87x_capture_source_put(struct snd_kcontrol *kcontrol,
  552. struct snd_ctl_elem_value *value)
  553. {
  554. struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
  555. u32 old_control;
  556. int changed;
  557. spin_lock_irq(&chip->reg_lock);
  558. old_control = chip->reg_control;
  559. chip->reg_control = (chip->reg_control & ~CTL_A_SEL_MASK)
  560. | (value->value.enumerated.item[0] << CTL_A_SEL_SHIFT);
  561. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  562. changed = chip->reg_control != old_control;
  563. spin_unlock_irq(&chip->reg_lock);
  564. return changed;
  565. }
  566. static const struct snd_kcontrol_new snd_bt87x_capture_source = {
  567. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  568. .name = "Capture Source",
  569. .info = snd_bt87x_capture_source_info,
  570. .get = snd_bt87x_capture_source_get,
  571. .put = snd_bt87x_capture_source_put,
  572. };
  573. static void snd_bt87x_free(struct snd_card *card)
  574. {
  575. struct snd_bt87x *chip = card->private_data;
  576. snd_bt87x_stop(chip);
  577. }
  578. static int snd_bt87x_pcm(struct snd_bt87x *chip, int device, char *name)
  579. {
  580. int err;
  581. struct snd_pcm *pcm;
  582. err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
  583. if (err < 0)
  584. return err;
  585. pcm->private_data = chip;
  586. strcpy(pcm->name, name);
  587. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_bt87x_pcm_ops);
  588. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
  589. &chip->pci->dev,
  590. 128 * 1024,
  591. ALIGN(255 * 4092, 1024));
  592. return 0;
  593. }
  594. static int snd_bt87x_create(struct snd_card *card,
  595. struct pci_dev *pci)
  596. {
  597. struct snd_bt87x *chip = card->private_data;
  598. int err;
  599. err = pcim_enable_device(pci);
  600. if (err < 0)
  601. return err;
  602. chip->card = card;
  603. chip->pci = pci;
  604. chip->irq = -1;
  605. spin_lock_init(&chip->reg_lock);
  606. err = pcim_iomap_regions(pci, 1 << 0, "Bt87x audio");
  607. if (err < 0)
  608. return err;
  609. chip->mmio = pcim_iomap_table(pci)[0];
  610. chip->reg_control = CTL_A_PWRDN | CTL_DA_ES2 |
  611. CTL_PKTP_16 | (15 << CTL_DA_SDR_SHIFT);
  612. chip->interrupt_mask = MY_INTERRUPTS;
  613. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  614. snd_bt87x_writel(chip, REG_INT_MASK, 0);
  615. snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
  616. err = devm_request_irq(&pci->dev, pci->irq, snd_bt87x_interrupt,
  617. IRQF_SHARED, KBUILD_MODNAME, chip);
  618. if (err < 0) {
  619. dev_err(card->dev, "cannot grab irq %d\n", pci->irq);
  620. return err;
  621. }
  622. chip->irq = pci->irq;
  623. card->sync_irq = chip->irq;
  624. card->private_free = snd_bt87x_free;
  625. pci_set_master(pci);
  626. return 0;
  627. }
  628. #define BT_DEVICE(chip, subvend, subdev, id) \
  629. { .vendor = PCI_VENDOR_ID_BROOKTREE, \
  630. .device = chip, \
  631. .subvendor = subvend, .subdevice = subdev, \
  632. .driver_data = SND_BT87X_BOARD_ ## id }
  633. /* driver_data is the card id for that device */
  634. static const struct pci_device_id snd_bt87x_ids[] = {
  635. /* Hauppauge WinTV series */
  636. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0x13eb, GENERIC),
  637. /* Hauppauge WinTV series */
  638. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_879, 0x0070, 0x13eb, GENERIC),
  639. /* Viewcast Osprey 200 */
  640. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0xff01, OSPREY2x0),
  641. /* Viewcast Osprey 440 (rate is configurable via gpio) */
  642. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0xff07, OSPREY440),
  643. /* ATI TV-Wonder */
  644. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1002, 0x0001, GENERIC),
  645. /* Leadtek Winfast tv 2000xp delux */
  646. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x107d, 0x6606, GENERIC),
  647. /* Pinnacle PCTV */
  648. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x11bd, 0x0012, GENERIC),
  649. /* Voodoo TV 200 */
  650. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x121a, 0x3000, GENERIC),
  651. /* Askey Computer Corp. MagicTView'99 */
  652. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x144f, 0x3000, GENERIC),
  653. /* AVerMedia Studio No. 103, 203, ...? */
  654. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1461, 0x0003, AVPHONE98),
  655. /* Prolink PixelView PV-M4900 */
  656. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1554, 0x4011, GENERIC),
  657. /* Pinnacle Studio PCTV rave */
  658. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0xbd11, 0x1200, GENERIC),
  659. { }
  660. };
  661. MODULE_DEVICE_TABLE(pci, snd_bt87x_ids);
  662. /* cards known not to have audio
  663. * (DVB cards use the audio function to transfer MPEG data) */
  664. static struct {
  665. unsigned short subvendor, subdevice;
  666. } denylist[] = {
  667. {0x0071, 0x0101}, /* Nebula Electronics DigiTV */
  668. {0x11bd, 0x001c}, /* Pinnacle PCTV Sat */
  669. {0x11bd, 0x0026}, /* Pinnacle PCTV SAT CI */
  670. {0x1461, 0x0761}, /* AVermedia AverTV DVB-T */
  671. {0x1461, 0x0771}, /* AVermedia DVB-T 771 */
  672. {0x1822, 0x0001}, /* Twinhan VisionPlus DVB-T */
  673. {0x18ac, 0xd500}, /* DVICO FusionHDTV 5 Lite */
  674. {0x18ac, 0xdb10}, /* DVICO FusionHDTV DVB-T Lite */
  675. {0x18ac, 0xdb11}, /* Ultraview DVB-T Lite */
  676. {0x270f, 0xfc00}, /* Chaintech Digitop DST-1000 DVB-S */
  677. {0x7063, 0x2000}, /* pcHDTV HD-2000 TV */
  678. };
  679. static struct pci_driver driver;
  680. /* return the id of the card, or a negative value if it's on the denylist */
  681. static int snd_bt87x_detect_card(struct pci_dev *pci)
  682. {
  683. int i;
  684. const struct pci_device_id *supported;
  685. supported = pci_match_id(snd_bt87x_ids, pci);
  686. if (supported && supported->driver_data > 0)
  687. return supported->driver_data;
  688. for (i = 0; i < ARRAY_SIZE(denylist); ++i)
  689. if (denylist[i].subvendor == pci->subsystem_vendor &&
  690. denylist[i].subdevice == pci->subsystem_device) {
  691. dev_dbg(&pci->dev,
  692. "card %#04x-%#04x:%#04x has no audio\n",
  693. pci->device, pci->subsystem_vendor, pci->subsystem_device);
  694. return -EBUSY;
  695. }
  696. dev_info(&pci->dev, "unknown card %#04x-%#04x:%#04x\n",
  697. pci->device, pci->subsystem_vendor, pci->subsystem_device);
  698. dev_info(&pci->dev, "please mail id, board name, and, "
  699. "if it works, the correct digital_rate option to "
  700. "<[email protected]>\n");
  701. return SND_BT87X_BOARD_UNKNOWN;
  702. }
  703. static int __snd_bt87x_probe(struct pci_dev *pci,
  704. const struct pci_device_id *pci_id)
  705. {
  706. static int dev;
  707. struct snd_card *card;
  708. struct snd_bt87x *chip;
  709. int err;
  710. enum snd_bt87x_boardid boardid;
  711. if (!pci_id->driver_data) {
  712. err = snd_bt87x_detect_card(pci);
  713. if (err < 0)
  714. return -ENODEV;
  715. boardid = err;
  716. } else
  717. boardid = pci_id->driver_data;
  718. if (dev >= SNDRV_CARDS)
  719. return -ENODEV;
  720. if (!enable[dev]) {
  721. ++dev;
  722. return -ENOENT;
  723. }
  724. err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  725. sizeof(*chip), &card);
  726. if (err < 0)
  727. return err;
  728. chip = card->private_data;
  729. err = snd_bt87x_create(card, pci);
  730. if (err < 0)
  731. return err;
  732. memcpy(&chip->board, &snd_bt87x_boards[boardid], sizeof(chip->board));
  733. if (!chip->board.no_digital) {
  734. if (digital_rate[dev] > 0)
  735. chip->board.dig_rate = digital_rate[dev];
  736. chip->reg_control |= chip->board.digital_fmt;
  737. err = snd_bt87x_pcm(chip, DEVICE_DIGITAL, "Bt87x Digital");
  738. if (err < 0)
  739. return err;
  740. }
  741. if (!chip->board.no_analog) {
  742. err = snd_bt87x_pcm(chip, DEVICE_ANALOG, "Bt87x Analog");
  743. if (err < 0)
  744. return err;
  745. err = snd_ctl_add(card, snd_ctl_new1(
  746. &snd_bt87x_capture_volume, chip));
  747. if (err < 0)
  748. return err;
  749. err = snd_ctl_add(card, snd_ctl_new1(
  750. &snd_bt87x_capture_boost, chip));
  751. if (err < 0)
  752. return err;
  753. err = snd_ctl_add(card, snd_ctl_new1(
  754. &snd_bt87x_capture_source, chip));
  755. if (err < 0)
  756. return err;
  757. }
  758. dev_info(card->dev, "bt87x%d: Using board %d, %sanalog, %sdigital "
  759. "(rate %d Hz)\n", dev, boardid,
  760. chip->board.no_analog ? "no " : "",
  761. chip->board.no_digital ? "no " : "", chip->board.dig_rate);
  762. strcpy(card->driver, "Bt87x");
  763. sprintf(card->shortname, "Brooktree Bt%x", pci->device);
  764. sprintf(card->longname, "%s at %#llx, irq %i",
  765. card->shortname, (unsigned long long)pci_resource_start(pci, 0),
  766. chip->irq);
  767. strcpy(card->mixername, "Bt87x");
  768. err = snd_card_register(card);
  769. if (err < 0)
  770. return err;
  771. pci_set_drvdata(pci, card);
  772. ++dev;
  773. return 0;
  774. }
  775. static int snd_bt87x_probe(struct pci_dev *pci,
  776. const struct pci_device_id *pci_id)
  777. {
  778. return snd_card_free_on_error(&pci->dev, __snd_bt87x_probe(pci, pci_id));
  779. }
  780. /* default entries for all Bt87x cards - it's not exported */
  781. /* driver_data is set to 0 to call detection */
  782. static const struct pci_device_id snd_bt87x_default_ids[] = {
  783. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, PCI_ANY_ID, PCI_ANY_ID, UNKNOWN),
  784. BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_879, PCI_ANY_ID, PCI_ANY_ID, UNKNOWN),
  785. { }
  786. };
  787. static struct pci_driver driver = {
  788. .name = KBUILD_MODNAME,
  789. .id_table = snd_bt87x_ids,
  790. .probe = snd_bt87x_probe,
  791. };
  792. static int __init alsa_card_bt87x_init(void)
  793. {
  794. if (load_all)
  795. driver.id_table = snd_bt87x_default_ids;
  796. return pci_register_driver(&driver);
  797. }
  798. static void __exit alsa_card_bt87x_exit(void)
  799. {
  800. pci_unregister_driver(&driver);
  801. }
  802. module_init(alsa_card_bt87x_init)
  803. module_exit(alsa_card_bt87x_exit)