rcar3.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas USB driver R-Car Gen. 3 initialization and power control
  4. *
  5. * Copyright (C) 2016-2019 Renesas Electronics Corporation
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include "common.h"
  10. #include "rcar3.h"
  11. #define LPSTS 0x102
  12. #define UGCTRL 0x180 /* 32-bit register */
  13. #define UGCTRL2 0x184 /* 32-bit register */
  14. #define UGSTS 0x188 /* 32-bit register */
  15. /* Low Power Status register (LPSTS) */
  16. #define LPSTS_SUSPM 0x4000
  17. /* R-Car D3 only: USB General control register (UGCTRL) */
  18. #define UGCTRL_PLLRESET 0x00000001
  19. #define UGCTRL_CONNECT 0x00000004
  20. /*
  21. * USB General control register 2 (UGCTRL2)
  22. * Remarks: bit[31:11] and bit[9:6] should be 0
  23. */
  24. #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
  25. #define UGCTRL2_USB0SEL_HSUSB 0x00000020
  26. #define UGCTRL2_USB0SEL_OTG 0x00000030
  27. #define UGCTRL2_VBUSSEL 0x00000400
  28. /* R-Car D3 only: USB General status register (UGSTS) */
  29. #define UGSTS_LOCK 0x00000100
  30. static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
  31. {
  32. iowrite32(data, priv->base + reg);
  33. }
  34. static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
  35. {
  36. return ioread32(priv->base + reg);
  37. }
  38. static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
  39. {
  40. usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
  41. }
  42. static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
  43. void __iomem *base, int enable)
  44. {
  45. struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
  46. usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
  47. if (enable) {
  48. usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
  49. /* The controller on R-Car Gen3 needs to wait up to 45 usec */
  50. usleep_range(45, 90);
  51. } else {
  52. usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
  53. }
  54. return 0;
  55. }
  56. /* R-Car D3 needs to release UGCTRL.PLLRESET */
  57. static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
  58. void __iomem *base, int enable)
  59. {
  60. struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
  61. u32 val;
  62. int timeout = 1000;
  63. if (enable) {
  64. usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
  65. usbhs_rcar3_set_ugctrl2(priv,
  66. UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
  67. usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
  68. do {
  69. val = usbhs_read32(priv, UGSTS);
  70. udelay(1);
  71. } while (!(val & UGSTS_LOCK) && timeout--);
  72. usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
  73. } else {
  74. usbhs_write32(priv, UGCTRL, 0);
  75. usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
  76. usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
  77. }
  78. return 0;
  79. }
  80. const struct renesas_usbhs_platform_info usbhs_rcar_gen3_plat_info = {
  81. .platform_callback = {
  82. .power_ctrl = usbhs_rcar3_power_ctrl,
  83. .get_id = usbhs_get_id_as_gadget,
  84. },
  85. .driver_param = {
  86. .has_usb_dmac = 1,
  87. .multi_clks = 1,
  88. .has_new_pipe_configs = 1,
  89. },
  90. };
  91. const struct renesas_usbhs_platform_info usbhs_rcar_gen3_with_pll_plat_info = {
  92. .platform_callback = {
  93. .power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
  94. .get_id = usbhs_get_id_as_gadget,
  95. },
  96. .driver_param = {
  97. .has_usb_dmac = 1,
  98. .multi_clks = 1,
  99. .has_new_pipe_configs = 1,
  100. },
  101. };