common.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-1.0+ */
  2. /*
  3. * Renesas USB driver
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. * Copyright (C) 2019 Renesas Electronics Corporation
  7. * Kuninori Morimoto <[email protected]>
  8. */
  9. #ifndef RENESAS_USB_DRIVER_H
  10. #define RENESAS_USB_DRIVER_H
  11. #include <linux/clk.h>
  12. #include <linux/extcon.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/reset.h>
  15. #include <linux/usb/renesas_usbhs.h>
  16. struct usbhs_priv;
  17. #include "mod.h"
  18. #include "pipe.h"
  19. /*
  20. *
  21. * register define
  22. *
  23. */
  24. #define SYSCFG 0x0000
  25. #define BUSWAIT 0x0002
  26. #define DVSTCTR 0x0008
  27. #define TESTMODE 0x000C
  28. #define CFIFO 0x0014
  29. #define CFIFOSEL 0x0020
  30. #define CFIFOCTR 0x0022
  31. #define D0FIFO 0x0100
  32. #define D0FIFOSEL 0x0028
  33. #define D0FIFOCTR 0x002A
  34. #define D1FIFO 0x0120
  35. #define D1FIFOSEL 0x002C
  36. #define D1FIFOCTR 0x002E
  37. #define INTENB0 0x0030
  38. #define INTENB1 0x0032
  39. #define BRDYENB 0x0036
  40. #define NRDYENB 0x0038
  41. #define BEMPENB 0x003A
  42. #define INTSTS0 0x0040
  43. #define INTSTS1 0x0042
  44. #define BRDYSTS 0x0046
  45. #define NRDYSTS 0x0048
  46. #define BEMPSTS 0x004A
  47. #define FRMNUM 0x004C
  48. #define USBREQ 0x0054 /* USB request type register */
  49. #define USBVAL 0x0056 /* USB request value register */
  50. #define USBINDX 0x0058 /* USB request index register */
  51. #define USBLENG 0x005A /* USB request length register */
  52. #define DCPCFG 0x005C
  53. #define DCPMAXP 0x005E
  54. #define DCPCTR 0x0060
  55. #define PIPESEL 0x0064
  56. #define PIPECFG 0x0068
  57. #define PIPEBUF 0x006A
  58. #define PIPEMAXP 0x006C
  59. #define PIPEPERI 0x006E
  60. #define PIPEnCTR 0x0070
  61. #define PIPE1TRE 0x0090
  62. #define PIPE1TRN 0x0092
  63. #define PIPE2TRE 0x0094
  64. #define PIPE2TRN 0x0096
  65. #define PIPE3TRE 0x0098
  66. #define PIPE3TRN 0x009A
  67. #define PIPE4TRE 0x009C
  68. #define PIPE4TRN 0x009E
  69. #define PIPE5TRE 0x00A0
  70. #define PIPE5TRN 0x00A2
  71. #define PIPEBTRE 0x00A4
  72. #define PIPEBTRN 0x00A6
  73. #define PIPECTRE 0x00A8
  74. #define PIPECTRN 0x00AA
  75. #define PIPEDTRE 0x00AC
  76. #define PIPEDTRN 0x00AE
  77. #define PIPEETRE 0x00B0
  78. #define PIPEETRN 0x00B2
  79. #define PIPEFTRE 0x00B4
  80. #define PIPEFTRN 0x00B6
  81. #define PIPE9TRE 0x00B8
  82. #define PIPE9TRN 0x00BA
  83. #define PIPEATRE 0x00BC
  84. #define PIPEATRN 0x00BE
  85. #define DEVADD0 0x00D0 /* Device address n configuration */
  86. #define DEVADD1 0x00D2
  87. #define DEVADD2 0x00D4
  88. #define DEVADD3 0x00D6
  89. #define DEVADD4 0x00D8
  90. #define DEVADD5 0x00DA
  91. #define DEVADD6 0x00DC
  92. #define DEVADD7 0x00DE
  93. #define DEVADD8 0x00E0
  94. #define DEVADD9 0x00E2
  95. #define DEVADDA 0x00E4
  96. #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
  97. #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
  98. #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
  99. #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
  100. #define SUSPMODE 0x0102 /* for RZ/A */
  101. /* SYSCFG */
  102. #define SCKE (1 << 10) /* USB Module Clock Enable */
  103. #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
  104. #define HSE (1 << 7) /* High-Speed Operation Enable */
  105. #define DCFM (1 << 6) /* Controller Function Select */
  106. #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
  107. #define DPRPU (1 << 4) /* D+ Line Resistance Control */
  108. #define USBE (1 << 0) /* USB Module Operation Enable */
  109. #define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */
  110. #define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */
  111. /* DVSTCTR */
  112. #define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
  113. #define PWEN (1 << 9) /* Controls the PWEN pin output state */
  114. #define USBRST (1 << 6) /* Bus Reset Output */
  115. #define UACT (1 << 4) /* USB Bus Enable */
  116. #define RHST (0x7) /* Reset Handshake */
  117. #define RHST_LOW_SPEED 1 /* Low-speed connection */
  118. #define RHST_FULL_SPEED 2 /* Full-speed connection */
  119. #define RHST_HIGH_SPEED 3 /* High-speed connection */
  120. /* CFIFOSEL */
  121. #define DREQE (1 << 12) /* DMA Transfer Request Enable */
  122. #define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
  123. /* CFIFOCTR */
  124. #define BVAL (1 << 15) /* Buffer Memory Enable Flag */
  125. #define BCLR (1 << 14) /* CPU buffer clear */
  126. #define FRDY (1 << 13) /* FIFO Port Ready */
  127. #define DTLN_MASK (0x0FFF) /* Receive Data Length */
  128. /* INTENB0 */
  129. #define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
  130. #define RSME (1 << 14) /* Enable IRQ Resume */
  131. #define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
  132. #define DVSE (1 << 12) /* Enable IRQ Device State Transition */
  133. #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
  134. #define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
  135. #define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
  136. #define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
  137. /* INTENB1 */
  138. #define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
  139. #define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
  140. #define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
  141. #define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
  142. #define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
  143. #define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
  144. /* INTSTS0 */
  145. #define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
  146. #define DVST (1 << 12) /* Device State Transition Interrupt Status */
  147. #define CTRT (1 << 11) /* Control Stage Interrupt Status */
  148. #define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
  149. #define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
  150. #define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
  151. #define VALID (1 << 3) /* USB Request Receive */
  152. #define DVSQ_MASK (0x7 << 4) /* Device State */
  153. #define POWER_STATE (0 << 4)
  154. #define DEFAULT_STATE (1 << 4)
  155. #define ADDRESS_STATE (2 << 4)
  156. #define CONFIGURATION_STATE (3 << 4)
  157. #define SUSPENDED_STATE (4 << 4)
  158. #define CTSQ_MASK (0x7) /* Control Transfer Stage */
  159. #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
  160. #define READ_DATA_STAGE 1 /* Control read data stage */
  161. #define READ_STATUS_STAGE 2 /* Control read status stage */
  162. #define WRITE_DATA_STAGE 3 /* Control write data stage */
  163. #define WRITE_STATUS_STAGE 4 /* Control write status stage */
  164. #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
  165. #define SEQUENCE_ERROR 6 /* Control transfer sequence error */
  166. /* INTSTS1 */
  167. #define OVRCR (1 << 15) /* OVRCR Interrupt Status */
  168. #define BCHG (1 << 14) /* USB Bus Change Interrupt Status */
  169. #define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */
  170. #define ATTCH (1 << 11) /* ATTCH Interrupt Status */
  171. #define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */
  172. #define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */
  173. #define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */
  174. /* PIPECFG */
  175. /* DCPCFG */
  176. #define TYPE_NONE (0 << 14) /* Transfer Type */
  177. #define TYPE_BULK (1 << 14)
  178. #define TYPE_INT (2 << 14)
  179. #define TYPE_ISO (3 << 14)
  180. #define BFRE (1 << 10) /* BRDY Interrupt Operation Spec. */
  181. #define DBLB (1 << 9) /* Double Buffer Mode */
  182. #define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
  183. #define DIR_OUT (1 << 4) /* Transfer Direction */
  184. /* PIPEMAXP */
  185. /* DCPMAXP */
  186. #define DEVSEL_MASK (0xF << 12) /* Device Select */
  187. #define DCP_MAXP_MASK (0x7F)
  188. #define PIPE_MAXP_MASK (0x7FF)
  189. /* PIPEBUF */
  190. #define BUFSIZE_SHIFT 10
  191. #define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
  192. #define BUFNMB_MASK (0xFF)
  193. /* PIPEnCTR */
  194. /* DCPCTR */
  195. #define BSTS (1 << 15) /* Buffer Status */
  196. #define SUREQ (1 << 14) /* Sending SETUP Token */
  197. #define INBUFM (1 << 14) /* (PIPEnCTR) Transfer Buffer Monitor */
  198. #define CSSTS (1 << 12) /* CSSTS Status */
  199. #define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
  200. #define SQCLR (1 << 8) /* Toggle Bit Clear */
  201. #define SQSET (1 << 7) /* Toggle Bit Set */
  202. #define SQMON (1 << 6) /* Toggle Bit Check */
  203. #define PBUSY (1 << 5) /* Pipe Busy */
  204. #define PID_MASK (0x3) /* Response PID */
  205. #define PID_NAK 0
  206. #define PID_BUF 1
  207. #define PID_STALL10 2
  208. #define PID_STALL11 3
  209. #define CCPL (1 << 2) /* Control Transfer End Enable */
  210. /* PIPEnTRE */
  211. #define TRENB (1 << 9) /* Transaction Counter Enable */
  212. #define TRCLR (1 << 8) /* Transaction Counter Clear */
  213. /* FRMNUM */
  214. #define FRNM_MASK (0x7FF)
  215. /* DEVADDn */
  216. #define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */
  217. #define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */
  218. #define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */
  219. #define USBSPD_SPEED_LOW 0x1
  220. #define USBSPD_SPEED_FULL 0x2
  221. #define USBSPD_SPEED_HIGH 0x3
  222. /* SUSPMODE */
  223. #define SUSPM (1 << 14) /* SuspendM Control */
  224. /*
  225. * struct
  226. */
  227. struct usbhs_priv {
  228. void __iomem *base;
  229. unsigned int irq;
  230. const struct renesas_usbhs_platform_callback *pfunc;
  231. struct renesas_usbhs_driver_param dparam;
  232. struct delayed_work notify_hotplug_work;
  233. struct platform_device *pdev;
  234. struct extcon_dev *edev;
  235. spinlock_t lock;
  236. /*
  237. * module control
  238. */
  239. struct usbhs_mod_info mod_info;
  240. /*
  241. * pipe control
  242. */
  243. struct usbhs_pipe_info pipe_info;
  244. /*
  245. * fifo control
  246. */
  247. struct usbhs_fifo_info fifo_info;
  248. struct phy *phy;
  249. struct reset_control *rsts;
  250. struct clk *clks[2];
  251. };
  252. /*
  253. * common
  254. */
  255. u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
  256. void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
  257. void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
  258. #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
  259. #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
  260. int usbhs_get_id_as_gadget(struct platform_device *pdev);
  261. /*
  262. * sysconfig
  263. */
  264. void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
  265. void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
  266. void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
  267. void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
  268. /*
  269. * usb request
  270. */
  271. void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
  272. void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
  273. /*
  274. * bus
  275. */
  276. void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
  277. void usbhs_bus_send_reset(struct usbhs_priv *priv);
  278. int usbhs_bus_get_speed(struct usbhs_priv *priv);
  279. int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
  280. int usbhsc_schedule_notify_hotplug(struct platform_device *pdev);
  281. /*
  282. * frame
  283. */
  284. int usbhs_frame_get_num(struct usbhs_priv *priv);
  285. /*
  286. * device config
  287. */
  288. int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
  289. u16 hubport, u16 speed);
  290. /*
  291. * interrupt functions
  292. */
  293. void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
  294. /*
  295. * data
  296. */
  297. struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
  298. #define usbhs_get_dparam(priv, param) (priv->dparam.param)
  299. #define usbhs_priv_to_pdev(priv) (priv->pdev)
  300. #define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
  301. #define usbhs_priv_to_lock(priv) (&priv->lock)
  302. #endif /* RENESAS_USB_DRIVER_H */