spmi-pmic-arb.c 54 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/bitmap.h>
  5. #include <linux/debugfs.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/irqchip/chained_irq.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include <linux/spmi.h>
  20. #include <linux/string.h>
  21. #include <linux/soc/qcom/spmi-pmic-arb.h>
  22. /* PMIC Arbiter configuration registers */
  23. #define PMIC_ARB_VERSION 0x0000
  24. #define PMIC_ARB_VERSION_V2_MIN 0x20010000
  25. #define PMIC_ARB_VERSION_V3_MIN 0x30000000
  26. #define PMIC_ARB_VERSION_V5_MIN 0x50000000
  27. #define PMIC_ARB_VERSION_V7_MIN 0x70000000
  28. #define PMIC_ARB_INT_EN 0x0004
  29. #define PMIC_ARB_FEATURES 0x0004
  30. #define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
  31. #define PMIC_ARB_FEATURES1 0x0008
  32. /* PMIC Arbiter channel registers offsets */
  33. #define PMIC_ARB_CMD 0x00
  34. #define PMIC_ARB_CONFIG 0x04
  35. #define PMIC_ARB_STATUS 0x08
  36. #define PMIC_ARB_WDATA0 0x10
  37. #define PMIC_ARB_WDATA1 0x14
  38. #define PMIC_ARB_RDATA0 0x18
  39. #define PMIC_ARB_RDATA1 0x1C
  40. /* Mapping Table */
  41. #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
  42. #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
  43. #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
  44. #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  45. #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
  46. #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  47. #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
  48. #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
  49. #define PMIC_ARB_APID_VALID BIT(15)
  50. #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
  51. #define INVALID_EE 0xFF
  52. /* Ownership Table */
  53. #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
  54. /* Channel Status fields */
  55. enum pmic_arb_chnl_status {
  56. PMIC_ARB_STATUS_DONE = BIT(0),
  57. PMIC_ARB_STATUS_FAILURE = BIT(1),
  58. PMIC_ARB_STATUS_DENIED = BIT(2),
  59. PMIC_ARB_STATUS_DROPPED = BIT(3),
  60. };
  61. /* Command register fields */
  62. #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
  63. /* Command Opcodes */
  64. enum pmic_arb_cmd_op_code {
  65. PMIC_ARB_OP_EXT_WRITEL = 0,
  66. PMIC_ARB_OP_EXT_READL = 1,
  67. PMIC_ARB_OP_EXT_WRITE = 2,
  68. PMIC_ARB_OP_RESET = 3,
  69. PMIC_ARB_OP_SLEEP = 4,
  70. PMIC_ARB_OP_SHUTDOWN = 5,
  71. PMIC_ARB_OP_WAKEUP = 6,
  72. PMIC_ARB_OP_AUTHENTICATE = 7,
  73. PMIC_ARB_OP_MSTR_READ = 8,
  74. PMIC_ARB_OP_MSTR_WRITE = 9,
  75. PMIC_ARB_OP_EXT_READ = 13,
  76. PMIC_ARB_OP_WRITE = 14,
  77. PMIC_ARB_OP_READ = 15,
  78. PMIC_ARB_OP_ZERO_WRITE = 16,
  79. };
  80. /*
  81. * PMIC arbiter version 5 uses different register offsets for read/write vs
  82. * observer channels.
  83. */
  84. enum pmic_arb_channel {
  85. PMIC_ARB_CHANNEL_RW,
  86. PMIC_ARB_CHANNEL_OBS,
  87. };
  88. /* Maximum number of support PMIC peripherals */
  89. #define PMIC_ARB_MAX_PERIPHS 512
  90. #define PMIC_ARB_MAX_PERIPHS_V7 1024
  91. #define PMIC_ARB_TIMEOUT_US 1000
  92. #define PMIC_ARB_MAX_TRANS_BYTES (8)
  93. #define PMIC_ARB_APID_MASK 0xFF
  94. #define PMIC_ARB_PPID_MASK 0xFFF
  95. /* interrupt enable bit */
  96. #define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
  97. #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
  98. ((((slave_id) & 0xF) << 28) | \
  99. (((periph_id) & 0xFF) << 20) | \
  100. (((irq_id) & 0x7) << 16) | \
  101. (((apid) & 0x3FF) << 0))
  102. #define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
  103. #define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
  104. #define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
  105. #define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
  106. struct pmic_arb_ver_ops;
  107. struct apid_data {
  108. u16 ppid;
  109. u8 write_ee;
  110. u8 irq_ee;
  111. };
  112. /**
  113. * spmi_pmic_arb - SPMI PMIC Arbiter object
  114. *
  115. * @rd_base: on v1 "core", on v2 "observer" register base off DT.
  116. * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
  117. * @wr_base_phys: Base physical address of the register range used for
  118. * SPMI write commands.
  119. * @intr: address of the SPMI interrupt control registers.
  120. * @cnfg: address of the PMIC Arbiter configuration registers.
  121. * @lock: lock to synchronize accesses.
  122. * @channel: execution environment channel to use for accesses.
  123. * @irq: PMIC ARB interrupt.
  124. * @ee: the current Execution Environment
  125. * @bus_instance: on v7: 0 = primary SPMI bus, 1 = secondary SPMI bus
  126. * @min_apid: minimum APID (used for bounding IRQ search)
  127. * @max_apid: maximum APID
  128. * @base_apid: on v7: minimum APID associated with the particular SPMI
  129. * bus instance
  130. * @apid_count: on v5 and v7: number of APIDs associated with the
  131. * particular SPMI bus instance
  132. * @mapping_table: in-memory copy of PPID -> APID mapping table.
  133. * @domain: irq domain object for PMIC IRQ domain
  134. * @spmic: SPMI controller object
  135. * @ver_ops: version dependent operations.
  136. * @ppid_to_apid: in-memory copy of PPID -> APID mapping table.
  137. * @last_apid: Highest value APID in use
  138. * @apid_data: Table of data for all APIDs
  139. * @max_periphs: Number of elements in apid_data[]
  140. * @debugfs: debugfs directory pointer
  141. * @debug_spmi_addr: SPMI address used for debugfs operations
  142. */
  143. struct spmi_pmic_arb {
  144. void __iomem *rd_base;
  145. void __iomem *wr_base;
  146. phys_addr_t wr_base_phys;
  147. void __iomem *intr;
  148. void __iomem *cnfg;
  149. void __iomem *core;
  150. resource_size_t core_size;
  151. raw_spinlock_t lock;
  152. u8 channel;
  153. int irq;
  154. u8 ee;
  155. u32 bus_instance;
  156. u16 min_apid;
  157. u16 max_apid;
  158. u16 base_apid;
  159. int apid_count;
  160. u32 *mapping_table;
  161. DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
  162. struct irq_domain *domain;
  163. struct spmi_controller *spmic;
  164. const struct pmic_arb_ver_ops *ver_ops;
  165. u16 *ppid_to_apid;
  166. u16 last_apid;
  167. struct apid_data *apid_data;
  168. int max_periphs;
  169. struct dentry *debugfs;
  170. u32 debug_spmi_addr;
  171. };
  172. /**
  173. * pmic_arb_ver: version dependent functionality.
  174. *
  175. * @ver_str: version string.
  176. * @ppid_to_apid: finds the apid for a given ppid.
  177. * @non_data_cmd: on v1 issues an spmi non-data command.
  178. * on v2 no HW support, returns -EOPNOTSUPP.
  179. * @offset: on v1 offset of per-ee channel.
  180. * on v2 offset of per-ee and per-ppid channel.
  181. * @fmt_cmd: formats a GENI/SPMI command.
  182. * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
  183. * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
  184. * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
  185. * on v2 address of SPMI_PIC_ACC_ENABLEn.
  186. * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
  187. * on v2 address of SPMI_PIC_IRQ_STATUSn.
  188. * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
  189. * on v2 address of SPMI_PIC_IRQ_CLEARn.
  190. * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
  191. * @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG
  192. * @wr_addr_map: maps from an SPMI address to the physical address
  193. * range of the registers used to perform an SPMI write
  194. * command to the SPMI address.
  195. */
  196. struct pmic_arb_ver_ops {
  197. const char *ver_str;
  198. int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
  199. /* spmi commands (read_cmd, write_cmd, cmd) functionality */
  200. int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  201. enum pmic_arb_channel ch_type);
  202. u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
  203. int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
  204. /* Interrupts controller functionality (offset of PIC registers) */
  205. void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
  206. u16 n);
  207. void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
  208. void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
  209. void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
  210. u32 (*apid_map_offset)(u16 n);
  211. void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n);
  212. int (*wr_addr_map)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  213. struct resource *res_out);
  214. };
  215. static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
  216. u32 offset, u32 val)
  217. {
  218. writel_relaxed(val, pmic_arb->wr_base + offset);
  219. }
  220. static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
  221. u32 offset, u32 val)
  222. {
  223. writel_relaxed(val, pmic_arb->rd_base + offset);
  224. }
  225. /**
  226. * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
  227. * @bc: byte count -1. range: 0..3
  228. * @reg: register's address
  229. * @buf: output parameter, length must be bc + 1
  230. */
  231. static void
  232. pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
  233. {
  234. u32 data = __raw_readl(pmic_arb->rd_base + reg);
  235. memcpy(buf, &data, (bc & 3) + 1);
  236. }
  237. /**
  238. * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
  239. * @bc: byte-count -1. range: 0..3.
  240. * @reg: register's address.
  241. * @buf: buffer to write. length must be bc + 1.
  242. */
  243. static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
  244. u32 reg, u8 bc)
  245. {
  246. u32 data = 0;
  247. memcpy(&data, buf, (bc & 3) + 1);
  248. __raw_writel(data, pmic_arb->wr_base + reg);
  249. }
  250. static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
  251. void __iomem *base, u8 sid, u16 addr,
  252. enum pmic_arb_channel ch_type)
  253. {
  254. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  255. u32 status = 0;
  256. u32 timeout = PMIC_ARB_TIMEOUT_US;
  257. u32 offset;
  258. int rc;
  259. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
  260. if (rc < 0)
  261. return rc;
  262. offset = rc;
  263. offset += PMIC_ARB_STATUS;
  264. while (timeout--) {
  265. status = readl_relaxed(base + offset);
  266. if (status & PMIC_ARB_STATUS_DONE) {
  267. if (status & PMIC_ARB_STATUS_DENIED) {
  268. dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n",
  269. __func__, sid, addr, status);
  270. return -EPERM;
  271. }
  272. if (status & PMIC_ARB_STATUS_FAILURE) {
  273. dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n",
  274. __func__, sid, addr, status);
  275. WARN_ON(1);
  276. return -EIO;
  277. }
  278. if (status & PMIC_ARB_STATUS_DROPPED) {
  279. dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n",
  280. __func__, sid, addr, status);
  281. return -EIO;
  282. }
  283. return 0;
  284. }
  285. udelay(1);
  286. }
  287. dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n",
  288. __func__, sid, addr, status);
  289. return -ETIMEDOUT;
  290. }
  291. static int
  292. pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
  293. {
  294. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  295. unsigned long flags;
  296. u32 cmd;
  297. int rc;
  298. u32 offset;
  299. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
  300. if (rc < 0)
  301. return rc;
  302. offset = rc;
  303. cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
  304. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  305. pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  306. rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
  307. PMIC_ARB_CHANNEL_RW);
  308. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  309. return rc;
  310. }
  311. static int
  312. pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
  313. {
  314. return -EOPNOTSUPP;
  315. }
  316. /* Non-data command */
  317. static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
  318. {
  319. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  320. dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
  321. /* Check for valid non-data command */
  322. if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
  323. return -EINVAL;
  324. return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
  325. }
  326. static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
  327. u16 addr, size_t len, u32 *cmd, u32 *offset)
  328. {
  329. u8 bc = len - 1;
  330. int rc;
  331. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
  332. PMIC_ARB_CHANNEL_OBS);
  333. if (rc < 0)
  334. return rc;
  335. *offset = rc;
  336. if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
  337. dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
  338. PMIC_ARB_MAX_TRANS_BYTES, len);
  339. return -EINVAL;
  340. }
  341. /* Check the opcode */
  342. if (opc >= 0x60 && opc <= 0x7F)
  343. opc = PMIC_ARB_OP_READ;
  344. else if (opc >= 0x20 && opc <= 0x2F)
  345. opc = PMIC_ARB_OP_EXT_READ;
  346. else if (opc >= 0x38 && opc <= 0x3F)
  347. opc = PMIC_ARB_OP_EXT_READL;
  348. else
  349. return -EINVAL;
  350. *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
  351. return 0;
  352. }
  353. static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
  354. u32 offset, u8 sid, u16 addr, u8 *buf,
  355. size_t len)
  356. {
  357. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  358. u8 bc = len - 1;
  359. int rc;
  360. pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  361. rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
  362. PMIC_ARB_CHANNEL_OBS);
  363. if (rc)
  364. return rc;
  365. pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
  366. min_t(u8, bc, 3));
  367. if (bc > 3)
  368. pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
  369. bc - 4);
  370. return 0;
  371. }
  372. static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  373. u16 addr, u8 *buf, size_t len)
  374. {
  375. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  376. unsigned long flags;
  377. u32 cmd, offset;
  378. int rc;
  379. rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
  380. &offset);
  381. if (rc)
  382. return rc;
  383. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  384. rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len);
  385. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  386. return rc;
  387. }
  388. static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
  389. u8 sid, u16 addr, size_t len, u32 *cmd,
  390. u32 *offset)
  391. {
  392. u8 bc = len - 1;
  393. int rc;
  394. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
  395. PMIC_ARB_CHANNEL_RW);
  396. if (rc < 0)
  397. return rc;
  398. *offset = rc;
  399. if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
  400. dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
  401. PMIC_ARB_MAX_TRANS_BYTES, len);
  402. return -EINVAL;
  403. }
  404. /* Check the opcode */
  405. if (opc >= 0x40 && opc <= 0x5F)
  406. opc = PMIC_ARB_OP_WRITE;
  407. else if (opc <= 0x0F)
  408. opc = PMIC_ARB_OP_EXT_WRITE;
  409. else if (opc >= 0x30 && opc <= 0x37)
  410. opc = PMIC_ARB_OP_EXT_WRITEL;
  411. else if (opc >= 0x80)
  412. opc = PMIC_ARB_OP_ZERO_WRITE;
  413. else
  414. return -EINVAL;
  415. *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
  416. return 0;
  417. }
  418. static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
  419. u32 offset, u8 sid, u16 addr,
  420. const u8 *buf, size_t len)
  421. {
  422. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  423. u8 bc = len - 1;
  424. /* Write data to FIFOs */
  425. pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
  426. min_t(u8, bc, 3));
  427. if (bc > 3)
  428. pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
  429. bc - 4);
  430. /* Start the transaction */
  431. pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  432. return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
  433. PMIC_ARB_CHANNEL_RW);
  434. }
  435. static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  436. u16 addr, const u8 *buf, size_t len)
  437. {
  438. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  439. unsigned long flags;
  440. u32 cmd, offset;
  441. int rc;
  442. rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
  443. &offset);
  444. if (rc)
  445. return rc;
  446. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  447. rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf,
  448. len);
  449. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  450. return rc;
  451. }
  452. static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,
  453. const u8 *buf, const u8 *mask, size_t len)
  454. {
  455. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  456. u32 read_cmd, read_offset, write_cmd, write_offset;
  457. u8 temp[PMIC_ARB_MAX_TRANS_BYTES];
  458. unsigned long flags;
  459. int rc, i;
  460. rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
  461. &read_cmd, &read_offset);
  462. if (rc)
  463. return rc;
  464. rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
  465. len, &write_cmd, &write_offset);
  466. if (rc)
  467. return rc;
  468. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  469. rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr,
  470. temp, len);
  471. if (rc)
  472. goto done;
  473. for (i = 0; i < len; i++)
  474. temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]);
  475. rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid,
  476. addr, temp, len);
  477. done:
  478. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  479. return rc;
  480. }
  481. enum qpnpint_regs {
  482. QPNPINT_REG_RT_STS = 0x10,
  483. QPNPINT_REG_SET_TYPE = 0x11,
  484. QPNPINT_REG_POLARITY_HIGH = 0x12,
  485. QPNPINT_REG_POLARITY_LOW = 0x13,
  486. QPNPINT_REG_LATCHED_CLR = 0x14,
  487. QPNPINT_REG_EN_SET = 0x15,
  488. QPNPINT_REG_EN_CLR = 0x16,
  489. QPNPINT_REG_LATCHED_STS = 0x18,
  490. };
  491. struct spmi_pmic_arb_qpnpint_type {
  492. u8 type; /* 1 -> edge */
  493. u8 polarity_high;
  494. u8 polarity_low;
  495. } __packed;
  496. /* Simplified accessor functions for irqchip callbacks */
  497. static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
  498. size_t len)
  499. {
  500. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  501. u8 sid = hwirq_to_sid(d->hwirq);
  502. u8 per = hwirq_to_per(d->hwirq);
  503. if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
  504. (per << 8) + reg, buf, len))
  505. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
  506. d->irq);
  507. }
  508. static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
  509. {
  510. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  511. u8 sid = hwirq_to_sid(d->hwirq);
  512. u8 per = hwirq_to_per(d->hwirq);
  513. if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
  514. (per << 8) + reg, buf, len))
  515. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
  516. d->irq);
  517. }
  518. static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,
  519. const void *buf, const void *mask,
  520. size_t len)
  521. {
  522. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  523. u8 sid = hwirq_to_sid(d->hwirq);
  524. u8 per = hwirq_to_per(d->hwirq);
  525. int rc;
  526. rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
  527. mask, len);
  528. if (rc)
  529. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
  530. d->irq, rc);
  531. return rc;
  532. }
  533. static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
  534. {
  535. u16 ppid = pmic_arb->apid_data[apid].ppid;
  536. u8 sid = ppid >> 8;
  537. u8 per = ppid & 0xFF;
  538. u8 irq_mask = BIT(id);
  539. dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
  540. __func__, apid, sid, per, id);
  541. writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
  542. }
  543. static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
  544. {
  545. unsigned int irq;
  546. u32 status, id;
  547. int handled = 0;
  548. u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
  549. u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
  550. status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
  551. while (status) {
  552. id = ffs(status) - 1;
  553. status &= ~BIT(id);
  554. irq = irq_find_mapping(pmic_arb->domain,
  555. spec_to_hwirq(sid, per, id, apid));
  556. if (irq == 0) {
  557. cleanup_irq(pmic_arb, apid, id);
  558. continue;
  559. }
  560. generic_handle_irq(irq);
  561. handled++;
  562. }
  563. return handled;
  564. }
  565. static void pmic_arb_chained_irq(struct irq_desc *desc)
  566. {
  567. struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
  568. const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
  569. struct irq_chip *chip = irq_desc_get_chip(desc);
  570. int first = pmic_arb->min_apid;
  571. int last = pmic_arb->max_apid;
  572. /*
  573. * acc_offset will be non-zero for the secondary SPMI bus instance on
  574. * v7 controllers.
  575. */
  576. int acc_offset = pmic_arb->base_apid >> 5;
  577. u8 ee = pmic_arb->ee;
  578. u32 status, enable, handled = 0;
  579. int i, id, apid;
  580. /* status based dispatch */
  581. bool acc_valid = false;
  582. u32 irq_status = 0;
  583. chained_irq_enter(chip, desc);
  584. for (i = first >> 5; i <= last >> 5; ++i) {
  585. status = readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee,
  586. i - acc_offset));
  587. if (status)
  588. acc_valid = true;
  589. while (status) {
  590. id = ffs(status) - 1;
  591. status &= ~BIT(id);
  592. apid = id + i * 32;
  593. if (apid < first || apid > last) {
  594. WARN_ONCE(true, "spurious spmi irq received for apid=%d\n",
  595. apid);
  596. continue;
  597. }
  598. enable = readl_relaxed(
  599. ver_ops->acc_enable(pmic_arb, apid));
  600. if (enable & SPMI_PIC_ACC_ENABLE_BIT)
  601. if (periph_interrupt(pmic_arb, apid) != 0)
  602. handled++;
  603. }
  604. }
  605. /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */
  606. if (!acc_valid) {
  607. for (i = first; i <= last; i++) {
  608. /* skip if APPS is not irq owner */
  609. if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee)
  610. continue;
  611. irq_status = readl_relaxed(
  612. ver_ops->irq_status(pmic_arb, i));
  613. if (irq_status) {
  614. enable = readl_relaxed(
  615. ver_ops->acc_enable(pmic_arb, i));
  616. if (enable & SPMI_PIC_ACC_ENABLE_BIT) {
  617. dev_dbg(&pmic_arb->spmic->dev,
  618. "Dispatching IRQ for apid=%d status=%x\n",
  619. i, irq_status);
  620. if (periph_interrupt(pmic_arb, i) != 0)
  621. handled++;
  622. }
  623. }
  624. }
  625. }
  626. if (handled == 0)
  627. handle_bad_irq(desc);
  628. chained_irq_exit(chip, desc);
  629. }
  630. static void qpnpint_irq_ack(struct irq_data *d)
  631. {
  632. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  633. u8 irq = hwirq_to_irq(d->hwirq);
  634. u16 apid = hwirq_to_apid(d->hwirq);
  635. u8 data;
  636. writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
  637. data = BIT(irq);
  638. qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
  639. }
  640. static void qpnpint_irq_mask(struct irq_data *d)
  641. {
  642. u8 irq = hwirq_to_irq(d->hwirq);
  643. u8 data = BIT(irq);
  644. qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
  645. }
  646. static void qpnpint_irq_unmask(struct irq_data *d)
  647. {
  648. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  649. const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
  650. u8 irq = hwirq_to_irq(d->hwirq);
  651. u16 apid = hwirq_to_apid(d->hwirq);
  652. u8 buf[2];
  653. writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
  654. ver_ops->acc_enable(pmic_arb, apid));
  655. qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
  656. if (!(buf[0] & BIT(irq))) {
  657. /*
  658. * Since the interrupt is currently disabled, write to both the
  659. * LATCHED_CLR and EN_SET registers so that a spurious interrupt
  660. * cannot be triggered when the interrupt is enabled
  661. */
  662. buf[0] = BIT(irq);
  663. buf[1] = BIT(irq);
  664. qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
  665. }
  666. }
  667. static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
  668. {
  669. struct spmi_pmic_arb_qpnpint_type type = {0};
  670. struct spmi_pmic_arb_qpnpint_type mask;
  671. irq_flow_handler_t flow_handler;
  672. u8 irq_bit = BIT(hwirq_to_irq(d->hwirq));
  673. int rc;
  674. if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
  675. type.type = irq_bit;
  676. if (flow_type & IRQF_TRIGGER_RISING)
  677. type.polarity_high = irq_bit;
  678. if (flow_type & IRQF_TRIGGER_FALLING)
  679. type.polarity_low = irq_bit;
  680. flow_handler = handle_edge_irq;
  681. } else {
  682. if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
  683. (flow_type & (IRQF_TRIGGER_LOW)))
  684. return -EINVAL;
  685. if (flow_type & IRQF_TRIGGER_HIGH)
  686. type.polarity_high = irq_bit;
  687. else
  688. type.polarity_low = irq_bit;
  689. flow_handler = handle_level_irq;
  690. }
  691. mask.type = irq_bit;
  692. mask.polarity_high = irq_bit;
  693. mask.polarity_low = irq_bit;
  694. rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask,
  695. sizeof(type));
  696. irq_set_handler_locked(d, flow_handler);
  697. return rc;
  698. }
  699. static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
  700. {
  701. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  702. return irq_set_irq_wake(pmic_arb->irq, on);
  703. }
  704. static int qpnpint_get_irqchip_state(struct irq_data *d,
  705. enum irqchip_irq_state which,
  706. bool *state)
  707. {
  708. u8 irq = hwirq_to_irq(d->hwirq);
  709. u8 status = 0;
  710. if (which != IRQCHIP_STATE_LINE_LEVEL)
  711. return -EINVAL;
  712. qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
  713. *state = !!(status & BIT(irq));
  714. return 0;
  715. }
  716. static int qpnpint_irq_domain_activate(struct irq_domain *domain,
  717. struct irq_data *d, bool reserve)
  718. {
  719. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  720. u16 periph = hwirq_to_per(d->hwirq);
  721. u16 apid = hwirq_to_apid(d->hwirq);
  722. u16 sid = hwirq_to_sid(d->hwirq);
  723. u16 irq = hwirq_to_irq(d->hwirq);
  724. u8 buf;
  725. if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
  726. dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
  727. sid, periph, irq, pmic_arb->ee,
  728. pmic_arb->apid_data[apid].irq_ee);
  729. return -ENODEV;
  730. }
  731. buf = BIT(irq);
  732. qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
  733. qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
  734. return 0;
  735. }
  736. static struct irq_chip pmic_arb_irqchip = {
  737. .name = "pmic_arb",
  738. .irq_ack = qpnpint_irq_ack,
  739. .irq_mask = qpnpint_irq_mask,
  740. .irq_unmask = qpnpint_irq_unmask,
  741. .irq_set_type = qpnpint_irq_set_type,
  742. .irq_set_wake = qpnpint_irq_set_wake,
  743. .irq_get_irqchip_state = qpnpint_get_irqchip_state,
  744. .flags = IRQCHIP_MASK_ON_SUSPEND,
  745. };
  746. static int qpnpint_irq_domain_translate(struct irq_domain *d,
  747. struct irq_fwspec *fwspec,
  748. unsigned long *out_hwirq,
  749. unsigned int *out_type)
  750. {
  751. struct spmi_pmic_arb *pmic_arb = d->host_data;
  752. u32 *intspec = fwspec->param;
  753. u16 apid, ppid;
  754. int rc;
  755. dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
  756. intspec[0], intspec[1], intspec[2]);
  757. if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
  758. return -EINVAL;
  759. if (fwspec->param_count != 4)
  760. return -EINVAL;
  761. if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
  762. return -EINVAL;
  763. ppid = intspec[0] << 8 | intspec[1];
  764. rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
  765. if (rc < 0) {
  766. dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
  767. intspec[0], intspec[1], intspec[2], rc);
  768. return rc;
  769. }
  770. apid = rc;
  771. /* Keep track of {max,min}_apid for bounding search during interrupt */
  772. if (apid > pmic_arb->max_apid)
  773. pmic_arb->max_apid = apid;
  774. if (apid < pmic_arb->min_apid)
  775. pmic_arb->min_apid = apid;
  776. *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
  777. *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
  778. dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
  779. return 0;
  780. }
  781. static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
  782. static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
  783. struct irq_domain *domain, unsigned int virq,
  784. irq_hw_number_t hwirq, unsigned int type)
  785. {
  786. irq_flow_handler_t handler;
  787. dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
  788. virq, hwirq, type);
  789. if (type & IRQ_TYPE_EDGE_BOTH)
  790. handler = handle_edge_irq;
  791. else
  792. handler = handle_level_irq;
  793. irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
  794. &qpnpint_irq_request_class);
  795. irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
  796. handler, NULL, NULL);
  797. }
  798. static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
  799. unsigned int virq, unsigned int nr_irqs,
  800. void *data)
  801. {
  802. struct spmi_pmic_arb *pmic_arb = domain->host_data;
  803. struct irq_fwspec *fwspec = data;
  804. irq_hw_number_t hwirq;
  805. unsigned int type;
  806. int ret, i;
  807. ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
  808. if (ret)
  809. return ret;
  810. for (i = 0; i < nr_irqs; i++)
  811. qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
  812. type);
  813. return 0;
  814. }
  815. static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  816. {
  817. u32 *mapping_table = pmic_arb->mapping_table;
  818. int index = 0, i;
  819. u16 apid_valid;
  820. u16 apid;
  821. u32 data;
  822. apid_valid = pmic_arb->ppid_to_apid[ppid];
  823. if (apid_valid & PMIC_ARB_APID_VALID) {
  824. apid = apid_valid & ~PMIC_ARB_APID_VALID;
  825. return apid;
  826. }
  827. for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
  828. if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
  829. mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
  830. SPMI_MAPPING_TABLE_REG(index));
  831. data = mapping_table[index];
  832. if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
  833. if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
  834. index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
  835. } else {
  836. apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
  837. pmic_arb->ppid_to_apid[ppid]
  838. = apid | PMIC_ARB_APID_VALID;
  839. pmic_arb->apid_data[apid].ppid = ppid;
  840. return apid;
  841. }
  842. } else {
  843. if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
  844. index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
  845. } else {
  846. apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
  847. pmic_arb->ppid_to_apid[ppid]
  848. = apid | PMIC_ARB_APID_VALID;
  849. pmic_arb->apid_data[apid].ppid = ppid;
  850. return apid;
  851. }
  852. }
  853. }
  854. return -ENODEV;
  855. }
  856. /* v1 offset per ee */
  857. static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  858. enum pmic_arb_channel ch_type)
  859. {
  860. return 0x800 + 0x80 * pmic_arb->channel;
  861. }
  862. static int pmic_arb_wr_addr_map_v1(struct spmi_pmic_arb *pmic_arb, u8 sid,
  863. u16 addr, struct resource *res_out)
  864. {
  865. int rc;
  866. rc = pmic_arb_offset_v1(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
  867. if (rc < 0)
  868. return rc;
  869. res_out->start = pmic_arb->wr_base_phys + rc;
  870. res_out->end = res_out->start + 0x80 - 1;
  871. return 0;
  872. }
  873. static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  874. {
  875. struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
  876. u32 regval, offset;
  877. u16 id, apid;
  878. for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
  879. offset = pmic_arb->ver_ops->apid_map_offset(apid);
  880. if (offset >= pmic_arb->core_size)
  881. break;
  882. regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
  883. apid));
  884. apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
  885. apidd->write_ee = apidd->irq_ee;
  886. regval = readl_relaxed(pmic_arb->core + offset);
  887. if (!regval)
  888. continue;
  889. id = (regval >> 8) & PMIC_ARB_PPID_MASK;
  890. pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
  891. apidd->ppid = id;
  892. if (id == ppid) {
  893. apid |= PMIC_ARB_APID_VALID;
  894. break;
  895. }
  896. }
  897. pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
  898. return apid;
  899. }
  900. static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  901. {
  902. u16 apid_valid;
  903. apid_valid = pmic_arb->ppid_to_apid[ppid];
  904. if (!(apid_valid & PMIC_ARB_APID_VALID))
  905. apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
  906. if (!(apid_valid & PMIC_ARB_APID_VALID))
  907. return -ENODEV;
  908. return apid_valid & ~PMIC_ARB_APID_VALID;
  909. }
  910. static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
  911. {
  912. struct apid_data *apidd;
  913. struct apid_data *prev_apidd;
  914. u16 i, apid, ppid, apid_max;
  915. bool valid, is_irq_ee;
  916. u32 regval, offset;
  917. /*
  918. * In order to allow multiple EEs to write to a single PPID in arbiter
  919. * version 5 and 7, there is more than one APID mapped to each PPID.
  920. * The owner field for each of these mappings specifies the EE which is
  921. * allowed to write to the APID. The owner of the last (highest) APID
  922. * which has the IRQ owner bit set for a given PPID will receive
  923. * interrupts from the PPID.
  924. *
  925. * In arbiter version 7, the APID numbering space is divided between
  926. * the primary bus (0) and secondary bus (1) such that:
  927. * APID = 0 to N-1 are assigned to the primary bus
  928. * APID = N to N+M-1 are assigned to the secondary bus
  929. * where N = number of APIDs supported by the primary bus and
  930. * M = number of APIDs supported by the secondary bus
  931. */
  932. apidd = &pmic_arb->apid_data[pmic_arb->base_apid];
  933. apid_max = pmic_arb->base_apid + pmic_arb->apid_count;
  934. for (i = pmic_arb->base_apid; i < apid_max; i++, apidd++) {
  935. offset = pmic_arb->ver_ops->apid_map_offset(i);
  936. if (offset >= pmic_arb->core_size)
  937. break;
  938. regval = readl_relaxed(pmic_arb->core + offset);
  939. if (!regval)
  940. continue;
  941. ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
  942. is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
  943. regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
  944. i));
  945. apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
  946. apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
  947. valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
  948. apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
  949. prev_apidd = &pmic_arb->apid_data[apid];
  950. if (!valid || apidd->write_ee == pmic_arb->ee) {
  951. /* First PPID mapping or one for this EE */
  952. pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
  953. } else if (valid && is_irq_ee &&
  954. prev_apidd->write_ee == pmic_arb->ee) {
  955. /*
  956. * Duplicate PPID mapping after the one for this EE;
  957. * override the irq owner
  958. */
  959. prev_apidd->irq_ee = apidd->irq_ee;
  960. }
  961. apidd->ppid = ppid;
  962. pmic_arb->last_apid = i;
  963. }
  964. /* Dump the mapping table for debug purposes. */
  965. dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
  966. for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
  967. apid = pmic_arb->ppid_to_apid[ppid];
  968. if (apid & PMIC_ARB_APID_VALID) {
  969. apid &= ~PMIC_ARB_APID_VALID;
  970. apidd = &pmic_arb->apid_data[apid];
  971. dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
  972. ppid, apid, apidd->write_ee, apidd->irq_ee);
  973. }
  974. }
  975. return 0;
  976. }
  977. static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  978. {
  979. if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
  980. return -ENODEV;
  981. return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
  982. }
  983. /* v2 offset per ppid and per ee */
  984. static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  985. enum pmic_arb_channel ch_type)
  986. {
  987. u16 apid;
  988. u16 ppid;
  989. int rc;
  990. ppid = sid << 8 | ((addr >> 8) & 0xFF);
  991. rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
  992. if (rc < 0)
  993. return rc;
  994. apid = rc;
  995. return 0x1000 * pmic_arb->ee + 0x8000 * apid;
  996. }
  997. static int pmic_arb_wr_addr_map_v2(struct spmi_pmic_arb *pmic_arb, u8 sid,
  998. u16 addr, struct resource *res_out)
  999. {
  1000. int rc;
  1001. rc = pmic_arb_offset_v2(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
  1002. if (rc < 0)
  1003. return rc;
  1004. res_out->start = pmic_arb->wr_base_phys + rc;
  1005. res_out->end = res_out->start + 0x1000 - 1;
  1006. return 0;
  1007. }
  1008. /*
  1009. * v5 offset per ee and per apid for observer channels and per apid for
  1010. * read/write channels.
  1011. */
  1012. static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  1013. enum pmic_arb_channel ch_type)
  1014. {
  1015. u16 apid;
  1016. int rc;
  1017. u32 offset = 0;
  1018. u16 ppid = (sid << 8) | (addr >> 8);
  1019. rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
  1020. if (rc < 0)
  1021. return rc;
  1022. apid = rc;
  1023. switch (ch_type) {
  1024. case PMIC_ARB_CHANNEL_OBS:
  1025. offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
  1026. break;
  1027. case PMIC_ARB_CHANNEL_RW:
  1028. if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
  1029. dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
  1030. sid, addr);
  1031. return -EPERM;
  1032. }
  1033. offset = 0x10000 * apid;
  1034. break;
  1035. }
  1036. return offset;
  1037. }
  1038. static int pmic_arb_wr_addr_map_v5(struct spmi_pmic_arb *pmic_arb, u8 sid,
  1039. u16 addr, struct resource *res_out)
  1040. {
  1041. int rc;
  1042. rc = pmic_arb_offset_v5(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
  1043. if (rc < 0)
  1044. return rc;
  1045. res_out->start = pmic_arb->wr_base_phys + rc;
  1046. res_out->end = res_out->start + 0x10000 - 1;
  1047. return 0;
  1048. }
  1049. /*
  1050. * v7 offset per ee and per apid for observer channels and per apid for
  1051. * read/write channels.
  1052. */
  1053. static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  1054. enum pmic_arb_channel ch_type)
  1055. {
  1056. u16 apid;
  1057. int rc;
  1058. u32 offset = 0;
  1059. u16 ppid = (sid << 8) | (addr >> 8);
  1060. rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
  1061. if (rc < 0)
  1062. return rc;
  1063. apid = rc;
  1064. switch (ch_type) {
  1065. case PMIC_ARB_CHANNEL_OBS:
  1066. offset = 0x8000 * pmic_arb->ee + 0x20 * apid;
  1067. break;
  1068. case PMIC_ARB_CHANNEL_RW:
  1069. if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
  1070. dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
  1071. sid, addr);
  1072. return -EPERM;
  1073. }
  1074. offset = 0x1000 * apid;
  1075. break;
  1076. }
  1077. return offset;
  1078. }
  1079. static int pmic_arb_wr_addr_map_v7(struct spmi_pmic_arb *pmic_arb, u8 sid,
  1080. u16 addr, struct resource *res_out)
  1081. {
  1082. int rc;
  1083. rc = pmic_arb_offset_v7(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
  1084. if (rc < 0)
  1085. return rc;
  1086. res_out->start = pmic_arb->wr_base_phys + rc;
  1087. res_out->end = res_out->start + 0x1000 - 1;
  1088. return 0;
  1089. }
  1090. static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
  1091. {
  1092. return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
  1093. }
  1094. static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
  1095. {
  1096. return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
  1097. }
  1098. static void __iomem *
  1099. pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  1100. {
  1101. return pmic_arb->intr + 0x20 * m + 0x4 * n;
  1102. }
  1103. static void __iomem *
  1104. pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  1105. {
  1106. return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
  1107. }
  1108. static void __iomem *
  1109. pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  1110. {
  1111. return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
  1112. }
  1113. static void __iomem *
  1114. pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  1115. {
  1116. return pmic_arb->intr + 0x10000 * m + 0x4 * n;
  1117. }
  1118. static void __iomem *
  1119. pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  1120. {
  1121. return pmic_arb->intr + 0x1000 * m + 0x4 * n;
  1122. }
  1123. static void __iomem *
  1124. pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  1125. {
  1126. return pmic_arb->intr + 0x200 + 0x4 * n;
  1127. }
  1128. static void __iomem *
  1129. pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  1130. {
  1131. return pmic_arb->intr + 0x1000 * n;
  1132. }
  1133. static void __iomem *
  1134. pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  1135. {
  1136. return pmic_arb->wr_base + 0x100 + 0x10000 * n;
  1137. }
  1138. static void __iomem *
  1139. pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
  1140. {
  1141. return pmic_arb->wr_base + 0x100 + 0x1000 * n;
  1142. }
  1143. static void __iomem *
  1144. pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  1145. {
  1146. return pmic_arb->intr + 0x600 + 0x4 * n;
  1147. }
  1148. static void __iomem *
  1149. pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  1150. {
  1151. return pmic_arb->intr + 0x4 + 0x1000 * n;
  1152. }
  1153. static void __iomem *
  1154. pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  1155. {
  1156. return pmic_arb->wr_base + 0x104 + 0x10000 * n;
  1157. }
  1158. static void __iomem *
  1159. pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
  1160. {
  1161. return pmic_arb->wr_base + 0x104 + 0x1000 * n;
  1162. }
  1163. static void __iomem *
  1164. pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  1165. {
  1166. return pmic_arb->intr + 0xA00 + 0x4 * n;
  1167. }
  1168. static void __iomem *
  1169. pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  1170. {
  1171. return pmic_arb->intr + 0x8 + 0x1000 * n;
  1172. }
  1173. static void __iomem *
  1174. pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  1175. {
  1176. return pmic_arb->wr_base + 0x108 + 0x10000 * n;
  1177. }
  1178. static void __iomem *
  1179. pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
  1180. {
  1181. return pmic_arb->wr_base + 0x108 + 0x1000 * n;
  1182. }
  1183. static u32 pmic_arb_apid_map_offset_v2(u16 n)
  1184. {
  1185. return 0x800 + 0x4 * n;
  1186. }
  1187. static u32 pmic_arb_apid_map_offset_v5(u16 n)
  1188. {
  1189. return 0x900 + 0x4 * n;
  1190. }
  1191. static u32 pmic_arb_apid_map_offset_v7(u16 n)
  1192. {
  1193. return 0x2000 + 0x4 * n;
  1194. }
  1195. static void __iomem *
  1196. pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  1197. {
  1198. return pmic_arb->cnfg + 0x700 + 0x4 * n;
  1199. }
  1200. /*
  1201. * For arbiter version 7, APID ownership table registers have independent
  1202. * numbering space for each SPMI bus instance, so each is indexed starting from
  1203. * 0.
  1204. */
  1205. static void __iomem *
  1206. pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
  1207. {
  1208. return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid);
  1209. }
  1210. static const struct pmic_arb_ver_ops pmic_arb_v1 = {
  1211. .ver_str = "v1",
  1212. .ppid_to_apid = pmic_arb_ppid_to_apid_v1,
  1213. .non_data_cmd = pmic_arb_non_data_cmd_v1,
  1214. .offset = pmic_arb_offset_v1,
  1215. .fmt_cmd = pmic_arb_fmt_cmd_v1,
  1216. .owner_acc_status = pmic_arb_owner_acc_status_v1,
  1217. .acc_enable = pmic_arb_acc_enable_v1,
  1218. .irq_status = pmic_arb_irq_status_v1,
  1219. .irq_clear = pmic_arb_irq_clear_v1,
  1220. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  1221. .wr_addr_map = pmic_arb_wr_addr_map_v1,
  1222. };
  1223. static const struct pmic_arb_ver_ops pmic_arb_v2 = {
  1224. .ver_str = "v2",
  1225. .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
  1226. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  1227. .offset = pmic_arb_offset_v2,
  1228. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  1229. .owner_acc_status = pmic_arb_owner_acc_status_v2,
  1230. .acc_enable = pmic_arb_acc_enable_v2,
  1231. .irq_status = pmic_arb_irq_status_v2,
  1232. .irq_clear = pmic_arb_irq_clear_v2,
  1233. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  1234. .apid_owner = pmic_arb_apid_owner_v2,
  1235. .wr_addr_map = pmic_arb_wr_addr_map_v2,
  1236. };
  1237. static const struct pmic_arb_ver_ops pmic_arb_v3 = {
  1238. .ver_str = "v3",
  1239. .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
  1240. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  1241. .offset = pmic_arb_offset_v2,
  1242. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  1243. .owner_acc_status = pmic_arb_owner_acc_status_v3,
  1244. .acc_enable = pmic_arb_acc_enable_v2,
  1245. .irq_status = pmic_arb_irq_status_v2,
  1246. .irq_clear = pmic_arb_irq_clear_v2,
  1247. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  1248. .apid_owner = pmic_arb_apid_owner_v2,
  1249. .wr_addr_map = pmic_arb_wr_addr_map_v2,
  1250. };
  1251. static const struct pmic_arb_ver_ops pmic_arb_v5 = {
  1252. .ver_str = "v5",
  1253. .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
  1254. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  1255. .offset = pmic_arb_offset_v5,
  1256. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  1257. .owner_acc_status = pmic_arb_owner_acc_status_v5,
  1258. .acc_enable = pmic_arb_acc_enable_v5,
  1259. .irq_status = pmic_arb_irq_status_v5,
  1260. .irq_clear = pmic_arb_irq_clear_v5,
  1261. .apid_map_offset = pmic_arb_apid_map_offset_v5,
  1262. .apid_owner = pmic_arb_apid_owner_v2,
  1263. .wr_addr_map = pmic_arb_wr_addr_map_v5,
  1264. };
  1265. static const struct pmic_arb_ver_ops pmic_arb_v7 = {
  1266. .ver_str = "v7",
  1267. .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
  1268. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  1269. .offset = pmic_arb_offset_v7,
  1270. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  1271. .owner_acc_status = pmic_arb_owner_acc_status_v7,
  1272. .acc_enable = pmic_arb_acc_enable_v7,
  1273. .irq_status = pmic_arb_irq_status_v7,
  1274. .irq_clear = pmic_arb_irq_clear_v7,
  1275. .apid_map_offset = pmic_arb_apid_map_offset_v7,
  1276. .apid_owner = pmic_arb_apid_owner_v7,
  1277. .wr_addr_map = pmic_arb_wr_addr_map_v7,
  1278. };
  1279. static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
  1280. .activate = qpnpint_irq_domain_activate,
  1281. .alloc = qpnpint_irq_domain_alloc,
  1282. .free = irq_domain_free_irqs_common,
  1283. .translate = qpnpint_irq_domain_translate,
  1284. };
  1285. static int _spmi_pmic_arb_map_address(struct spmi_pmic_arb *pmic_arb,
  1286. u32 spmi_address, struct resource *res_out)
  1287. {
  1288. u32 sid, addr;
  1289. sid = (spmi_address >> 16) & 0xF;
  1290. addr = spmi_address & 0xFFFF;
  1291. return pmic_arb->ver_ops->wr_addr_map(pmic_arb, sid, addr, res_out);
  1292. }
  1293. /**
  1294. * spmi_pmic_arb_map_address() - returns physical addresses of registers used to
  1295. * write to the PMIC peripheral at spmi_address
  1296. * @dev: Consumer device pointer
  1297. * @spmi_address: 20-bit SPMI address of the form: 0xSPPPP
  1298. * where S = global PMIC SID and
  1299. * PPPP = SPMI address within the slave
  1300. * @res_out: Resource struct (allocated by the caller) in which
  1301. * physical addresses for the range are passed via start
  1302. * and end elements
  1303. *
  1304. * Returns: 0 on success or an errno on failure.
  1305. */
  1306. int spmi_pmic_arb_map_address(const struct device *dev, u32 spmi_address,
  1307. struct resource *res_out)
  1308. {
  1309. struct device_node *ctrl_node;
  1310. struct platform_device *ctrl_pdev;
  1311. struct spmi_controller *ctrl;
  1312. struct spmi_pmic_arb *pmic_arb;
  1313. if (!dev || !dev->of_node || !res_out) {
  1314. pr_err("%s: Invalid pointer\n", __func__);
  1315. return -EINVAL;
  1316. }
  1317. ctrl_node = of_parse_phandle(dev->of_node, "qcom,pmic-arb", 0);
  1318. if (!ctrl_node) {
  1319. pr_err("%s: Could not find PMIC arbiter node via qcom,pmic-arb property\n",
  1320. __func__);
  1321. return -ENODEV;
  1322. }
  1323. ctrl_pdev = of_find_device_by_node(ctrl_node);
  1324. of_node_put(ctrl_node);
  1325. if (!ctrl_pdev)
  1326. return -EPROBE_DEFER;
  1327. ctrl = platform_get_drvdata(ctrl_pdev);
  1328. if (!ctrl)
  1329. return -EPROBE_DEFER;
  1330. pmic_arb = spmi_controller_get_drvdata(ctrl);
  1331. if (!pmic_arb) {
  1332. pr_err("Missing PMIC arbiter device\n");
  1333. return -ENODEV;
  1334. }
  1335. return _spmi_pmic_arb_map_address(pmic_arb, spmi_address, res_out);
  1336. }
  1337. EXPORT_SYMBOL(spmi_pmic_arb_map_address);
  1338. #ifdef CONFIG_DEBUG_FS
  1339. static int debug_spmi_addr_get(void *data, u64 *val)
  1340. {
  1341. struct spmi_pmic_arb *pmic_arb = data;
  1342. *val = pmic_arb->debug_spmi_addr;
  1343. return 0;
  1344. }
  1345. static int debug_spmi_addr_set(void *data, u64 val)
  1346. {
  1347. struct spmi_pmic_arb *pmic_arb = data;
  1348. pmic_arb->debug_spmi_addr = val;
  1349. return 0;
  1350. }
  1351. DEFINE_DEBUGFS_ATTRIBUTE(debug_spmi_addr_fops, debug_spmi_addr_get,
  1352. debug_spmi_addr_set, "0x%05llX\n");
  1353. static int debug_soc_start_addr_get(void *data, u64 *val)
  1354. {
  1355. struct spmi_pmic_arb *pmic_arb = data;
  1356. struct resource res = {0};
  1357. int err;
  1358. err = _spmi_pmic_arb_map_address(pmic_arb, pmic_arb->debug_spmi_addr,
  1359. &res);
  1360. if (err)
  1361. return err;
  1362. *val = res.start;
  1363. return 0;
  1364. }
  1365. DEFINE_DEBUGFS_ATTRIBUTE(debug_soc_start_addr_fops, debug_soc_start_addr_get,
  1366. NULL, "0x%llX\n");
  1367. static int debug_soc_end_addr_get(void *data, u64 *val)
  1368. {
  1369. struct spmi_pmic_arb *pmic_arb = data;
  1370. struct resource res = {0};
  1371. int err;
  1372. err = _spmi_pmic_arb_map_address(pmic_arb, pmic_arb->debug_spmi_addr,
  1373. &res);
  1374. if (err)
  1375. return err;
  1376. *val = res.end;
  1377. return 0;
  1378. }
  1379. DEFINE_DEBUGFS_ATTRIBUTE(debug_soc_end_addr_fops, debug_soc_end_addr_get,
  1380. NULL, "0x%llX\n");
  1381. static void spmi_pmic_arb_debugfs_init(struct spmi_pmic_arb *pmic_arb)
  1382. {
  1383. struct dentry *dir, *file;
  1384. char buf[10];
  1385. scnprintf(buf, sizeof(buf), "spmi%u", pmic_arb->spmic->nr);
  1386. dir = debugfs_create_dir(buf, NULL);
  1387. if (IS_ERR(dir)) {
  1388. dev_err(&pmic_arb->spmic->dev, "Could not create %s debugfs directory, rc=%ld\n",
  1389. buf, PTR_ERR(dir));
  1390. return;
  1391. }
  1392. pmic_arb->debugfs = dir;
  1393. dir = debugfs_create_dir("address_map", pmic_arb->debugfs);
  1394. if (IS_ERR(dir)) {
  1395. dev_err(&pmic_arb->spmic->dev, "Could not create address_map debugfs directory, rc=%ld\n",
  1396. PTR_ERR(dir));
  1397. goto error;
  1398. }
  1399. file = debugfs_create_file_unsafe("spmi_addr", 0600, dir, pmic_arb,
  1400. &debug_spmi_addr_fops);
  1401. if (IS_ERR(file)) {
  1402. dev_err(&pmic_arb->spmic->dev, "Could not create spmi_addr debugfs file, rc=%ld\n",
  1403. PTR_ERR(file));
  1404. goto error;
  1405. }
  1406. file = debugfs_create_file_unsafe("soc_addr_start", 0400, dir, pmic_arb,
  1407. &debug_soc_start_addr_fops);
  1408. if (IS_ERR(file)) {
  1409. dev_err(&pmic_arb->spmic->dev, "Could not create soc_addr_start debugfs file, rc=%ld\n",
  1410. PTR_ERR(file));
  1411. goto error;
  1412. }
  1413. file = debugfs_create_file_unsafe("soc_addr_end", 0400, dir, pmic_arb,
  1414. &debug_soc_end_addr_fops);
  1415. if (IS_ERR(file)) {
  1416. dev_err(&pmic_arb->spmic->dev, "Could not create soc_addr_end debugfs file, rc=%ld\n",
  1417. PTR_ERR(file));
  1418. goto error;
  1419. }
  1420. return;
  1421. error:
  1422. debugfs_remove_recursive(pmic_arb->debugfs);
  1423. }
  1424. #else
  1425. static void spmi_pmic_arb_debugfs_init(struct spmi_pmic_arb *pmic_arb) { }
  1426. #endif
  1427. static int spmi_pmic_arb_probe(struct platform_device *pdev)
  1428. {
  1429. struct spmi_pmic_arb *pmic_arb;
  1430. struct spmi_controller *ctrl;
  1431. struct resource *res;
  1432. void __iomem *core;
  1433. u32 *mapping_table;
  1434. u32 channel, ee, hw_ver;
  1435. int err;
  1436. ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
  1437. if (!ctrl)
  1438. return -ENOMEM;
  1439. pmic_arb = spmi_controller_get_drvdata(ctrl);
  1440. pmic_arb->spmic = ctrl;
  1441. /*
  1442. * Please don't replace this with devm_platform_ioremap_resource() or
  1443. * devm_ioremap_resource(). These both result in a call to
  1444. * devm_request_mem_region() which prevents multiple mappings of this
  1445. * register address range. SoCs with PMIC arbiter v7 may define two
  1446. * arbiter devices, for the two physical SPMI interfaces, which share
  1447. * some register address ranges (i.e. "core", "obsrvr", and "chnls").
  1448. * Ensure that both devices probe successfully by calling devm_ioremap()
  1449. * which does not result in a devm_request_mem_region() call.
  1450. */
  1451. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
  1452. if (!res) {
  1453. err = -EINVAL;
  1454. goto err_put_ctrl;
  1455. }
  1456. core = devm_ioremap(&ctrl->dev, res->start, resource_size(res));
  1457. if (IS_ERR(core)) {
  1458. err = PTR_ERR(core);
  1459. goto err_put_ctrl;
  1460. }
  1461. pmic_arb->core_size = resource_size(res);
  1462. pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
  1463. sizeof(*pmic_arb->ppid_to_apid),
  1464. GFP_KERNEL);
  1465. if (!pmic_arb->ppid_to_apid) {
  1466. err = -ENOMEM;
  1467. goto err_put_ctrl;
  1468. }
  1469. hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
  1470. if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
  1471. pmic_arb->ver_ops = &pmic_arb_v1;
  1472. pmic_arb->wr_base = core;
  1473. pmic_arb->wr_base_phys = res->start;
  1474. pmic_arb->rd_base = core;
  1475. } else {
  1476. pmic_arb->core = core;
  1477. if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
  1478. pmic_arb->ver_ops = &pmic_arb_v2;
  1479. else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
  1480. pmic_arb->ver_ops = &pmic_arb_v3;
  1481. else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
  1482. pmic_arb->ver_ops = &pmic_arb_v5;
  1483. else
  1484. pmic_arb->ver_ops = &pmic_arb_v7;
  1485. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1486. "obsrvr");
  1487. if (!res) {
  1488. err = -EINVAL;
  1489. goto err_put_ctrl;
  1490. }
  1491. pmic_arb->rd_base = devm_ioremap(&ctrl->dev, res->start,
  1492. resource_size(res));
  1493. if (IS_ERR(pmic_arb->rd_base)) {
  1494. err = PTR_ERR(pmic_arb->rd_base);
  1495. goto err_put_ctrl;
  1496. }
  1497. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1498. "chnls");
  1499. if (!res) {
  1500. err = -EINVAL;
  1501. goto err_put_ctrl;
  1502. }
  1503. pmic_arb->wr_base = devm_ioremap(&ctrl->dev, res->start,
  1504. resource_size(res));
  1505. if (IS_ERR(pmic_arb->wr_base)) {
  1506. err = PTR_ERR(pmic_arb->wr_base);
  1507. goto err_put_ctrl;
  1508. }
  1509. pmic_arb->wr_base_phys = res->start;
  1510. }
  1511. pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
  1512. if (hw_ver >= PMIC_ARB_VERSION_V7_MIN) {
  1513. pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
  1514. /* Optional property for v7: */
  1515. of_property_read_u32(pdev->dev.of_node, "qcom,bus-id",
  1516. &pmic_arb->bus_instance);
  1517. if (pmic_arb->bus_instance > 1) {
  1518. err = -EINVAL;
  1519. dev_err(&pdev->dev, "invalid bus instance (%u) specified\n",
  1520. pmic_arb->bus_instance);
  1521. goto err_put_ctrl;
  1522. }
  1523. if (pmic_arb->bus_instance == 0) {
  1524. pmic_arb->base_apid = 0;
  1525. pmic_arb->apid_count =
  1526. readl_relaxed(core + PMIC_ARB_FEATURES) &
  1527. PMIC_ARB_FEATURES_PERIPH_MASK;
  1528. } else {
  1529. pmic_arb->base_apid =
  1530. readl_relaxed(core + PMIC_ARB_FEATURES) &
  1531. PMIC_ARB_FEATURES_PERIPH_MASK;
  1532. pmic_arb->apid_count =
  1533. readl_relaxed(core + PMIC_ARB_FEATURES1) &
  1534. PMIC_ARB_FEATURES_PERIPH_MASK;
  1535. }
  1536. if (pmic_arb->base_apid + pmic_arb->apid_count >
  1537. pmic_arb->max_periphs) {
  1538. err = -EINVAL;
  1539. dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
  1540. pmic_arb->base_apid + pmic_arb->apid_count);
  1541. goto err_put_ctrl;
  1542. }
  1543. } else if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
  1544. pmic_arb->base_apid = 0;
  1545. pmic_arb->apid_count = readl_relaxed(core + PMIC_ARB_FEATURES) &
  1546. PMIC_ARB_FEATURES_PERIPH_MASK;
  1547. if (pmic_arb->apid_count > pmic_arb->max_periphs) {
  1548. err = -EINVAL;
  1549. dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
  1550. pmic_arb->apid_count);
  1551. goto err_put_ctrl;
  1552. }
  1553. }
  1554. pmic_arb->apid_data = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
  1555. sizeof(*pmic_arb->apid_data),
  1556. GFP_KERNEL);
  1557. if (!pmic_arb->apid_data) {
  1558. err = -ENOMEM;
  1559. goto err_put_ctrl;
  1560. }
  1561. dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
  1562. pmic_arb->ver_ops->ver_str, hw_ver);
  1563. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
  1564. if (!res) {
  1565. err = -EINVAL;
  1566. goto err_put_ctrl;
  1567. }
  1568. pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
  1569. if (IS_ERR(pmic_arb->intr)) {
  1570. err = PTR_ERR(pmic_arb->intr);
  1571. goto err_put_ctrl;
  1572. }
  1573. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
  1574. if (!res) {
  1575. err = -EINVAL;
  1576. goto err_put_ctrl;
  1577. }
  1578. pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
  1579. if (IS_ERR(pmic_arb->cnfg)) {
  1580. err = PTR_ERR(pmic_arb->cnfg);
  1581. goto err_put_ctrl;
  1582. }
  1583. if (of_find_property(pdev->dev.of_node, "interrupt-names", NULL)) {
  1584. pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
  1585. if (pmic_arb->irq < 0) {
  1586. err = pmic_arb->irq;
  1587. goto err_put_ctrl;
  1588. }
  1589. }
  1590. err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
  1591. if (err) {
  1592. dev_err(&pdev->dev, "channel unspecified.\n");
  1593. goto err_put_ctrl;
  1594. }
  1595. if (channel > 5) {
  1596. dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
  1597. channel);
  1598. err = -EINVAL;
  1599. goto err_put_ctrl;
  1600. }
  1601. pmic_arb->channel = channel;
  1602. err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
  1603. if (err) {
  1604. dev_err(&pdev->dev, "EE unspecified.\n");
  1605. goto err_put_ctrl;
  1606. }
  1607. if (ee > 5) {
  1608. dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
  1609. err = -EINVAL;
  1610. goto err_put_ctrl;
  1611. }
  1612. pmic_arb->ee = ee;
  1613. mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
  1614. sizeof(*mapping_table), GFP_KERNEL);
  1615. if (!mapping_table) {
  1616. err = -ENOMEM;
  1617. goto err_put_ctrl;
  1618. }
  1619. pmic_arb->mapping_table = mapping_table;
  1620. /* Initialize max_apid/min_apid to the opposite bounds, during
  1621. * the irq domain translation, we are sure to update these */
  1622. pmic_arb->max_apid = 0;
  1623. pmic_arb->min_apid = pmic_arb->max_periphs - 1;
  1624. platform_set_drvdata(pdev, ctrl);
  1625. raw_spin_lock_init(&pmic_arb->lock);
  1626. ctrl->cmd = pmic_arb_cmd;
  1627. ctrl->read_cmd = pmic_arb_read_cmd;
  1628. ctrl->write_cmd = pmic_arb_write_cmd;
  1629. if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
  1630. err = pmic_arb_read_apid_map_v5(pmic_arb);
  1631. if (err) {
  1632. dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
  1633. err);
  1634. goto err_put_ctrl;
  1635. }
  1636. }
  1637. if (pmic_arb->irq > 0) {
  1638. dev_dbg(&pdev->dev, "adding irq domain\n");
  1639. pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
  1640. &pmic_arb_irq_domain_ops, pmic_arb);
  1641. if (!pmic_arb->domain) {
  1642. dev_err(&pdev->dev, "unable to create irq_domain\n");
  1643. err = -ENOMEM;
  1644. goto err_put_ctrl;
  1645. }
  1646. irq_set_chained_handler_and_data(pmic_arb->irq,
  1647. pmic_arb_chained_irq, pmic_arb);
  1648. } else {
  1649. dev_dbg(&pdev->dev, "not supporting PMIC interrupts\n");
  1650. }
  1651. err = spmi_controller_add(ctrl);
  1652. if (err)
  1653. goto err_domain_remove;
  1654. spmi_pmic_arb_debugfs_init(pmic_arb);
  1655. return 0;
  1656. err_domain_remove:
  1657. if (pmic_arb->irq > 0) {
  1658. irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
  1659. irq_domain_remove(pmic_arb->domain);
  1660. }
  1661. err_put_ctrl:
  1662. spmi_controller_put(ctrl);
  1663. return err;
  1664. }
  1665. static int spmi_pmic_arb_remove(struct platform_device *pdev)
  1666. {
  1667. struct spmi_controller *ctrl = platform_get_drvdata(pdev);
  1668. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  1669. debugfs_remove_recursive(pmic_arb->debugfs);
  1670. spmi_controller_remove(ctrl);
  1671. if (pmic_arb->irq > 0) {
  1672. irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
  1673. irq_domain_remove(pmic_arb->domain);
  1674. }
  1675. spmi_controller_put(ctrl);
  1676. return 0;
  1677. }
  1678. static const struct of_device_id spmi_pmic_arb_match_table[] = {
  1679. { .compatible = "qcom,spmi-pmic-arb", },
  1680. {},
  1681. };
  1682. MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
  1683. static struct platform_driver spmi_pmic_arb_driver = {
  1684. .probe = spmi_pmic_arb_probe,
  1685. .remove = spmi_pmic_arb_remove,
  1686. .driver = {
  1687. .name = "spmi_pmic_arb",
  1688. .of_match_table = spmi_pmic_arb_match_table,
  1689. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1690. },
  1691. };
  1692. static int __init spmi_pmic_arb_init(void)
  1693. {
  1694. return platform_driver_register(&spmi_pmic_arb_driver);
  1695. }
  1696. arch_initcall(spmi_pmic_arb_init);
  1697. static void __exit spmi_pmic_arb_exit(void)
  1698. {
  1699. platform_driver_unregister(&spmi_pmic_arb_driver);
  1700. }
  1701. module_exit(spmi_pmic_arb_exit);
  1702. MODULE_LICENSE("GPL v2");
  1703. MODULE_ALIAS("platform:spmi_pmic_arb");