spmi-mtk-pmif.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2021 MediaTek Inc.
  4. #include <linux/clk.h>
  5. #include <linux/iopoll.h>
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/property.h>
  10. #include <linux/spmi.h>
  11. #define SWINF_IDLE 0x00
  12. #define SWINF_WFVLDCLR 0x06
  13. #define GET_SWINF(x) (((x) >> 1) & 0x7)
  14. #define PMIF_CMD_REG_0 0
  15. #define PMIF_CMD_REG 1
  16. #define PMIF_CMD_EXT_REG 2
  17. #define PMIF_CMD_EXT_REG_LONG 3
  18. #define PMIF_DELAY_US 10
  19. #define PMIF_TIMEOUT_US (10 * 1000)
  20. #define PMIF_CHAN_OFFSET 0x5
  21. #define PMIF_MAX_CLKS 3
  22. #define SPMI_OP_ST_BUSY 1
  23. struct ch_reg {
  24. u32 ch_sta;
  25. u32 wdata;
  26. u32 rdata;
  27. u32 ch_send;
  28. u32 ch_rdy;
  29. };
  30. struct pmif_data {
  31. const u32 *regs;
  32. const u32 *spmimst_regs;
  33. u32 soc_chan;
  34. };
  35. struct pmif {
  36. void __iomem *base;
  37. void __iomem *spmimst_base;
  38. struct ch_reg chan;
  39. struct clk_bulk_data clks[PMIF_MAX_CLKS];
  40. size_t nclks;
  41. const struct pmif_data *data;
  42. };
  43. static const char * const pmif_clock_names[] = {
  44. "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
  45. };
  46. enum pmif_regs {
  47. PMIF_INIT_DONE,
  48. PMIF_INF_EN,
  49. PMIF_ARB_EN,
  50. PMIF_CMDISSUE_EN,
  51. PMIF_TIMER_CTRL,
  52. PMIF_SPI_MODE_CTRL,
  53. PMIF_IRQ_EVENT_EN_0,
  54. PMIF_IRQ_FLAG_0,
  55. PMIF_IRQ_CLR_0,
  56. PMIF_IRQ_EVENT_EN_1,
  57. PMIF_IRQ_FLAG_1,
  58. PMIF_IRQ_CLR_1,
  59. PMIF_IRQ_EVENT_EN_2,
  60. PMIF_IRQ_FLAG_2,
  61. PMIF_IRQ_CLR_2,
  62. PMIF_IRQ_EVENT_EN_3,
  63. PMIF_IRQ_FLAG_3,
  64. PMIF_IRQ_CLR_3,
  65. PMIF_IRQ_EVENT_EN_4,
  66. PMIF_IRQ_FLAG_4,
  67. PMIF_IRQ_CLR_4,
  68. PMIF_WDT_EVENT_EN_0,
  69. PMIF_WDT_FLAG_0,
  70. PMIF_WDT_EVENT_EN_1,
  71. PMIF_WDT_FLAG_1,
  72. PMIF_SWINF_0_STA,
  73. PMIF_SWINF_0_WDATA_31_0,
  74. PMIF_SWINF_0_RDATA_31_0,
  75. PMIF_SWINF_0_ACC,
  76. PMIF_SWINF_0_VLD_CLR,
  77. PMIF_SWINF_1_STA,
  78. PMIF_SWINF_1_WDATA_31_0,
  79. PMIF_SWINF_1_RDATA_31_0,
  80. PMIF_SWINF_1_ACC,
  81. PMIF_SWINF_1_VLD_CLR,
  82. PMIF_SWINF_2_STA,
  83. PMIF_SWINF_2_WDATA_31_0,
  84. PMIF_SWINF_2_RDATA_31_0,
  85. PMIF_SWINF_2_ACC,
  86. PMIF_SWINF_2_VLD_CLR,
  87. PMIF_SWINF_3_STA,
  88. PMIF_SWINF_3_WDATA_31_0,
  89. PMIF_SWINF_3_RDATA_31_0,
  90. PMIF_SWINF_3_ACC,
  91. PMIF_SWINF_3_VLD_CLR,
  92. };
  93. static const u32 mt6873_regs[] = {
  94. [PMIF_INIT_DONE] = 0x0000,
  95. [PMIF_INF_EN] = 0x0024,
  96. [PMIF_ARB_EN] = 0x0150,
  97. [PMIF_CMDISSUE_EN] = 0x03B4,
  98. [PMIF_TIMER_CTRL] = 0x03E0,
  99. [PMIF_SPI_MODE_CTRL] = 0x0400,
  100. [PMIF_IRQ_EVENT_EN_0] = 0x0418,
  101. [PMIF_IRQ_FLAG_0] = 0x0420,
  102. [PMIF_IRQ_CLR_0] = 0x0424,
  103. [PMIF_IRQ_EVENT_EN_1] = 0x0428,
  104. [PMIF_IRQ_FLAG_1] = 0x0430,
  105. [PMIF_IRQ_CLR_1] = 0x0434,
  106. [PMIF_IRQ_EVENT_EN_2] = 0x0438,
  107. [PMIF_IRQ_FLAG_2] = 0x0440,
  108. [PMIF_IRQ_CLR_2] = 0x0444,
  109. [PMIF_IRQ_EVENT_EN_3] = 0x0448,
  110. [PMIF_IRQ_FLAG_3] = 0x0450,
  111. [PMIF_IRQ_CLR_3] = 0x0454,
  112. [PMIF_IRQ_EVENT_EN_4] = 0x0458,
  113. [PMIF_IRQ_FLAG_4] = 0x0460,
  114. [PMIF_IRQ_CLR_4] = 0x0464,
  115. [PMIF_WDT_EVENT_EN_0] = 0x046C,
  116. [PMIF_WDT_FLAG_0] = 0x0470,
  117. [PMIF_WDT_EVENT_EN_1] = 0x0474,
  118. [PMIF_WDT_FLAG_1] = 0x0478,
  119. [PMIF_SWINF_0_ACC] = 0x0C00,
  120. [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
  121. [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
  122. [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
  123. [PMIF_SWINF_0_STA] = 0x0C28,
  124. [PMIF_SWINF_1_ACC] = 0x0C40,
  125. [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
  126. [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
  127. [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
  128. [PMIF_SWINF_1_STA] = 0x0C68,
  129. [PMIF_SWINF_2_ACC] = 0x0C80,
  130. [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
  131. [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
  132. [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
  133. [PMIF_SWINF_2_STA] = 0x0CA8,
  134. [PMIF_SWINF_3_ACC] = 0x0CC0,
  135. [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
  136. [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
  137. [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
  138. [PMIF_SWINF_3_STA] = 0x0CE8,
  139. };
  140. static const u32 mt8195_regs[] = {
  141. [PMIF_INIT_DONE] = 0x0000,
  142. [PMIF_INF_EN] = 0x0024,
  143. [PMIF_ARB_EN] = 0x0150,
  144. [PMIF_CMDISSUE_EN] = 0x03B8,
  145. [PMIF_TIMER_CTRL] = 0x03E4,
  146. [PMIF_SPI_MODE_CTRL] = 0x0408,
  147. [PMIF_IRQ_EVENT_EN_0] = 0x0420,
  148. [PMIF_IRQ_FLAG_0] = 0x0428,
  149. [PMIF_IRQ_CLR_0] = 0x042C,
  150. [PMIF_IRQ_EVENT_EN_1] = 0x0430,
  151. [PMIF_IRQ_FLAG_1] = 0x0438,
  152. [PMIF_IRQ_CLR_1] = 0x043C,
  153. [PMIF_IRQ_EVENT_EN_2] = 0x0440,
  154. [PMIF_IRQ_FLAG_2] = 0x0448,
  155. [PMIF_IRQ_CLR_2] = 0x044C,
  156. [PMIF_IRQ_EVENT_EN_3] = 0x0450,
  157. [PMIF_IRQ_FLAG_3] = 0x0458,
  158. [PMIF_IRQ_CLR_3] = 0x045C,
  159. [PMIF_IRQ_EVENT_EN_4] = 0x0460,
  160. [PMIF_IRQ_FLAG_4] = 0x0468,
  161. [PMIF_IRQ_CLR_4] = 0x046C,
  162. [PMIF_WDT_EVENT_EN_0] = 0x0474,
  163. [PMIF_WDT_FLAG_0] = 0x0478,
  164. [PMIF_WDT_EVENT_EN_1] = 0x047C,
  165. [PMIF_WDT_FLAG_1] = 0x0480,
  166. [PMIF_SWINF_0_ACC] = 0x0800,
  167. [PMIF_SWINF_0_WDATA_31_0] = 0x0804,
  168. [PMIF_SWINF_0_RDATA_31_0] = 0x0814,
  169. [PMIF_SWINF_0_VLD_CLR] = 0x0824,
  170. [PMIF_SWINF_0_STA] = 0x0828,
  171. [PMIF_SWINF_1_ACC] = 0x0840,
  172. [PMIF_SWINF_1_WDATA_31_0] = 0x0844,
  173. [PMIF_SWINF_1_RDATA_31_0] = 0x0854,
  174. [PMIF_SWINF_1_VLD_CLR] = 0x0864,
  175. [PMIF_SWINF_1_STA] = 0x0868,
  176. [PMIF_SWINF_2_ACC] = 0x0880,
  177. [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
  178. [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
  179. [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
  180. [PMIF_SWINF_2_STA] = 0x08A8,
  181. [PMIF_SWINF_3_ACC] = 0x08C0,
  182. [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
  183. [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
  184. [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
  185. [PMIF_SWINF_3_STA] = 0x08E8,
  186. };
  187. enum spmi_regs {
  188. SPMI_OP_ST_CTRL,
  189. SPMI_GRP_ID_EN,
  190. SPMI_OP_ST_STA,
  191. SPMI_MST_SAMPL,
  192. SPMI_MST_REQ_EN,
  193. SPMI_REC_CTRL,
  194. SPMI_REC0,
  195. SPMI_REC1,
  196. SPMI_REC2,
  197. SPMI_REC3,
  198. SPMI_REC4,
  199. SPMI_MST_DBG,
  200. /* MT8195 spmi regs */
  201. SPMI_MST_RCS_CTRL,
  202. SPMI_SLV_3_0_EINT,
  203. SPMI_SLV_7_4_EINT,
  204. SPMI_SLV_B_8_EINT,
  205. SPMI_SLV_F_C_EINT,
  206. SPMI_REC_CMD_DEC,
  207. SPMI_DEC_DBG,
  208. };
  209. static const u32 mt6873_spmi_regs[] = {
  210. [SPMI_OP_ST_CTRL] = 0x0000,
  211. [SPMI_GRP_ID_EN] = 0x0004,
  212. [SPMI_OP_ST_STA] = 0x0008,
  213. [SPMI_MST_SAMPL] = 0x000c,
  214. [SPMI_MST_REQ_EN] = 0x0010,
  215. [SPMI_REC_CTRL] = 0x0040,
  216. [SPMI_REC0] = 0x0044,
  217. [SPMI_REC1] = 0x0048,
  218. [SPMI_REC2] = 0x004c,
  219. [SPMI_REC3] = 0x0050,
  220. [SPMI_REC4] = 0x0054,
  221. [SPMI_MST_DBG] = 0x00fc,
  222. };
  223. static const u32 mt8195_spmi_regs[] = {
  224. [SPMI_OP_ST_CTRL] = 0x0000,
  225. [SPMI_GRP_ID_EN] = 0x0004,
  226. [SPMI_OP_ST_STA] = 0x0008,
  227. [SPMI_MST_SAMPL] = 0x000C,
  228. [SPMI_MST_REQ_EN] = 0x0010,
  229. [SPMI_MST_RCS_CTRL] = 0x0014,
  230. [SPMI_SLV_3_0_EINT] = 0x0020,
  231. [SPMI_SLV_7_4_EINT] = 0x0024,
  232. [SPMI_SLV_B_8_EINT] = 0x0028,
  233. [SPMI_SLV_F_C_EINT] = 0x002C,
  234. [SPMI_REC_CTRL] = 0x0040,
  235. [SPMI_REC0] = 0x0044,
  236. [SPMI_REC1] = 0x0048,
  237. [SPMI_REC2] = 0x004C,
  238. [SPMI_REC3] = 0x0050,
  239. [SPMI_REC4] = 0x0054,
  240. [SPMI_REC_CMD_DEC] = 0x005C,
  241. [SPMI_DEC_DBG] = 0x00F8,
  242. [SPMI_MST_DBG] = 0x00FC,
  243. };
  244. static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
  245. {
  246. return readl(arb->base + arb->data->regs[reg]);
  247. }
  248. static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
  249. {
  250. writel(val, arb->base + arb->data->regs[reg]);
  251. }
  252. static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
  253. {
  254. writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
  255. }
  256. static bool pmif_is_fsm_vldclr(struct pmif *arb)
  257. {
  258. u32 reg_rdata;
  259. reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
  260. return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
  261. }
  262. static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
  263. {
  264. struct pmif *arb = spmi_controller_get_drvdata(ctrl);
  265. u32 rdata, cmd;
  266. int ret;
  267. /* Check the opcode */
  268. if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
  269. return -EINVAL;
  270. cmd = opc - SPMI_CMD_RESET;
  271. mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
  272. ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
  273. rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
  274. PMIF_DELAY_US, PMIF_TIMEOUT_US);
  275. if (ret < 0)
  276. dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
  277. return ret;
  278. }
  279. static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  280. u16 addr, u8 *buf, size_t len)
  281. {
  282. struct pmif *arb = spmi_controller_get_drvdata(ctrl);
  283. struct ch_reg *inf_reg;
  284. int ret;
  285. u32 data, cmd;
  286. /* Check for argument validation. */
  287. if (sid & ~0xf) {
  288. dev_err(&ctrl->dev, "exceed the max slv id\n");
  289. return -EINVAL;
  290. }
  291. if (len > 4) {
  292. dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
  293. return -EINVAL;
  294. }
  295. if (opc >= 0x60 && opc <= 0x7f)
  296. opc = PMIF_CMD_REG;
  297. else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
  298. opc = PMIF_CMD_EXT_REG_LONG;
  299. else
  300. return -EINVAL;
  301. /* Wait for Software Interface FSM state to be IDLE. */
  302. inf_reg = &arb->chan;
  303. ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
  304. data, GET_SWINF(data) == SWINF_IDLE,
  305. PMIF_DELAY_US, PMIF_TIMEOUT_US);
  306. if (ret < 0) {
  307. /* set channel ready if the data has transferred */
  308. if (pmif_is_fsm_vldclr(arb))
  309. pmif_writel(arb, 1, inf_reg->ch_rdy);
  310. dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
  311. return ret;
  312. }
  313. /* Send the command. */
  314. cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
  315. pmif_writel(arb, cmd, inf_reg->ch_send);
  316. /*
  317. * Wait for Software Interface FSM state to be WFVLDCLR,
  318. * read the data and clear the valid flag.
  319. */
  320. ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
  321. data, GET_SWINF(data) == SWINF_WFVLDCLR,
  322. PMIF_DELAY_US, PMIF_TIMEOUT_US);
  323. if (ret < 0) {
  324. dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
  325. return ret;
  326. }
  327. data = pmif_readl(arb, inf_reg->rdata);
  328. memcpy(buf, &data, len);
  329. pmif_writel(arb, 1, inf_reg->ch_rdy);
  330. return 0;
  331. }
  332. static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  333. u16 addr, const u8 *buf, size_t len)
  334. {
  335. struct pmif *arb = spmi_controller_get_drvdata(ctrl);
  336. struct ch_reg *inf_reg;
  337. int ret;
  338. u32 data, cmd;
  339. if (len > 4) {
  340. dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
  341. return -EINVAL;
  342. }
  343. /* Check the opcode */
  344. if (opc >= 0x40 && opc <= 0x5F)
  345. opc = PMIF_CMD_REG;
  346. else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
  347. opc = PMIF_CMD_EXT_REG_LONG;
  348. else if (opc >= 0x80)
  349. opc = PMIF_CMD_REG_0;
  350. else
  351. return -EINVAL;
  352. /* Wait for Software Interface FSM state to be IDLE. */
  353. inf_reg = &arb->chan;
  354. ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
  355. data, GET_SWINF(data) == SWINF_IDLE,
  356. PMIF_DELAY_US, PMIF_TIMEOUT_US);
  357. if (ret < 0) {
  358. /* set channel ready if the data has transferred */
  359. if (pmif_is_fsm_vldclr(arb))
  360. pmif_writel(arb, 1, inf_reg->ch_rdy);
  361. dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
  362. return ret;
  363. }
  364. /* Set the write data. */
  365. memcpy(&data, buf, len);
  366. pmif_writel(arb, data, inf_reg->wdata);
  367. /* Send the command. */
  368. cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
  369. pmif_writel(arb, cmd, inf_reg->ch_send);
  370. return 0;
  371. }
  372. static const struct pmif_data mt6873_pmif_arb = {
  373. .regs = mt6873_regs,
  374. .spmimst_regs = mt6873_spmi_regs,
  375. .soc_chan = 2,
  376. };
  377. static const struct pmif_data mt8195_pmif_arb = {
  378. .regs = mt8195_regs,
  379. .spmimst_regs = mt8195_spmi_regs,
  380. .soc_chan = 2,
  381. };
  382. static int mtk_spmi_probe(struct platform_device *pdev)
  383. {
  384. struct pmif *arb;
  385. struct spmi_controller *ctrl;
  386. int err, i;
  387. u32 chan_offset;
  388. ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
  389. if (!ctrl)
  390. return -ENOMEM;
  391. arb = spmi_controller_get_drvdata(ctrl);
  392. arb->data = device_get_match_data(&pdev->dev);
  393. if (!arb->data) {
  394. err = -EINVAL;
  395. dev_err(&pdev->dev, "Cannot get drv_data\n");
  396. goto err_put_ctrl;
  397. }
  398. arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
  399. if (IS_ERR(arb->base)) {
  400. err = PTR_ERR(arb->base);
  401. goto err_put_ctrl;
  402. }
  403. arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
  404. if (IS_ERR(arb->spmimst_base)) {
  405. err = PTR_ERR(arb->spmimst_base);
  406. goto err_put_ctrl;
  407. }
  408. arb->nclks = ARRAY_SIZE(pmif_clock_names);
  409. for (i = 0; i < arb->nclks; i++)
  410. arb->clks[i].id = pmif_clock_names[i];
  411. err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
  412. if (err) {
  413. dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
  414. goto err_put_ctrl;
  415. }
  416. err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
  417. if (err) {
  418. dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
  419. goto err_put_ctrl;
  420. }
  421. ctrl->cmd = pmif_arb_cmd;
  422. ctrl->read_cmd = pmif_spmi_read_cmd;
  423. ctrl->write_cmd = pmif_spmi_write_cmd;
  424. chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
  425. arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
  426. arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
  427. arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
  428. arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
  429. arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
  430. platform_set_drvdata(pdev, ctrl);
  431. err = spmi_controller_add(ctrl);
  432. if (err)
  433. goto err_domain_remove;
  434. return 0;
  435. err_domain_remove:
  436. clk_bulk_disable_unprepare(arb->nclks, arb->clks);
  437. err_put_ctrl:
  438. spmi_controller_put(ctrl);
  439. return err;
  440. }
  441. static int mtk_spmi_remove(struct platform_device *pdev)
  442. {
  443. struct spmi_controller *ctrl = platform_get_drvdata(pdev);
  444. struct pmif *arb = spmi_controller_get_drvdata(ctrl);
  445. clk_bulk_disable_unprepare(arb->nclks, arb->clks);
  446. spmi_controller_remove(ctrl);
  447. spmi_controller_put(ctrl);
  448. return 0;
  449. }
  450. static const struct of_device_id mtk_spmi_match_table[] = {
  451. {
  452. .compatible = "mediatek,mt6873-spmi",
  453. .data = &mt6873_pmif_arb,
  454. }, {
  455. .compatible = "mediatek,mt8195-spmi",
  456. .data = &mt8195_pmif_arb,
  457. }, {
  458. /* sentinel */
  459. },
  460. };
  461. MODULE_DEVICE_TABLE(of, mtk_spmi_match_table);
  462. static struct platform_driver mtk_spmi_driver = {
  463. .driver = {
  464. .name = "spmi-mtk",
  465. .of_match_table = of_match_ptr(mtk_spmi_match_table),
  466. },
  467. .probe = mtk_spmi_probe,
  468. .remove = mtk_spmi_remove,
  469. };
  470. module_platform_driver(mtk_spmi_driver);
  471. MODULE_AUTHOR("Hsin-Hsiung Wang <[email protected]>");
  472. MODULE_DESCRIPTION("MediaTek SPMI Driver");
  473. MODULE_LICENSE("GPL");