spi-s3c64xx.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2009 Samsung Electronics Co., Ltd.
  4. // Jaswinder Singh <[email protected]>
  5. #include <linux/init.h>
  6. #include <linux/module.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/delay.h>
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_data/spi-s3c64xx.h>
  18. #define MAX_SPI_PORTS 12
  19. #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
  20. #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
  21. #define AUTOSUSPEND_TIMEOUT 2000
  22. /* Registers and bit-fields */
  23. #define S3C64XX_SPI_CH_CFG 0x00
  24. #define S3C64XX_SPI_CLK_CFG 0x04
  25. #define S3C64XX_SPI_MODE_CFG 0x08
  26. #define S3C64XX_SPI_CS_REG 0x0C
  27. #define S3C64XX_SPI_INT_EN 0x10
  28. #define S3C64XX_SPI_STATUS 0x14
  29. #define S3C64XX_SPI_TX_DATA 0x18
  30. #define S3C64XX_SPI_RX_DATA 0x1C
  31. #define S3C64XX_SPI_PACKET_CNT 0x20
  32. #define S3C64XX_SPI_PENDING_CLR 0x24
  33. #define S3C64XX_SPI_SWAP_CFG 0x28
  34. #define S3C64XX_SPI_FB_CLK 0x2C
  35. #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
  36. #define S3C64XX_SPI_CH_SW_RST (1<<5)
  37. #define S3C64XX_SPI_CH_SLAVE (1<<4)
  38. #define S3C64XX_SPI_CPOL_L (1<<3)
  39. #define S3C64XX_SPI_CPHA_B (1<<2)
  40. #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
  41. #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
  42. #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
  43. #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
  44. #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
  45. #define S3C64XX_SPI_PSR_MASK 0xff
  46. #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
  47. #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
  48. #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
  49. #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
  50. #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
  51. #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
  52. #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
  53. #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
  54. #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3)
  55. #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
  56. #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
  57. #define S3C64XX_SPI_MODE_4BURST (1<<0)
  58. #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
  59. #define S3C64XX_SPI_CS_AUTO (1<<1)
  60. #define S3C64XX_SPI_CS_SIG_INACT (1<<0)
  61. #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
  62. #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
  63. #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
  64. #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
  65. #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
  66. #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
  67. #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
  68. #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
  69. #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
  70. #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
  71. #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
  72. #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
  73. #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
  74. #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
  75. #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
  76. #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
  77. #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
  78. #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
  79. #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
  80. #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
  81. #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
  82. #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
  83. #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
  84. #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
  85. #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
  86. #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
  87. #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
  88. #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
  89. #define S3C64XX_SPI_FBCLK_MSK (3<<0)
  90. #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
  91. #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
  92. (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
  93. #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
  94. #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
  95. FIFO_LVL_MASK(i))
  96. #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
  97. #define S3C64XX_SPI_TRAILCNT_OFF 19
  98. #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
  99. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  100. #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
  101. #define RXBUSY (1<<2)
  102. #define TXBUSY (1<<3)
  103. struct s3c64xx_spi_dma_data {
  104. struct dma_chan *ch;
  105. dma_cookie_t cookie;
  106. enum dma_transfer_direction direction;
  107. };
  108. /**
  109. * struct s3c64xx_spi_port_config - SPI Controller hardware info
  110. * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
  111. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
  112. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
  113. * @clk_div: Internal clock divider
  114. * @quirks: Bitmask of known quirks
  115. * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
  116. * @clk_from_cmu: True, if the controller does not include a clock mux and
  117. * prescaler unit.
  118. * @clk_ioclk: True if clock is present on this device
  119. * @has_loopback: True if loopback mode can be supported
  120. *
  121. * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
  122. * differ in some aspects such as the size of the fifo and spi bus clock
  123. * setup. Such differences are specified to the driver using this structure
  124. * which is provided as driver data to the driver.
  125. */
  126. struct s3c64xx_spi_port_config {
  127. int fifo_lvl_mask[MAX_SPI_PORTS];
  128. int rx_lvl_offset;
  129. int tx_st_done;
  130. int quirks;
  131. int clk_div;
  132. bool high_speed;
  133. bool clk_from_cmu;
  134. bool clk_ioclk;
  135. bool has_loopback;
  136. };
  137. /**
  138. * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
  139. * @clk: Pointer to the spi clock.
  140. * @src_clk: Pointer to the clock used to generate SPI signals.
  141. * @ioclk: Pointer to the i/o clock between master and slave
  142. * @pdev: Pointer to device's platform device data
  143. * @master: Pointer to the SPI Protocol master.
  144. * @cntrlr_info: Platform specific data for the controller this driver manages.
  145. * @lock: Controller specific lock.
  146. * @state: Set of FLAGS to indicate status.
  147. * @sfr_start: BUS address of SPI controller regs.
  148. * @regs: Pointer to ioremap'ed controller registers.
  149. * @xfer_completion: To indicate completion of xfer task.
  150. * @cur_mode: Stores the active configuration of the controller.
  151. * @cur_bpw: Stores the active bits per word settings.
  152. * @cur_speed: Current clock speed
  153. * @rx_dma: Local receive DMA data (e.g. chan and direction)
  154. * @tx_dma: Local transmit DMA data (e.g. chan and direction)
  155. * @port_conf: Local SPI port configuartion data
  156. * @port_id: Port identification number
  157. */
  158. struct s3c64xx_spi_driver_data {
  159. void __iomem *regs;
  160. struct clk *clk;
  161. struct clk *src_clk;
  162. struct clk *ioclk;
  163. struct platform_device *pdev;
  164. struct spi_master *master;
  165. struct s3c64xx_spi_info *cntrlr_info;
  166. spinlock_t lock;
  167. unsigned long sfr_start;
  168. struct completion xfer_completion;
  169. unsigned state;
  170. unsigned cur_mode, cur_bpw;
  171. unsigned cur_speed;
  172. struct s3c64xx_spi_dma_data rx_dma;
  173. struct s3c64xx_spi_dma_data tx_dma;
  174. const struct s3c64xx_spi_port_config *port_conf;
  175. unsigned int port_id;
  176. };
  177. static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
  178. {
  179. void __iomem *regs = sdd->regs;
  180. unsigned long loops;
  181. u32 val;
  182. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  183. val = readl(regs + S3C64XX_SPI_CH_CFG);
  184. val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
  185. writel(val, regs + S3C64XX_SPI_CH_CFG);
  186. val = readl(regs + S3C64XX_SPI_CH_CFG);
  187. val |= S3C64XX_SPI_CH_SW_RST;
  188. val &= ~S3C64XX_SPI_CH_HS_EN;
  189. writel(val, regs + S3C64XX_SPI_CH_CFG);
  190. /* Flush TxFIFO*/
  191. loops = msecs_to_loops(1);
  192. do {
  193. val = readl(regs + S3C64XX_SPI_STATUS);
  194. } while (TX_FIFO_LVL(val, sdd) && loops--);
  195. if (loops == 0)
  196. dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
  197. /* Flush RxFIFO*/
  198. loops = msecs_to_loops(1);
  199. do {
  200. val = readl(regs + S3C64XX_SPI_STATUS);
  201. if (RX_FIFO_LVL(val, sdd))
  202. readl(regs + S3C64XX_SPI_RX_DATA);
  203. else
  204. break;
  205. } while (loops--);
  206. if (loops == 0)
  207. dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
  208. val = readl(regs + S3C64XX_SPI_CH_CFG);
  209. val &= ~S3C64XX_SPI_CH_SW_RST;
  210. writel(val, regs + S3C64XX_SPI_CH_CFG);
  211. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  212. val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  213. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  214. }
  215. static void s3c64xx_spi_dmacb(void *data)
  216. {
  217. struct s3c64xx_spi_driver_data *sdd;
  218. struct s3c64xx_spi_dma_data *dma = data;
  219. unsigned long flags;
  220. if (dma->direction == DMA_DEV_TO_MEM)
  221. sdd = container_of(data,
  222. struct s3c64xx_spi_driver_data, rx_dma);
  223. else
  224. sdd = container_of(data,
  225. struct s3c64xx_spi_driver_data, tx_dma);
  226. spin_lock_irqsave(&sdd->lock, flags);
  227. if (dma->direction == DMA_DEV_TO_MEM) {
  228. sdd->state &= ~RXBUSY;
  229. if (!(sdd->state & TXBUSY))
  230. complete(&sdd->xfer_completion);
  231. } else {
  232. sdd->state &= ~TXBUSY;
  233. if (!(sdd->state & RXBUSY))
  234. complete(&sdd->xfer_completion);
  235. }
  236. spin_unlock_irqrestore(&sdd->lock, flags);
  237. }
  238. static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
  239. struct sg_table *sgt)
  240. {
  241. struct s3c64xx_spi_driver_data *sdd;
  242. struct dma_slave_config config;
  243. struct dma_async_tx_descriptor *desc;
  244. int ret;
  245. memset(&config, 0, sizeof(config));
  246. if (dma->direction == DMA_DEV_TO_MEM) {
  247. sdd = container_of((void *)dma,
  248. struct s3c64xx_spi_driver_data, rx_dma);
  249. config.direction = dma->direction;
  250. config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
  251. config.src_addr_width = sdd->cur_bpw / 8;
  252. config.src_maxburst = 1;
  253. dmaengine_slave_config(dma->ch, &config);
  254. } else {
  255. sdd = container_of((void *)dma,
  256. struct s3c64xx_spi_driver_data, tx_dma);
  257. config.direction = dma->direction;
  258. config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
  259. config.dst_addr_width = sdd->cur_bpw / 8;
  260. config.dst_maxburst = 1;
  261. dmaengine_slave_config(dma->ch, &config);
  262. }
  263. desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
  264. dma->direction, DMA_PREP_INTERRUPT);
  265. if (!desc) {
  266. dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
  267. dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
  268. return -ENOMEM;
  269. }
  270. desc->callback = s3c64xx_spi_dmacb;
  271. desc->callback_param = dma;
  272. dma->cookie = dmaengine_submit(desc);
  273. ret = dma_submit_error(dma->cookie);
  274. if (ret) {
  275. dev_err(&sdd->pdev->dev, "DMA submission failed");
  276. return -EIO;
  277. }
  278. dma_async_issue_pending(dma->ch);
  279. return 0;
  280. }
  281. static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
  282. {
  283. struct s3c64xx_spi_driver_data *sdd =
  284. spi_master_get_devdata(spi->master);
  285. if (sdd->cntrlr_info->no_cs)
  286. return;
  287. if (enable) {
  288. if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
  289. writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
  290. } else {
  291. u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
  292. ssel |= (S3C64XX_SPI_CS_AUTO |
  293. S3C64XX_SPI_CS_NSC_CNT_2);
  294. writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
  295. }
  296. } else {
  297. if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
  298. writel(S3C64XX_SPI_CS_SIG_INACT,
  299. sdd->regs + S3C64XX_SPI_CS_REG);
  300. }
  301. }
  302. static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
  303. {
  304. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  305. if (is_polling(sdd))
  306. return 0;
  307. /* Requests DMA channels */
  308. sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
  309. if (IS_ERR(sdd->rx_dma.ch)) {
  310. dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
  311. sdd->rx_dma.ch = NULL;
  312. return 0;
  313. }
  314. sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
  315. if (IS_ERR(sdd->tx_dma.ch)) {
  316. dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
  317. dma_release_channel(sdd->rx_dma.ch);
  318. sdd->tx_dma.ch = NULL;
  319. sdd->rx_dma.ch = NULL;
  320. return 0;
  321. }
  322. spi->dma_rx = sdd->rx_dma.ch;
  323. spi->dma_tx = sdd->tx_dma.ch;
  324. return 0;
  325. }
  326. static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
  327. {
  328. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  329. if (is_polling(sdd))
  330. return 0;
  331. /* Releases DMA channels if they are allocated */
  332. if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
  333. dma_release_channel(sdd->rx_dma.ch);
  334. dma_release_channel(sdd->tx_dma.ch);
  335. sdd->rx_dma.ch = NULL;
  336. sdd->tx_dma.ch = NULL;
  337. }
  338. return 0;
  339. }
  340. static bool s3c64xx_spi_can_dma(struct spi_master *master,
  341. struct spi_device *spi,
  342. struct spi_transfer *xfer)
  343. {
  344. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  345. if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
  346. return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
  347. } else {
  348. return false;
  349. }
  350. }
  351. static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
  352. struct spi_transfer *xfer, int dma_mode)
  353. {
  354. void __iomem *regs = sdd->regs;
  355. u32 modecfg, chcfg;
  356. int ret = 0;
  357. modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
  358. modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  359. chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
  360. chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
  361. if (dma_mode) {
  362. chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
  363. } else {
  364. /* Always shift in data in FIFO, even if xfer is Tx only,
  365. * this helps setting PCKT_CNT value for generating clocks
  366. * as exactly needed.
  367. */
  368. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  369. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  370. | S3C64XX_SPI_PACKET_CNT_EN,
  371. regs + S3C64XX_SPI_PACKET_CNT);
  372. }
  373. if (xfer->tx_buf != NULL) {
  374. sdd->state |= TXBUSY;
  375. chcfg |= S3C64XX_SPI_CH_TXCH_ON;
  376. if (dma_mode) {
  377. modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
  378. ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
  379. } else {
  380. switch (sdd->cur_bpw) {
  381. case 32:
  382. iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
  383. xfer->tx_buf, xfer->len / 4);
  384. break;
  385. case 16:
  386. iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
  387. xfer->tx_buf, xfer->len / 2);
  388. break;
  389. default:
  390. iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
  391. xfer->tx_buf, xfer->len);
  392. break;
  393. }
  394. }
  395. }
  396. if (xfer->rx_buf != NULL) {
  397. sdd->state |= RXBUSY;
  398. if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
  399. && !(sdd->cur_mode & SPI_CPHA))
  400. chcfg |= S3C64XX_SPI_CH_HS_EN;
  401. if (dma_mode) {
  402. modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
  403. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  404. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  405. | S3C64XX_SPI_PACKET_CNT_EN,
  406. regs + S3C64XX_SPI_PACKET_CNT);
  407. ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
  408. }
  409. }
  410. if (ret)
  411. return ret;
  412. writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
  413. writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
  414. return 0;
  415. }
  416. static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
  417. int timeout_ms)
  418. {
  419. void __iomem *regs = sdd->regs;
  420. unsigned long val = 1;
  421. u32 status;
  422. /* max fifo depth available */
  423. u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
  424. if (timeout_ms)
  425. val = msecs_to_loops(timeout_ms);
  426. do {
  427. status = readl(regs + S3C64XX_SPI_STATUS);
  428. } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
  429. /* return the actual received data length */
  430. return RX_FIFO_LVL(status, sdd);
  431. }
  432. static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
  433. struct spi_transfer *xfer)
  434. {
  435. void __iomem *regs = sdd->regs;
  436. unsigned long val;
  437. u32 status;
  438. int ms;
  439. /* millisecs to xfer 'len' bytes @ 'cur_speed' */
  440. ms = xfer->len * 8 * 1000 / sdd->cur_speed;
  441. ms += 30; /* some tolerance */
  442. ms = max(ms, 100); /* minimum timeout */
  443. val = msecs_to_jiffies(ms) + 10;
  444. val = wait_for_completion_timeout(&sdd->xfer_completion, val);
  445. /*
  446. * If the previous xfer was completed within timeout, then
  447. * proceed further else return -EIO.
  448. * DmaTx returns after simply writing data in the FIFO,
  449. * w/o waiting for real transmission on the bus to finish.
  450. * DmaRx returns only after Dma read data from FIFO which
  451. * needs bus transmission to finish, so we don't worry if
  452. * Xfer involved Rx(with or without Tx).
  453. */
  454. if (val && !xfer->rx_buf) {
  455. val = msecs_to_loops(10);
  456. status = readl(regs + S3C64XX_SPI_STATUS);
  457. while ((TX_FIFO_LVL(status, sdd)
  458. || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
  459. && --val) {
  460. cpu_relax();
  461. status = readl(regs + S3C64XX_SPI_STATUS);
  462. }
  463. }
  464. /* If timed out while checking rx/tx status return error */
  465. if (!val)
  466. return -EIO;
  467. return 0;
  468. }
  469. static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
  470. struct spi_transfer *xfer)
  471. {
  472. void __iomem *regs = sdd->regs;
  473. unsigned long val;
  474. u32 status;
  475. int loops;
  476. u32 cpy_len;
  477. u8 *buf;
  478. int ms;
  479. /* millisecs to xfer 'len' bytes @ 'cur_speed' */
  480. ms = xfer->len * 8 * 1000 / sdd->cur_speed;
  481. ms += 10; /* some tolerance */
  482. val = msecs_to_loops(ms);
  483. do {
  484. status = readl(regs + S3C64XX_SPI_STATUS);
  485. } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
  486. if (!val)
  487. return -EIO;
  488. /* If it was only Tx */
  489. if (!xfer->rx_buf) {
  490. sdd->state &= ~TXBUSY;
  491. return 0;
  492. }
  493. /*
  494. * If the receive length is bigger than the controller fifo
  495. * size, calculate the loops and read the fifo as many times.
  496. * loops = length / max fifo size (calculated by using the
  497. * fifo mask).
  498. * For any size less than the fifo size the below code is
  499. * executed atleast once.
  500. */
  501. loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
  502. buf = xfer->rx_buf;
  503. do {
  504. /* wait for data to be received in the fifo */
  505. cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
  506. (loops ? ms : 0));
  507. switch (sdd->cur_bpw) {
  508. case 32:
  509. ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
  510. buf, cpy_len / 4);
  511. break;
  512. case 16:
  513. ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
  514. buf, cpy_len / 2);
  515. break;
  516. default:
  517. ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
  518. buf, cpy_len);
  519. break;
  520. }
  521. buf = buf + cpy_len;
  522. } while (loops--);
  523. sdd->state &= ~RXBUSY;
  524. return 0;
  525. }
  526. static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
  527. {
  528. void __iomem *regs = sdd->regs;
  529. int ret;
  530. u32 val;
  531. int div = sdd->port_conf->clk_div;
  532. /* Disable Clock */
  533. if (!sdd->port_conf->clk_from_cmu) {
  534. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  535. val &= ~S3C64XX_SPI_ENCLK_ENABLE;
  536. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  537. }
  538. /* Set Polarity and Phase */
  539. val = readl(regs + S3C64XX_SPI_CH_CFG);
  540. val &= ~(S3C64XX_SPI_CH_SLAVE |
  541. S3C64XX_SPI_CPOL_L |
  542. S3C64XX_SPI_CPHA_B);
  543. if (sdd->cur_mode & SPI_CPOL)
  544. val |= S3C64XX_SPI_CPOL_L;
  545. if (sdd->cur_mode & SPI_CPHA)
  546. val |= S3C64XX_SPI_CPHA_B;
  547. writel(val, regs + S3C64XX_SPI_CH_CFG);
  548. /* Set Channel & DMA Mode */
  549. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  550. val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
  551. | S3C64XX_SPI_MODE_CH_TSZ_MASK);
  552. switch (sdd->cur_bpw) {
  553. case 32:
  554. val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
  555. val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
  556. break;
  557. case 16:
  558. val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
  559. val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
  560. break;
  561. default:
  562. val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
  563. val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
  564. break;
  565. }
  566. if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
  567. val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
  568. else
  569. val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK;
  570. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  571. if (sdd->port_conf->clk_from_cmu) {
  572. ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
  573. if (ret)
  574. return ret;
  575. sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
  576. } else {
  577. /* Configure Clock */
  578. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  579. val &= ~S3C64XX_SPI_PSR_MASK;
  580. val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
  581. & S3C64XX_SPI_PSR_MASK);
  582. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  583. /* Enable Clock */
  584. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  585. val |= S3C64XX_SPI_ENCLK_ENABLE;
  586. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  587. }
  588. return 0;
  589. }
  590. #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
  591. static int s3c64xx_spi_prepare_message(struct spi_master *master,
  592. struct spi_message *msg)
  593. {
  594. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  595. struct spi_device *spi = msg->spi;
  596. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  597. /* Configure feedback delay */
  598. if (!cs)
  599. /* No delay if not defined */
  600. writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
  601. else
  602. writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
  603. return 0;
  604. }
  605. static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
  606. {
  607. struct spi_controller *ctlr = spi->controller;
  608. return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
  609. }
  610. static int s3c64xx_spi_transfer_one(struct spi_master *master,
  611. struct spi_device *spi,
  612. struct spi_transfer *xfer)
  613. {
  614. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  615. const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
  616. const void *tx_buf = NULL;
  617. void *rx_buf = NULL;
  618. int target_len = 0, origin_len = 0;
  619. int use_dma = 0;
  620. int status;
  621. u32 speed;
  622. u8 bpw;
  623. unsigned long flags;
  624. reinit_completion(&sdd->xfer_completion);
  625. /* Only BPW and Speed may change across transfers */
  626. bpw = xfer->bits_per_word;
  627. speed = xfer->speed_hz;
  628. if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
  629. sdd->cur_bpw = bpw;
  630. sdd->cur_speed = speed;
  631. sdd->cur_mode = spi->mode;
  632. status = s3c64xx_spi_config(sdd);
  633. if (status)
  634. return status;
  635. }
  636. if (!is_polling(sdd) && (xfer->len > fifo_len) &&
  637. sdd->rx_dma.ch && sdd->tx_dma.ch) {
  638. use_dma = 1;
  639. } else if (xfer->len > fifo_len) {
  640. tx_buf = xfer->tx_buf;
  641. rx_buf = xfer->rx_buf;
  642. origin_len = xfer->len;
  643. target_len = xfer->len;
  644. if (xfer->len > fifo_len)
  645. xfer->len = fifo_len;
  646. }
  647. do {
  648. spin_lock_irqsave(&sdd->lock, flags);
  649. /* Pending only which is to be done */
  650. sdd->state &= ~RXBUSY;
  651. sdd->state &= ~TXBUSY;
  652. /* Start the signals */
  653. s3c64xx_spi_set_cs(spi, true);
  654. status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
  655. spin_unlock_irqrestore(&sdd->lock, flags);
  656. if (status) {
  657. dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
  658. break;
  659. }
  660. if (use_dma)
  661. status = s3c64xx_wait_for_dma(sdd, xfer);
  662. else
  663. status = s3c64xx_wait_for_pio(sdd, xfer);
  664. if (status) {
  665. dev_err(&spi->dev,
  666. "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
  667. xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
  668. (sdd->state & RXBUSY) ? 'f' : 'p',
  669. (sdd->state & TXBUSY) ? 'f' : 'p',
  670. xfer->len, use_dma ? 1 : 0, status);
  671. if (use_dma) {
  672. struct dma_tx_state s;
  673. if (xfer->tx_buf && (sdd->state & TXBUSY)) {
  674. dmaengine_pause(sdd->tx_dma.ch);
  675. dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
  676. dmaengine_terminate_all(sdd->tx_dma.ch);
  677. dev_err(&spi->dev, "TX residue: %d\n", s.residue);
  678. }
  679. if (xfer->rx_buf && (sdd->state & RXBUSY)) {
  680. dmaengine_pause(sdd->rx_dma.ch);
  681. dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
  682. dmaengine_terminate_all(sdd->rx_dma.ch);
  683. dev_err(&spi->dev, "RX residue: %d\n", s.residue);
  684. }
  685. }
  686. } else {
  687. s3c64xx_flush_fifo(sdd);
  688. }
  689. if (target_len > 0) {
  690. target_len -= xfer->len;
  691. if (xfer->tx_buf)
  692. xfer->tx_buf += xfer->len;
  693. if (xfer->rx_buf)
  694. xfer->rx_buf += xfer->len;
  695. if (target_len > fifo_len)
  696. xfer->len = fifo_len;
  697. else
  698. xfer->len = target_len;
  699. }
  700. } while (target_len > 0);
  701. if (origin_len) {
  702. /* Restore original xfer buffers and length */
  703. xfer->tx_buf = tx_buf;
  704. xfer->rx_buf = rx_buf;
  705. xfer->len = origin_len;
  706. }
  707. return status;
  708. }
  709. static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
  710. struct spi_device *spi)
  711. {
  712. struct s3c64xx_spi_csinfo *cs;
  713. struct device_node *slave_np, *data_np = NULL;
  714. u32 fb_delay = 0;
  715. slave_np = spi->dev.of_node;
  716. if (!slave_np) {
  717. dev_err(&spi->dev, "device node not found\n");
  718. return ERR_PTR(-EINVAL);
  719. }
  720. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  721. if (!cs)
  722. return ERR_PTR(-ENOMEM);
  723. data_np = of_get_child_by_name(slave_np, "controller-data");
  724. if (!data_np) {
  725. dev_info(&spi->dev, "feedback delay set to default (0)\n");
  726. return cs;
  727. }
  728. of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
  729. cs->fb_delay = fb_delay;
  730. of_node_put(data_np);
  731. return cs;
  732. }
  733. /*
  734. * Here we only check the validity of requested configuration
  735. * and save the configuration in a local data-structure.
  736. * The controller is actually configured only just before we
  737. * get a message to transfer.
  738. */
  739. static int s3c64xx_spi_setup(struct spi_device *spi)
  740. {
  741. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  742. struct s3c64xx_spi_driver_data *sdd;
  743. int err;
  744. int div;
  745. sdd = spi_master_get_devdata(spi->master);
  746. if (spi->dev.of_node) {
  747. cs = s3c64xx_get_slave_ctrldata(spi);
  748. spi->controller_data = cs;
  749. }
  750. /* NULL is fine, we just avoid using the FB delay (=0) */
  751. if (IS_ERR(cs)) {
  752. dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
  753. return -ENODEV;
  754. }
  755. if (!spi_get_ctldata(spi))
  756. spi_set_ctldata(spi, cs);
  757. pm_runtime_get_sync(&sdd->pdev->dev);
  758. div = sdd->port_conf->clk_div;
  759. /* Check if we can provide the requested rate */
  760. if (!sdd->port_conf->clk_from_cmu) {
  761. u32 psr, speed;
  762. /* Max possible */
  763. speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
  764. if (spi->max_speed_hz > speed)
  765. spi->max_speed_hz = speed;
  766. psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
  767. psr &= S3C64XX_SPI_PSR_MASK;
  768. if (psr == S3C64XX_SPI_PSR_MASK)
  769. psr--;
  770. speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
  771. if (spi->max_speed_hz < speed) {
  772. if (psr+1 < S3C64XX_SPI_PSR_MASK) {
  773. psr++;
  774. } else {
  775. err = -EINVAL;
  776. goto setup_exit;
  777. }
  778. }
  779. speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
  780. if (spi->max_speed_hz >= speed) {
  781. spi->max_speed_hz = speed;
  782. } else {
  783. dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
  784. spi->max_speed_hz);
  785. err = -EINVAL;
  786. goto setup_exit;
  787. }
  788. }
  789. pm_runtime_mark_last_busy(&sdd->pdev->dev);
  790. pm_runtime_put_autosuspend(&sdd->pdev->dev);
  791. s3c64xx_spi_set_cs(spi, false);
  792. return 0;
  793. setup_exit:
  794. pm_runtime_mark_last_busy(&sdd->pdev->dev);
  795. pm_runtime_put_autosuspend(&sdd->pdev->dev);
  796. /* setup() returns with device de-selected */
  797. s3c64xx_spi_set_cs(spi, false);
  798. spi_set_ctldata(spi, NULL);
  799. /* This was dynamically allocated on the DT path */
  800. if (spi->dev.of_node)
  801. kfree(cs);
  802. return err;
  803. }
  804. static void s3c64xx_spi_cleanup(struct spi_device *spi)
  805. {
  806. struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
  807. /* This was dynamically allocated on the DT path */
  808. if (spi->dev.of_node)
  809. kfree(cs);
  810. spi_set_ctldata(spi, NULL);
  811. }
  812. static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
  813. {
  814. struct s3c64xx_spi_driver_data *sdd = data;
  815. struct spi_master *spi = sdd->master;
  816. unsigned int val, clr = 0;
  817. val = readl(sdd->regs + S3C64XX_SPI_STATUS);
  818. if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
  819. clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
  820. dev_err(&spi->dev, "RX overrun\n");
  821. }
  822. if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
  823. clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
  824. dev_err(&spi->dev, "RX underrun\n");
  825. }
  826. if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
  827. clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
  828. dev_err(&spi->dev, "TX overrun\n");
  829. }
  830. if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
  831. clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  832. dev_err(&spi->dev, "TX underrun\n");
  833. }
  834. /* Clear the pending irq by setting and then clearing it */
  835. writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  836. writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  837. return IRQ_HANDLED;
  838. }
  839. static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
  840. {
  841. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  842. void __iomem *regs = sdd->regs;
  843. unsigned int val;
  844. sdd->cur_speed = 0;
  845. if (sci->no_cs)
  846. writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
  847. else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
  848. writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
  849. /* Disable Interrupts - we use Polling if not DMA mode */
  850. writel(0, regs + S3C64XX_SPI_INT_EN);
  851. if (!sdd->port_conf->clk_from_cmu)
  852. writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
  853. regs + S3C64XX_SPI_CLK_CFG);
  854. writel(0, regs + S3C64XX_SPI_MODE_CFG);
  855. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  856. /* Clear any irq pending bits, should set and clear the bits */
  857. val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
  858. S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
  859. S3C64XX_SPI_PND_TX_OVERRUN_CLR |
  860. S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  861. writel(val, regs + S3C64XX_SPI_PENDING_CLR);
  862. writel(0, regs + S3C64XX_SPI_PENDING_CLR);
  863. writel(0, regs + S3C64XX_SPI_SWAP_CFG);
  864. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  865. val &= ~S3C64XX_SPI_MODE_4BURST;
  866. val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  867. val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  868. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  869. s3c64xx_flush_fifo(sdd);
  870. }
  871. #ifdef CONFIG_OF
  872. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  873. {
  874. struct s3c64xx_spi_info *sci;
  875. u32 temp;
  876. sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
  877. if (!sci)
  878. return ERR_PTR(-ENOMEM);
  879. if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
  880. dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
  881. sci->src_clk_nr = 0;
  882. } else {
  883. sci->src_clk_nr = temp;
  884. }
  885. if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
  886. dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
  887. sci->num_cs = 1;
  888. } else {
  889. sci->num_cs = temp;
  890. }
  891. sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
  892. return sci;
  893. }
  894. #else
  895. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  896. {
  897. return dev_get_platdata(dev);
  898. }
  899. #endif
  900. static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
  901. struct platform_device *pdev)
  902. {
  903. #ifdef CONFIG_OF
  904. if (pdev->dev.of_node)
  905. return of_device_get_match_data(&pdev->dev);
  906. #endif
  907. return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
  908. }
  909. static int s3c64xx_spi_probe(struct platform_device *pdev)
  910. {
  911. struct resource *mem_res;
  912. struct s3c64xx_spi_driver_data *sdd;
  913. struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
  914. struct spi_master *master;
  915. int ret, irq;
  916. char clk_name[16];
  917. if (!sci && pdev->dev.of_node) {
  918. sci = s3c64xx_spi_parse_dt(&pdev->dev);
  919. if (IS_ERR(sci))
  920. return PTR_ERR(sci);
  921. }
  922. if (!sci) {
  923. dev_err(&pdev->dev, "platform_data missing!\n");
  924. return -ENODEV;
  925. }
  926. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  927. if (mem_res == NULL) {
  928. dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
  929. return -ENXIO;
  930. }
  931. irq = platform_get_irq(pdev, 0);
  932. if (irq < 0) {
  933. dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
  934. return irq;
  935. }
  936. master = spi_alloc_master(&pdev->dev,
  937. sizeof(struct s3c64xx_spi_driver_data));
  938. if (master == NULL) {
  939. dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
  940. return -ENOMEM;
  941. }
  942. platform_set_drvdata(pdev, master);
  943. sdd = spi_master_get_devdata(master);
  944. sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
  945. sdd->master = master;
  946. sdd->cntrlr_info = sci;
  947. sdd->pdev = pdev;
  948. sdd->sfr_start = mem_res->start;
  949. if (pdev->dev.of_node) {
  950. ret = of_alias_get_id(pdev->dev.of_node, "spi");
  951. if (ret < 0) {
  952. dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
  953. ret);
  954. goto err_deref_master;
  955. }
  956. sdd->port_id = ret;
  957. } else {
  958. sdd->port_id = pdev->id;
  959. }
  960. sdd->cur_bpw = 8;
  961. sdd->tx_dma.direction = DMA_MEM_TO_DEV;
  962. sdd->rx_dma.direction = DMA_DEV_TO_MEM;
  963. master->dev.of_node = pdev->dev.of_node;
  964. master->bus_num = sdd->port_id;
  965. master->setup = s3c64xx_spi_setup;
  966. master->cleanup = s3c64xx_spi_cleanup;
  967. master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
  968. master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
  969. master->prepare_message = s3c64xx_spi_prepare_message;
  970. master->transfer_one = s3c64xx_spi_transfer_one;
  971. master->max_transfer_size = s3c64xx_spi_max_transfer_size;
  972. master->num_chipselect = sci->num_cs;
  973. master->use_gpio_descriptors = true;
  974. master->dma_alignment = 8;
  975. master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
  976. SPI_BPW_MASK(8);
  977. /* the spi->mode bits understood by this driver: */
  978. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  979. if (sdd->port_conf->has_loopback)
  980. master->mode_bits |= SPI_LOOP;
  981. master->auto_runtime_pm = true;
  982. if (!is_polling(sdd))
  983. master->can_dma = s3c64xx_spi_can_dma;
  984. sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
  985. if (IS_ERR(sdd->regs)) {
  986. ret = PTR_ERR(sdd->regs);
  987. goto err_deref_master;
  988. }
  989. if (sci->cfg_gpio && sci->cfg_gpio()) {
  990. dev_err(&pdev->dev, "Unable to config gpio\n");
  991. ret = -EBUSY;
  992. goto err_deref_master;
  993. }
  994. /* Setup clocks */
  995. sdd->clk = devm_clk_get(&pdev->dev, "spi");
  996. if (IS_ERR(sdd->clk)) {
  997. dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
  998. ret = PTR_ERR(sdd->clk);
  999. goto err_deref_master;
  1000. }
  1001. ret = clk_prepare_enable(sdd->clk);
  1002. if (ret) {
  1003. dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
  1004. goto err_deref_master;
  1005. }
  1006. sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
  1007. sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
  1008. if (IS_ERR(sdd->src_clk)) {
  1009. dev_err(&pdev->dev,
  1010. "Unable to acquire clock '%s'\n", clk_name);
  1011. ret = PTR_ERR(sdd->src_clk);
  1012. goto err_disable_clk;
  1013. }
  1014. ret = clk_prepare_enable(sdd->src_clk);
  1015. if (ret) {
  1016. dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
  1017. goto err_disable_clk;
  1018. }
  1019. if (sdd->port_conf->clk_ioclk) {
  1020. sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
  1021. if (IS_ERR(sdd->ioclk)) {
  1022. dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
  1023. ret = PTR_ERR(sdd->ioclk);
  1024. goto err_disable_src_clk;
  1025. }
  1026. ret = clk_prepare_enable(sdd->ioclk);
  1027. if (ret) {
  1028. dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
  1029. goto err_disable_src_clk;
  1030. }
  1031. }
  1032. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
  1033. pm_runtime_use_autosuspend(&pdev->dev);
  1034. pm_runtime_set_active(&pdev->dev);
  1035. pm_runtime_enable(&pdev->dev);
  1036. pm_runtime_get_sync(&pdev->dev);
  1037. /* Setup Deufult Mode */
  1038. s3c64xx_spi_hwinit(sdd);
  1039. spin_lock_init(&sdd->lock);
  1040. init_completion(&sdd->xfer_completion);
  1041. ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
  1042. "spi-s3c64xx", sdd);
  1043. if (ret != 0) {
  1044. dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
  1045. irq, ret);
  1046. goto err_pm_put;
  1047. }
  1048. writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
  1049. S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
  1050. sdd->regs + S3C64XX_SPI_INT_EN);
  1051. ret = devm_spi_register_master(&pdev->dev, master);
  1052. if (ret != 0) {
  1053. dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
  1054. goto err_pm_put;
  1055. }
  1056. dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
  1057. sdd->port_id, master->num_chipselect);
  1058. dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
  1059. mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
  1060. pm_runtime_mark_last_busy(&pdev->dev);
  1061. pm_runtime_put_autosuspend(&pdev->dev);
  1062. return 0;
  1063. err_pm_put:
  1064. pm_runtime_put_noidle(&pdev->dev);
  1065. pm_runtime_disable(&pdev->dev);
  1066. pm_runtime_set_suspended(&pdev->dev);
  1067. clk_disable_unprepare(sdd->ioclk);
  1068. err_disable_src_clk:
  1069. clk_disable_unprepare(sdd->src_clk);
  1070. err_disable_clk:
  1071. clk_disable_unprepare(sdd->clk);
  1072. err_deref_master:
  1073. spi_master_put(master);
  1074. return ret;
  1075. }
  1076. static int s3c64xx_spi_remove(struct platform_device *pdev)
  1077. {
  1078. struct spi_master *master = platform_get_drvdata(pdev);
  1079. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1080. pm_runtime_get_sync(&pdev->dev);
  1081. writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
  1082. if (!is_polling(sdd)) {
  1083. dma_release_channel(sdd->rx_dma.ch);
  1084. dma_release_channel(sdd->tx_dma.ch);
  1085. }
  1086. clk_disable_unprepare(sdd->ioclk);
  1087. clk_disable_unprepare(sdd->src_clk);
  1088. clk_disable_unprepare(sdd->clk);
  1089. pm_runtime_put_noidle(&pdev->dev);
  1090. pm_runtime_disable(&pdev->dev);
  1091. pm_runtime_set_suspended(&pdev->dev);
  1092. return 0;
  1093. }
  1094. #ifdef CONFIG_PM_SLEEP
  1095. static int s3c64xx_spi_suspend(struct device *dev)
  1096. {
  1097. struct spi_master *master = dev_get_drvdata(dev);
  1098. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1099. int ret = spi_master_suspend(master);
  1100. if (ret)
  1101. return ret;
  1102. ret = pm_runtime_force_suspend(dev);
  1103. if (ret < 0)
  1104. return ret;
  1105. sdd->cur_speed = 0; /* Output Clock is stopped */
  1106. return 0;
  1107. }
  1108. static int s3c64xx_spi_resume(struct device *dev)
  1109. {
  1110. struct spi_master *master = dev_get_drvdata(dev);
  1111. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1112. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  1113. int ret;
  1114. if (sci->cfg_gpio)
  1115. sci->cfg_gpio();
  1116. ret = pm_runtime_force_resume(dev);
  1117. if (ret < 0)
  1118. return ret;
  1119. return spi_master_resume(master);
  1120. }
  1121. #endif /* CONFIG_PM_SLEEP */
  1122. #ifdef CONFIG_PM
  1123. static int s3c64xx_spi_runtime_suspend(struct device *dev)
  1124. {
  1125. struct spi_master *master = dev_get_drvdata(dev);
  1126. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1127. clk_disable_unprepare(sdd->clk);
  1128. clk_disable_unprepare(sdd->src_clk);
  1129. clk_disable_unprepare(sdd->ioclk);
  1130. return 0;
  1131. }
  1132. static int s3c64xx_spi_runtime_resume(struct device *dev)
  1133. {
  1134. struct spi_master *master = dev_get_drvdata(dev);
  1135. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1136. int ret;
  1137. if (sdd->port_conf->clk_ioclk) {
  1138. ret = clk_prepare_enable(sdd->ioclk);
  1139. if (ret != 0)
  1140. return ret;
  1141. }
  1142. ret = clk_prepare_enable(sdd->src_clk);
  1143. if (ret != 0)
  1144. goto err_disable_ioclk;
  1145. ret = clk_prepare_enable(sdd->clk);
  1146. if (ret != 0)
  1147. goto err_disable_src_clk;
  1148. s3c64xx_spi_hwinit(sdd);
  1149. writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
  1150. S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
  1151. sdd->regs + S3C64XX_SPI_INT_EN);
  1152. return 0;
  1153. err_disable_src_clk:
  1154. clk_disable_unprepare(sdd->src_clk);
  1155. err_disable_ioclk:
  1156. clk_disable_unprepare(sdd->ioclk);
  1157. return ret;
  1158. }
  1159. #endif /* CONFIG_PM */
  1160. static const struct dev_pm_ops s3c64xx_spi_pm = {
  1161. SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
  1162. SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
  1163. s3c64xx_spi_runtime_resume, NULL)
  1164. };
  1165. static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
  1166. .fifo_lvl_mask = { 0x7f },
  1167. .rx_lvl_offset = 13,
  1168. .tx_st_done = 21,
  1169. .clk_div = 2,
  1170. .high_speed = true,
  1171. };
  1172. static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
  1173. .fifo_lvl_mask = { 0x7f, 0x7F },
  1174. .rx_lvl_offset = 13,
  1175. .tx_st_done = 21,
  1176. .clk_div = 2,
  1177. };
  1178. static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
  1179. .fifo_lvl_mask = { 0x1ff, 0x7F },
  1180. .rx_lvl_offset = 15,
  1181. .tx_st_done = 25,
  1182. .clk_div = 2,
  1183. .high_speed = true,
  1184. };
  1185. static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
  1186. .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
  1187. .rx_lvl_offset = 15,
  1188. .tx_st_done = 25,
  1189. .clk_div = 2,
  1190. .high_speed = true,
  1191. .clk_from_cmu = true,
  1192. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1193. };
  1194. static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
  1195. .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
  1196. .rx_lvl_offset = 15,
  1197. .tx_st_done = 25,
  1198. .clk_div = 2,
  1199. .high_speed = true,
  1200. .clk_from_cmu = true,
  1201. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1202. };
  1203. static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
  1204. .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
  1205. .rx_lvl_offset = 15,
  1206. .tx_st_done = 25,
  1207. .clk_div = 2,
  1208. .high_speed = true,
  1209. .clk_from_cmu = true,
  1210. .clk_ioclk = true,
  1211. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1212. };
  1213. static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
  1214. .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
  1215. 0x7f, 0x7f, 0x7f, 0x7f},
  1216. .rx_lvl_offset = 15,
  1217. .tx_st_done = 25,
  1218. .clk_div = 4,
  1219. .high_speed = true,
  1220. .clk_from_cmu = true,
  1221. .clk_ioclk = true,
  1222. .has_loopback = true,
  1223. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1224. };
  1225. static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
  1226. .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
  1227. .rx_lvl_offset = 15,
  1228. .tx_st_done = 25,
  1229. .clk_div = 2,
  1230. .high_speed = true,
  1231. .clk_from_cmu = true,
  1232. .clk_ioclk = false,
  1233. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1234. };
  1235. static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
  1236. {
  1237. .name = "s3c2443-spi",
  1238. .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
  1239. }, {
  1240. .name = "s3c6410-spi",
  1241. .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
  1242. },
  1243. { },
  1244. };
  1245. static const struct of_device_id s3c64xx_spi_dt_match[] = {
  1246. { .compatible = "samsung,s3c2443-spi",
  1247. .data = (void *)&s3c2443_spi_port_config,
  1248. },
  1249. { .compatible = "samsung,s3c6410-spi",
  1250. .data = (void *)&s3c6410_spi_port_config,
  1251. },
  1252. { .compatible = "samsung,s5pv210-spi",
  1253. .data = (void *)&s5pv210_spi_port_config,
  1254. },
  1255. { .compatible = "samsung,exynos4210-spi",
  1256. .data = (void *)&exynos4_spi_port_config,
  1257. },
  1258. { .compatible = "samsung,exynos7-spi",
  1259. .data = (void *)&exynos7_spi_port_config,
  1260. },
  1261. { .compatible = "samsung,exynos5433-spi",
  1262. .data = (void *)&exynos5433_spi_port_config,
  1263. },
  1264. { .compatible = "samsung,exynosautov9-spi",
  1265. .data = (void *)&exynosautov9_spi_port_config,
  1266. },
  1267. { .compatible = "tesla,fsd-spi",
  1268. .data = (void *)&fsd_spi_port_config,
  1269. },
  1270. { },
  1271. };
  1272. MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
  1273. static struct platform_driver s3c64xx_spi_driver = {
  1274. .driver = {
  1275. .name = "s3c64xx-spi",
  1276. .pm = &s3c64xx_spi_pm,
  1277. .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
  1278. },
  1279. .probe = s3c64xx_spi_probe,
  1280. .remove = s3c64xx_spi_remove,
  1281. .id_table = s3c64xx_spi_driver_ids,
  1282. };
  1283. MODULE_ALIAS("platform:s3c64xx-spi");
  1284. module_platform_driver(s3c64xx_spi_driver);
  1285. MODULE_AUTHOR("Jaswinder Singh <[email protected]>");
  1286. MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
  1287. MODULE_LICENSE("GPL");