spi-pxa2xx.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  4. * Copyright (C) 2013, 2021 Intel Corporation
  5. */
  6. #ifndef SPI_PXA2XX_H
  7. #define SPI_PXA2XX_H
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/types.h>
  11. #include <linux/sizes.h>
  12. #include <linux/pxa2xx_ssp.h>
  13. struct gpio_desc;
  14. struct pxa2xx_spi_controller;
  15. struct spi_controller;
  16. struct spi_device;
  17. struct spi_transfer;
  18. struct driver_data {
  19. /* SSP Info */
  20. struct ssp_device *ssp;
  21. /* SPI framework hookup */
  22. enum pxa_ssp_type ssp_type;
  23. struct spi_controller *controller;
  24. /* PXA hookup */
  25. struct pxa2xx_spi_controller *controller_info;
  26. /* SSP masks*/
  27. u32 dma_cr1;
  28. u32 int_cr1;
  29. u32 clear_sr;
  30. u32 mask_sr;
  31. /* DMA engine support */
  32. atomic_t dma_running;
  33. /* Current transfer state info */
  34. void *tx;
  35. void *tx_end;
  36. void *rx;
  37. void *rx_end;
  38. u8 n_bytes;
  39. int (*write)(struct driver_data *drv_data);
  40. int (*read)(struct driver_data *drv_data);
  41. irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  42. void __iomem *lpss_base;
  43. /* Optional slave FIFO ready signal */
  44. struct gpio_desc *gpiod_ready;
  45. };
  46. struct chip_data {
  47. u32 cr1;
  48. u32 dds_rate;
  49. u32 timeout;
  50. u8 enable_dma;
  51. u32 dma_burst_size;
  52. u32 dma_threshold;
  53. u32 threshold;
  54. u16 lpss_rx_threshold;
  55. u16 lpss_tx_threshold;
  56. };
  57. static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
  58. {
  59. return pxa_ssp_read_reg(drv_data->ssp, reg);
  60. }
  61. static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
  62. {
  63. pxa_ssp_write_reg(drv_data->ssp, reg, val);
  64. }
  65. #define DMA_ALIGNMENT 8
  66. static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
  67. {
  68. switch (drv_data->ssp_type) {
  69. case PXA25x_SSP:
  70. case CE4100_SSP:
  71. case QUARK_X1000_SSP:
  72. return 1;
  73. default:
  74. return 0;
  75. }
  76. }
  77. static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
  78. {
  79. pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
  80. }
  81. static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
  82. {
  83. return pxa2xx_spi_read(drv_data, SSSR) & bits;
  84. }
  85. static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
  86. {
  87. if (drv_data->ssp_type == CE4100_SSP ||
  88. drv_data->ssp_type == QUARK_X1000_SSP)
  89. val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
  90. pxa2xx_spi_write(drv_data, SSSR, val);
  91. }
  92. extern int pxa2xx_spi_flush(struct driver_data *drv_data);
  93. #define MAX_DMA_LEN SZ_64K
  94. #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
  95. extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
  96. extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
  97. struct spi_transfer *xfer);
  98. extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
  99. extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
  100. extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
  101. extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
  102. extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
  103. struct spi_device *spi,
  104. u8 bits_per_word,
  105. u32 *burst_code,
  106. u32 *threshold);
  107. #endif /* SPI_PXA2XX_H */