spi-pxa2xx-dma.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PXA2xx SPI DMA engine support.
  4. *
  5. * Copyright (C) 2013, 2021 Intel Corporation
  6. * Author: Mika Westerberg <[email protected]>
  7. */
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/sizes.h>
  13. #include <linux/spi/pxa2xx_spi.h>
  14. #include <linux/spi/spi.h>
  15. #include "spi-pxa2xx.h"
  16. static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
  17. bool error)
  18. {
  19. struct spi_message *msg = drv_data->controller->cur_msg;
  20. /*
  21. * It is possible that one CPU is handling ROR interrupt and other
  22. * just gets DMA completion. Calling pump_transfers() twice for the
  23. * same transfer leads to problems thus we prevent concurrent calls
  24. * by using dma_running.
  25. */
  26. if (atomic_dec_and_test(&drv_data->dma_running)) {
  27. /*
  28. * If the other CPU is still handling the ROR interrupt we
  29. * might not know about the error yet. So we re-check the
  30. * ROR bit here before we clear the status register.
  31. */
  32. if (!error)
  33. error = read_SSSR_bits(drv_data, drv_data->mask_sr) & SSSR_ROR;
  34. /* Clear status & disable interrupts */
  35. clear_SSCR1_bits(drv_data, drv_data->dma_cr1);
  36. write_SSSR_CS(drv_data, drv_data->clear_sr);
  37. if (!pxa25x_ssp_comp(drv_data))
  38. pxa2xx_spi_write(drv_data, SSTO, 0);
  39. if (error) {
  40. /* In case we got an error we disable the SSP now */
  41. pxa_ssp_disable(drv_data->ssp);
  42. msg->status = -EIO;
  43. }
  44. spi_finalize_current_transfer(drv_data->controller);
  45. }
  46. }
  47. static void pxa2xx_spi_dma_callback(void *data)
  48. {
  49. pxa2xx_spi_dma_transfer_complete(data, false);
  50. }
  51. static struct dma_async_tx_descriptor *
  52. pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
  53. enum dma_transfer_direction dir,
  54. struct spi_transfer *xfer)
  55. {
  56. struct chip_data *chip =
  57. spi_get_ctldata(drv_data->controller->cur_msg->spi);
  58. enum dma_slave_buswidth width;
  59. struct dma_slave_config cfg;
  60. struct dma_chan *chan;
  61. struct sg_table *sgt;
  62. int ret;
  63. switch (drv_data->n_bytes) {
  64. case 1:
  65. width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  66. break;
  67. case 2:
  68. width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  69. break;
  70. default:
  71. width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  72. break;
  73. }
  74. memset(&cfg, 0, sizeof(cfg));
  75. cfg.direction = dir;
  76. if (dir == DMA_MEM_TO_DEV) {
  77. cfg.dst_addr = drv_data->ssp->phys_base + SSDR;
  78. cfg.dst_addr_width = width;
  79. cfg.dst_maxburst = chip->dma_burst_size;
  80. sgt = &xfer->tx_sg;
  81. chan = drv_data->controller->dma_tx;
  82. } else {
  83. cfg.src_addr = drv_data->ssp->phys_base + SSDR;
  84. cfg.src_addr_width = width;
  85. cfg.src_maxburst = chip->dma_burst_size;
  86. sgt = &xfer->rx_sg;
  87. chan = drv_data->controller->dma_rx;
  88. }
  89. ret = dmaengine_slave_config(chan, &cfg);
  90. if (ret) {
  91. dev_warn(drv_data->ssp->dev, "DMA slave config failed\n");
  92. return NULL;
  93. }
  94. return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
  95. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  96. }
  97. irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
  98. {
  99. u32 status;
  100. status = read_SSSR_bits(drv_data, drv_data->mask_sr);
  101. if (status & SSSR_ROR) {
  102. dev_err(drv_data->ssp->dev, "FIFO overrun\n");
  103. dmaengine_terminate_async(drv_data->controller->dma_rx);
  104. dmaengine_terminate_async(drv_data->controller->dma_tx);
  105. pxa2xx_spi_dma_transfer_complete(drv_data, true);
  106. return IRQ_HANDLED;
  107. }
  108. return IRQ_NONE;
  109. }
  110. int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
  111. struct spi_transfer *xfer)
  112. {
  113. struct dma_async_tx_descriptor *tx_desc, *rx_desc;
  114. int err;
  115. tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer);
  116. if (!tx_desc) {
  117. dev_err(drv_data->ssp->dev, "failed to get DMA TX descriptor\n");
  118. err = -EBUSY;
  119. goto err_tx;
  120. }
  121. rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer);
  122. if (!rx_desc) {
  123. dev_err(drv_data->ssp->dev, "failed to get DMA RX descriptor\n");
  124. err = -EBUSY;
  125. goto err_rx;
  126. }
  127. /* We are ready when RX completes */
  128. rx_desc->callback = pxa2xx_spi_dma_callback;
  129. rx_desc->callback_param = drv_data;
  130. dmaengine_submit(rx_desc);
  131. dmaengine_submit(tx_desc);
  132. return 0;
  133. err_rx:
  134. dmaengine_terminate_async(drv_data->controller->dma_tx);
  135. err_tx:
  136. return err;
  137. }
  138. void pxa2xx_spi_dma_start(struct driver_data *drv_data)
  139. {
  140. dma_async_issue_pending(drv_data->controller->dma_rx);
  141. dma_async_issue_pending(drv_data->controller->dma_tx);
  142. atomic_set(&drv_data->dma_running, 1);
  143. }
  144. void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
  145. {
  146. atomic_set(&drv_data->dma_running, 0);
  147. dmaengine_terminate_sync(drv_data->controller->dma_rx);
  148. dmaengine_terminate_sync(drv_data->controller->dma_tx);
  149. }
  150. int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
  151. {
  152. struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
  153. struct spi_controller *controller = drv_data->controller;
  154. struct device *dev = drv_data->ssp->dev;
  155. dma_cap_mask_t mask;
  156. dma_cap_zero(mask);
  157. dma_cap_set(DMA_SLAVE, mask);
  158. controller->dma_tx = dma_request_slave_channel_compat(mask,
  159. pdata->dma_filter, pdata->tx_param, dev, "tx");
  160. if (!controller->dma_tx)
  161. return -ENODEV;
  162. controller->dma_rx = dma_request_slave_channel_compat(mask,
  163. pdata->dma_filter, pdata->rx_param, dev, "rx");
  164. if (!controller->dma_rx) {
  165. dma_release_channel(controller->dma_tx);
  166. controller->dma_tx = NULL;
  167. return -ENODEV;
  168. }
  169. return 0;
  170. }
  171. void pxa2xx_spi_dma_release(struct driver_data *drv_data)
  172. {
  173. struct spi_controller *controller = drv_data->controller;
  174. if (controller->dma_rx) {
  175. dmaengine_terminate_sync(controller->dma_rx);
  176. dma_release_channel(controller->dma_rx);
  177. controller->dma_rx = NULL;
  178. }
  179. if (controller->dma_tx) {
  180. dmaengine_terminate_sync(controller->dma_tx);
  181. dma_release_channel(controller->dma_tx);
  182. controller->dma_tx = NULL;
  183. }
  184. }
  185. int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
  186. struct spi_device *spi,
  187. u8 bits_per_word, u32 *burst_code,
  188. u32 *threshold)
  189. {
  190. struct pxa2xx_spi_chip *chip_info = spi->controller_data;
  191. struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
  192. u32 dma_burst_size = drv_data->controller_info->dma_burst_size;
  193. /*
  194. * If the DMA burst size is given in chip_info we use that,
  195. * otherwise we use the default. Also we use the default FIFO
  196. * thresholds for now.
  197. */
  198. *burst_code = chip_info ? chip_info->dma_burst_size : dma_burst_size;
  199. *threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
  200. | SSCR1_TxTresh(TX_THRESH_DFLT);
  201. return 0;
  202. }