spi-pl022.c 67 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
  4. *
  5. * Copyright (C) 2008-2012 ST-Ericsson AB
  6. * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  7. *
  8. * Author: Linus Walleij <[email protected]>
  9. *
  10. * Initial version inspired by:
  11. * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  12. * Initial adoption to PL022 by:
  13. * Sachin Verma <[email protected]>
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/device.h>
  18. #include <linux/ioport.h>
  19. #include <linux/errno.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/delay.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/amba/bus.h>
  26. #include <linux/amba/pl022.h>
  27. #include <linux/io.h>
  28. #include <linux/slab.h>
  29. #include <linux/dmaengine.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/scatterlist.h>
  32. #include <linux/pm_runtime.h>
  33. #include <linux/of.h>
  34. #include <linux/pinctrl/consumer.h>
  35. /*
  36. * This macro is used to define some register default values.
  37. * reg is masked with mask, the OR:ed with an (again masked)
  38. * val shifted sb steps to the left.
  39. */
  40. #define SSP_WRITE_BITS(reg, val, mask, sb) \
  41. ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
  42. /*
  43. * This macro is also used to define some default values.
  44. * It will just shift val by sb steps to the left and mask
  45. * the result with mask.
  46. */
  47. #define GEN_MASK_BITS(val, mask, sb) \
  48. (((val)<<(sb)) & (mask))
  49. #define DRIVE_TX 0
  50. #define DO_NOT_DRIVE_TX 1
  51. #define DO_NOT_QUEUE_DMA 0
  52. #define QUEUE_DMA 1
  53. #define RX_TRANSFER 1
  54. #define TX_TRANSFER 2
  55. /*
  56. * Macros to access SSP Registers with their offsets
  57. */
  58. #define SSP_CR0(r) (r + 0x000)
  59. #define SSP_CR1(r) (r + 0x004)
  60. #define SSP_DR(r) (r + 0x008)
  61. #define SSP_SR(r) (r + 0x00C)
  62. #define SSP_CPSR(r) (r + 0x010)
  63. #define SSP_IMSC(r) (r + 0x014)
  64. #define SSP_RIS(r) (r + 0x018)
  65. #define SSP_MIS(r) (r + 0x01C)
  66. #define SSP_ICR(r) (r + 0x020)
  67. #define SSP_DMACR(r) (r + 0x024)
  68. #define SSP_CSR(r) (r + 0x030) /* vendor extension */
  69. #define SSP_ITCR(r) (r + 0x080)
  70. #define SSP_ITIP(r) (r + 0x084)
  71. #define SSP_ITOP(r) (r + 0x088)
  72. #define SSP_TDR(r) (r + 0x08C)
  73. #define SSP_PID0(r) (r + 0xFE0)
  74. #define SSP_PID1(r) (r + 0xFE4)
  75. #define SSP_PID2(r) (r + 0xFE8)
  76. #define SSP_PID3(r) (r + 0xFEC)
  77. #define SSP_CID0(r) (r + 0xFF0)
  78. #define SSP_CID1(r) (r + 0xFF4)
  79. #define SSP_CID2(r) (r + 0xFF8)
  80. #define SSP_CID3(r) (r + 0xFFC)
  81. /*
  82. * SSP Control Register 0 - SSP_CR0
  83. */
  84. #define SSP_CR0_MASK_DSS (0x0FUL << 0)
  85. #define SSP_CR0_MASK_FRF (0x3UL << 4)
  86. #define SSP_CR0_MASK_SPO (0x1UL << 6)
  87. #define SSP_CR0_MASK_SPH (0x1UL << 7)
  88. #define SSP_CR0_MASK_SCR (0xFFUL << 8)
  89. /*
  90. * The ST version of this block moves som bits
  91. * in SSP_CR0 and extends it to 32 bits
  92. */
  93. #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
  94. #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
  95. #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
  96. #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
  97. /*
  98. * SSP Control Register 0 - SSP_CR1
  99. */
  100. #define SSP_CR1_MASK_LBM (0x1UL << 0)
  101. #define SSP_CR1_MASK_SSE (0x1UL << 1)
  102. #define SSP_CR1_MASK_MS (0x1UL << 2)
  103. #define SSP_CR1_MASK_SOD (0x1UL << 3)
  104. /*
  105. * The ST version of this block adds some bits
  106. * in SSP_CR1
  107. */
  108. #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
  109. #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
  110. #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
  111. #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
  112. #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
  113. /* This one is only in the PL023 variant */
  114. #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
  115. /*
  116. * SSP Status Register - SSP_SR
  117. */
  118. #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
  119. #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
  120. #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
  121. #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
  122. #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
  123. /*
  124. * SSP Clock Prescale Register - SSP_CPSR
  125. */
  126. #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
  127. /*
  128. * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
  129. */
  130. #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
  131. #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
  132. #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
  133. #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
  134. /*
  135. * SSP Raw Interrupt Status Register - SSP_RIS
  136. */
  137. /* Receive Overrun Raw Interrupt status */
  138. #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
  139. /* Receive Timeout Raw Interrupt status */
  140. #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
  141. /* Receive FIFO Raw Interrupt status */
  142. #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
  143. /* Transmit FIFO Raw Interrupt status */
  144. #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
  145. /*
  146. * SSP Masked Interrupt Status Register - SSP_MIS
  147. */
  148. /* Receive Overrun Masked Interrupt status */
  149. #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
  150. /* Receive Timeout Masked Interrupt status */
  151. #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
  152. /* Receive FIFO Masked Interrupt status */
  153. #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
  154. /* Transmit FIFO Masked Interrupt status */
  155. #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
  156. /*
  157. * SSP Interrupt Clear Register - SSP_ICR
  158. */
  159. /* Receive Overrun Raw Clear Interrupt bit */
  160. #define SSP_ICR_MASK_RORIC (0x1UL << 0)
  161. /* Receive Timeout Clear Interrupt bit */
  162. #define SSP_ICR_MASK_RTIC (0x1UL << 1)
  163. /*
  164. * SSP DMA Control Register - SSP_DMACR
  165. */
  166. /* Receive DMA Enable bit */
  167. #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
  168. /* Transmit DMA Enable bit */
  169. #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
  170. /*
  171. * SSP Chip Select Control Register - SSP_CSR
  172. * (vendor extension)
  173. */
  174. #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0)
  175. /*
  176. * SSP Integration Test control Register - SSP_ITCR
  177. */
  178. #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
  179. #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
  180. /*
  181. * SSP Integration Test Input Register - SSP_ITIP
  182. */
  183. #define ITIP_MASK_SSPRXD (0x1UL << 0)
  184. #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
  185. #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
  186. #define ITIP_MASK_RXDMAC (0x1UL << 3)
  187. #define ITIP_MASK_TXDMAC (0x1UL << 4)
  188. #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
  189. /*
  190. * SSP Integration Test output Register - SSP_ITOP
  191. */
  192. #define ITOP_MASK_SSPTXD (0x1UL << 0)
  193. #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
  194. #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
  195. #define ITOP_MASK_SSPOEn (0x1UL << 3)
  196. #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
  197. #define ITOP_MASK_RORINTR (0x1UL << 5)
  198. #define ITOP_MASK_RTINTR (0x1UL << 6)
  199. #define ITOP_MASK_RXINTR (0x1UL << 7)
  200. #define ITOP_MASK_TXINTR (0x1UL << 8)
  201. #define ITOP_MASK_INTR (0x1UL << 9)
  202. #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
  203. #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
  204. #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
  205. #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
  206. /*
  207. * SSP Test Data Register - SSP_TDR
  208. */
  209. #define TDR_MASK_TESTDATA (0xFFFFFFFF)
  210. /*
  211. * Message State
  212. * we use the spi_message.state (void *) pointer to
  213. * hold a single state value, that's why all this
  214. * (void *) casting is done here.
  215. */
  216. #define STATE_START ((void *) 0)
  217. #define STATE_RUNNING ((void *) 1)
  218. #define STATE_DONE ((void *) 2)
  219. #define STATE_ERROR ((void *) -1)
  220. #define STATE_TIMEOUT ((void *) -2)
  221. /*
  222. * SSP State - Whether Enabled or Disabled
  223. */
  224. #define SSP_DISABLED (0)
  225. #define SSP_ENABLED (1)
  226. /*
  227. * SSP DMA State - Whether DMA Enabled or Disabled
  228. */
  229. #define SSP_DMA_DISABLED (0)
  230. #define SSP_DMA_ENABLED (1)
  231. /*
  232. * SSP Clock Defaults
  233. */
  234. #define SSP_DEFAULT_CLKRATE 0x2
  235. #define SSP_DEFAULT_PRESCALE 0x40
  236. /*
  237. * SSP Clock Parameter ranges
  238. */
  239. #define CPSDVR_MIN 0x02
  240. #define CPSDVR_MAX 0xFE
  241. #define SCR_MIN 0x00
  242. #define SCR_MAX 0xFF
  243. /*
  244. * SSP Interrupt related Macros
  245. */
  246. #define DEFAULT_SSP_REG_IMSC 0x0UL
  247. #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
  248. #define ENABLE_ALL_INTERRUPTS ( \
  249. SSP_IMSC_MASK_RORIM | \
  250. SSP_IMSC_MASK_RTIM | \
  251. SSP_IMSC_MASK_RXIM | \
  252. SSP_IMSC_MASK_TXIM \
  253. )
  254. #define CLEAR_ALL_INTERRUPTS 0x3
  255. #define SPI_POLLING_TIMEOUT 1000
  256. /*
  257. * The type of reading going on this chip
  258. */
  259. enum ssp_reading {
  260. READING_NULL,
  261. READING_U8,
  262. READING_U16,
  263. READING_U32
  264. };
  265. /*
  266. * The type of writing going on this chip
  267. */
  268. enum ssp_writing {
  269. WRITING_NULL,
  270. WRITING_U8,
  271. WRITING_U16,
  272. WRITING_U32
  273. };
  274. /**
  275. * struct vendor_data - vendor-specific config parameters
  276. * for PL022 derivates
  277. * @fifodepth: depth of FIFOs (both)
  278. * @max_bpw: maximum number of bits per word
  279. * @unidir: supports unidirection transfers
  280. * @extended_cr: 32 bit wide control register 0 with extra
  281. * features and extra features in CR1 as found in the ST variants
  282. * @pl023: supports a subset of the ST extensions called "PL023"
  283. * @loopback: supports loopback mode
  284. * @internal_cs_ctrl: supports chip select control register
  285. */
  286. struct vendor_data {
  287. int fifodepth;
  288. int max_bpw;
  289. bool unidir;
  290. bool extended_cr;
  291. bool pl023;
  292. bool loopback;
  293. bool internal_cs_ctrl;
  294. };
  295. /**
  296. * struct pl022 - This is the private SSP driver data structure
  297. * @adev: AMBA device model hookup
  298. * @vendor: vendor data for the IP block
  299. * @phybase: the physical memory where the SSP device resides
  300. * @virtbase: the virtual memory where the SSP is mapped
  301. * @clk: outgoing clock "SPICLK" for the SPI bus
  302. * @master: SPI framework hookup
  303. * @master_info: controller-specific data from machine setup
  304. * @pump_transfers: Tasklet used in Interrupt Transfer mode
  305. * @cur_msg: Pointer to current spi_message being processed
  306. * @cur_transfer: Pointer to current spi_transfer
  307. * @cur_chip: pointer to current clients chip(assigned from controller_state)
  308. * @next_msg_cs_active: the next message in the queue has been examined
  309. * and it was found that it uses the same chip select as the previous
  310. * message, so we left it active after the previous transfer, and it's
  311. * active already.
  312. * @tx: current position in TX buffer to be read
  313. * @tx_end: end position in TX buffer to be read
  314. * @rx: current position in RX buffer to be written
  315. * @rx_end: end position in RX buffer to be written
  316. * @read: the type of read currently going on
  317. * @write: the type of write currently going on
  318. * @exp_fifo_level: expected FIFO level
  319. * @rx_lev_trig: receive FIFO watermark level which triggers IRQ
  320. * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ
  321. * @dma_rx_channel: optional channel for RX DMA
  322. * @dma_tx_channel: optional channel for TX DMA
  323. * @sgt_rx: scattertable for the RX transfer
  324. * @sgt_tx: scattertable for the TX transfer
  325. * @dummypage: a dummy page used for driving data on the bus with DMA
  326. * @dma_running: indicates whether DMA is in operation
  327. * @cur_cs: current chip select index
  328. * @cur_gpiod: current chip select GPIO descriptor
  329. */
  330. struct pl022 {
  331. struct amba_device *adev;
  332. struct vendor_data *vendor;
  333. resource_size_t phybase;
  334. void __iomem *virtbase;
  335. struct clk *clk;
  336. struct spi_master *master;
  337. struct pl022_ssp_controller *master_info;
  338. /* Message per-transfer pump */
  339. struct tasklet_struct pump_transfers;
  340. struct spi_message *cur_msg;
  341. struct spi_transfer *cur_transfer;
  342. struct chip_data *cur_chip;
  343. bool next_msg_cs_active;
  344. void *tx;
  345. void *tx_end;
  346. void *rx;
  347. void *rx_end;
  348. enum ssp_reading read;
  349. enum ssp_writing write;
  350. u32 exp_fifo_level;
  351. enum ssp_rx_level_trig rx_lev_trig;
  352. enum ssp_tx_level_trig tx_lev_trig;
  353. /* DMA settings */
  354. #ifdef CONFIG_DMA_ENGINE
  355. struct dma_chan *dma_rx_channel;
  356. struct dma_chan *dma_tx_channel;
  357. struct sg_table sgt_rx;
  358. struct sg_table sgt_tx;
  359. char *dummypage;
  360. bool dma_running;
  361. #endif
  362. int cur_cs;
  363. struct gpio_desc *cur_gpiod;
  364. };
  365. /**
  366. * struct chip_data - To maintain runtime state of SSP for each client chip
  367. * @cr0: Value of control register CR0 of SSP - on later ST variants this
  368. * register is 32 bits wide rather than just 16
  369. * @cr1: Value of control register CR1 of SSP
  370. * @dmacr: Value of DMA control Register of SSP
  371. * @cpsr: Value of Clock prescale register
  372. * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
  373. * @enable_dma: Whether to enable DMA or not
  374. * @read: function ptr to be used to read when doing xfer for this chip
  375. * @write: function ptr to be used to write when doing xfer for this chip
  376. * @xfer_type: polling/interrupt/DMA
  377. *
  378. * Runtime state of the SSP controller, maintained per chip,
  379. * This would be set according to the current message that would be served
  380. */
  381. struct chip_data {
  382. u32 cr0;
  383. u16 cr1;
  384. u16 dmacr;
  385. u16 cpsr;
  386. u8 n_bytes;
  387. bool enable_dma;
  388. enum ssp_reading read;
  389. enum ssp_writing write;
  390. int xfer_type;
  391. };
  392. /**
  393. * internal_cs_control - Control chip select signals via SSP_CSR.
  394. * @pl022: SSP driver private data structure
  395. * @command: select/delect the chip
  396. *
  397. * Used on controller with internal chip select control via SSP_CSR register
  398. * (vendor extension). Each of the 5 LSB in the register controls one chip
  399. * select signal.
  400. */
  401. static void internal_cs_control(struct pl022 *pl022, u32 command)
  402. {
  403. u32 tmp;
  404. tmp = readw(SSP_CSR(pl022->virtbase));
  405. if (command == SSP_CHIP_SELECT)
  406. tmp &= ~BIT(pl022->cur_cs);
  407. else
  408. tmp |= BIT(pl022->cur_cs);
  409. writew(tmp, SSP_CSR(pl022->virtbase));
  410. }
  411. static void pl022_cs_control(struct pl022 *pl022, u32 command)
  412. {
  413. if (pl022->vendor->internal_cs_ctrl)
  414. internal_cs_control(pl022, command);
  415. else if (pl022->cur_gpiod)
  416. /*
  417. * This needs to be inverted since with GPIOLIB in
  418. * control, the inversion will be handled by
  419. * GPIOLIB's active low handling. The "command"
  420. * passed into this function will be SSP_CHIP_SELECT
  421. * which is enum:ed to 0, so we need the inverse
  422. * (1) to activate chip select.
  423. */
  424. gpiod_set_value(pl022->cur_gpiod, !command);
  425. }
  426. /**
  427. * giveback - current spi_message is over, schedule next message and call
  428. * callback of this message. Assumes that caller already
  429. * set message->status; dma and pio irqs are blocked
  430. * @pl022: SSP driver private data structure
  431. */
  432. static void giveback(struct pl022 *pl022)
  433. {
  434. struct spi_transfer *last_transfer;
  435. pl022->next_msg_cs_active = false;
  436. last_transfer = list_last_entry(&pl022->cur_msg->transfers,
  437. struct spi_transfer, transfer_list);
  438. /* Delay if requested before any change in chip select */
  439. /*
  440. * FIXME: This runs in interrupt context.
  441. * Is this really smart?
  442. */
  443. spi_transfer_delay_exec(last_transfer);
  444. if (!last_transfer->cs_change) {
  445. struct spi_message *next_msg;
  446. /*
  447. * cs_change was not set. We can keep the chip select
  448. * enabled if there is message in the queue and it is
  449. * for the same spi device.
  450. *
  451. * We cannot postpone this until pump_messages, because
  452. * after calling msg->complete (below) the driver that
  453. * sent the current message could be unloaded, which
  454. * could invalidate the cs_control() callback...
  455. */
  456. /* get a pointer to the next message, if any */
  457. next_msg = spi_get_next_queued_message(pl022->master);
  458. /*
  459. * see if the next and current messages point
  460. * to the same spi device.
  461. */
  462. if (next_msg && next_msg->spi != pl022->cur_msg->spi)
  463. next_msg = NULL;
  464. if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
  465. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  466. else
  467. pl022->next_msg_cs_active = true;
  468. }
  469. pl022->cur_msg = NULL;
  470. pl022->cur_transfer = NULL;
  471. pl022->cur_chip = NULL;
  472. /* disable the SPI/SSP operation */
  473. writew((readw(SSP_CR1(pl022->virtbase)) &
  474. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  475. spi_finalize_current_message(pl022->master);
  476. }
  477. /**
  478. * flush - flush the FIFO to reach a clean state
  479. * @pl022: SSP driver private data structure
  480. */
  481. static int flush(struct pl022 *pl022)
  482. {
  483. unsigned long limit = loops_per_jiffy << 1;
  484. dev_dbg(&pl022->adev->dev, "flush\n");
  485. do {
  486. while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  487. readw(SSP_DR(pl022->virtbase));
  488. } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
  489. pl022->exp_fifo_level = 0;
  490. return limit;
  491. }
  492. /**
  493. * restore_state - Load configuration of current chip
  494. * @pl022: SSP driver private data structure
  495. */
  496. static void restore_state(struct pl022 *pl022)
  497. {
  498. struct chip_data *chip = pl022->cur_chip;
  499. if (pl022->vendor->extended_cr)
  500. writel(chip->cr0, SSP_CR0(pl022->virtbase));
  501. else
  502. writew(chip->cr0, SSP_CR0(pl022->virtbase));
  503. writew(chip->cr1, SSP_CR1(pl022->virtbase));
  504. writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
  505. writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
  506. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  507. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  508. }
  509. /*
  510. * Default SSP Register Values
  511. */
  512. #define DEFAULT_SSP_REG_CR0 ( \
  513. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
  514. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
  515. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  516. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  517. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  518. )
  519. /* ST versions have slightly different bit layout */
  520. #define DEFAULT_SSP_REG_CR0_ST ( \
  521. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  522. GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
  523. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  524. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  525. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
  526. GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
  527. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
  528. )
  529. /* The PL023 version is slightly different again */
  530. #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
  531. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  532. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  533. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  534. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  535. )
  536. #define DEFAULT_SSP_REG_CR1 ( \
  537. GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
  538. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  539. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  540. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
  541. )
  542. /* ST versions extend this register to use all 16 bits */
  543. #define DEFAULT_SSP_REG_CR1_ST ( \
  544. DEFAULT_SSP_REG_CR1 | \
  545. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  546. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  547. GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
  548. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  549. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
  550. )
  551. /*
  552. * The PL023 variant has further differences: no loopback mode, no microwire
  553. * support, and a new clock feedback delay setting.
  554. */
  555. #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
  556. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  557. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  558. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
  559. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  560. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  561. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  562. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
  563. GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
  564. )
  565. #define DEFAULT_SSP_REG_CPSR ( \
  566. GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
  567. )
  568. #define DEFAULT_SSP_REG_DMACR (\
  569. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
  570. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
  571. )
  572. /**
  573. * load_ssp_default_config - Load default configuration for SSP
  574. * @pl022: SSP driver private data structure
  575. */
  576. static void load_ssp_default_config(struct pl022 *pl022)
  577. {
  578. if (pl022->vendor->pl023) {
  579. writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
  580. writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
  581. } else if (pl022->vendor->extended_cr) {
  582. writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
  583. writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
  584. } else {
  585. writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
  586. writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
  587. }
  588. writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
  589. writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
  590. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  591. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  592. }
  593. /*
  594. * This will write to TX and read from RX according to the parameters
  595. * set in pl022.
  596. */
  597. static void readwriter(struct pl022 *pl022)
  598. {
  599. /*
  600. * The FIFO depth is different between primecell variants.
  601. * I believe filling in too much in the FIFO might cause
  602. * errons in 8bit wide transfers on ARM variants (just 8 words
  603. * FIFO, means only 8x8 = 64 bits in FIFO) at least.
  604. *
  605. * To prevent this issue, the TX FIFO is only filled to the
  606. * unused RX FIFO fill length, regardless of what the TX
  607. * FIFO status flag indicates.
  608. */
  609. dev_dbg(&pl022->adev->dev,
  610. "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
  611. __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
  612. /* Read as much as you can */
  613. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  614. && (pl022->rx < pl022->rx_end)) {
  615. switch (pl022->read) {
  616. case READING_NULL:
  617. readw(SSP_DR(pl022->virtbase));
  618. break;
  619. case READING_U8:
  620. *(u8 *) (pl022->rx) =
  621. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  622. break;
  623. case READING_U16:
  624. *(u16 *) (pl022->rx) =
  625. (u16) readw(SSP_DR(pl022->virtbase));
  626. break;
  627. case READING_U32:
  628. *(u32 *) (pl022->rx) =
  629. readl(SSP_DR(pl022->virtbase));
  630. break;
  631. }
  632. pl022->rx += (pl022->cur_chip->n_bytes);
  633. pl022->exp_fifo_level--;
  634. }
  635. /*
  636. * Write as much as possible up to the RX FIFO size
  637. */
  638. while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
  639. && (pl022->tx < pl022->tx_end)) {
  640. switch (pl022->write) {
  641. case WRITING_NULL:
  642. writew(0x0, SSP_DR(pl022->virtbase));
  643. break;
  644. case WRITING_U8:
  645. writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
  646. break;
  647. case WRITING_U16:
  648. writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
  649. break;
  650. case WRITING_U32:
  651. writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
  652. break;
  653. }
  654. pl022->tx += (pl022->cur_chip->n_bytes);
  655. pl022->exp_fifo_level++;
  656. /*
  657. * This inner reader takes care of things appearing in the RX
  658. * FIFO as we're transmitting. This will happen a lot since the
  659. * clock starts running when you put things into the TX FIFO,
  660. * and then things are continuously clocked into the RX FIFO.
  661. */
  662. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  663. && (pl022->rx < pl022->rx_end)) {
  664. switch (pl022->read) {
  665. case READING_NULL:
  666. readw(SSP_DR(pl022->virtbase));
  667. break;
  668. case READING_U8:
  669. *(u8 *) (pl022->rx) =
  670. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  671. break;
  672. case READING_U16:
  673. *(u16 *) (pl022->rx) =
  674. (u16) readw(SSP_DR(pl022->virtbase));
  675. break;
  676. case READING_U32:
  677. *(u32 *) (pl022->rx) =
  678. readl(SSP_DR(pl022->virtbase));
  679. break;
  680. }
  681. pl022->rx += (pl022->cur_chip->n_bytes);
  682. pl022->exp_fifo_level--;
  683. }
  684. }
  685. /*
  686. * When we exit here the TX FIFO should be full and the RX FIFO
  687. * should be empty
  688. */
  689. }
  690. /**
  691. * next_transfer - Move to the Next transfer in the current spi message
  692. * @pl022: SSP driver private data structure
  693. *
  694. * This function moves though the linked list of spi transfers in the
  695. * current spi message and returns with the state of current spi
  696. * message i.e whether its last transfer is done(STATE_DONE) or
  697. * Next transfer is ready(STATE_RUNNING)
  698. */
  699. static void *next_transfer(struct pl022 *pl022)
  700. {
  701. struct spi_message *msg = pl022->cur_msg;
  702. struct spi_transfer *trans = pl022->cur_transfer;
  703. /* Move to next transfer */
  704. if (trans->transfer_list.next != &msg->transfers) {
  705. pl022->cur_transfer =
  706. list_entry(trans->transfer_list.next,
  707. struct spi_transfer, transfer_list);
  708. return STATE_RUNNING;
  709. }
  710. return STATE_DONE;
  711. }
  712. /*
  713. * This DMA functionality is only compiled in if we have
  714. * access to the generic DMA devices/DMA engine.
  715. */
  716. #ifdef CONFIG_DMA_ENGINE
  717. static void unmap_free_dma_scatter(struct pl022 *pl022)
  718. {
  719. /* Unmap and free the SG tables */
  720. dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
  721. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  722. dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
  723. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  724. sg_free_table(&pl022->sgt_rx);
  725. sg_free_table(&pl022->sgt_tx);
  726. }
  727. static void dma_callback(void *data)
  728. {
  729. struct pl022 *pl022 = data;
  730. struct spi_message *msg = pl022->cur_msg;
  731. BUG_ON(!pl022->sgt_rx.sgl);
  732. #ifdef VERBOSE_DEBUG
  733. /*
  734. * Optionally dump out buffers to inspect contents, this is
  735. * good if you want to convince yourself that the loopback
  736. * read/write contents are the same, when adopting to a new
  737. * DMA engine.
  738. */
  739. {
  740. struct scatterlist *sg;
  741. unsigned int i;
  742. dma_sync_sg_for_cpu(&pl022->adev->dev,
  743. pl022->sgt_rx.sgl,
  744. pl022->sgt_rx.nents,
  745. DMA_FROM_DEVICE);
  746. for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
  747. dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
  748. print_hex_dump(KERN_ERR, "SPI RX: ",
  749. DUMP_PREFIX_OFFSET,
  750. 16,
  751. 1,
  752. sg_virt(sg),
  753. sg_dma_len(sg),
  754. 1);
  755. }
  756. for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
  757. dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
  758. print_hex_dump(KERN_ERR, "SPI TX: ",
  759. DUMP_PREFIX_OFFSET,
  760. 16,
  761. 1,
  762. sg_virt(sg),
  763. sg_dma_len(sg),
  764. 1);
  765. }
  766. }
  767. #endif
  768. unmap_free_dma_scatter(pl022);
  769. /* Update total bytes transferred */
  770. msg->actual_length += pl022->cur_transfer->len;
  771. /* Move to next transfer */
  772. msg->state = next_transfer(pl022);
  773. if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
  774. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  775. tasklet_schedule(&pl022->pump_transfers);
  776. }
  777. static void setup_dma_scatter(struct pl022 *pl022,
  778. void *buffer,
  779. unsigned int length,
  780. struct sg_table *sgtab)
  781. {
  782. struct scatterlist *sg;
  783. int bytesleft = length;
  784. void *bufp = buffer;
  785. int mapbytes;
  786. int i;
  787. if (buffer) {
  788. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  789. /*
  790. * If there are less bytes left than what fits
  791. * in the current page (plus page alignment offset)
  792. * we just feed in this, else we stuff in as much
  793. * as we can.
  794. */
  795. if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
  796. mapbytes = bytesleft;
  797. else
  798. mapbytes = PAGE_SIZE - offset_in_page(bufp);
  799. sg_set_page(sg, virt_to_page(bufp),
  800. mapbytes, offset_in_page(bufp));
  801. bufp += mapbytes;
  802. bytesleft -= mapbytes;
  803. dev_dbg(&pl022->adev->dev,
  804. "set RX/TX target page @ %p, %d bytes, %d left\n",
  805. bufp, mapbytes, bytesleft);
  806. }
  807. } else {
  808. /* Map the dummy buffer on every page */
  809. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  810. if (bytesleft < PAGE_SIZE)
  811. mapbytes = bytesleft;
  812. else
  813. mapbytes = PAGE_SIZE;
  814. sg_set_page(sg, virt_to_page(pl022->dummypage),
  815. mapbytes, 0);
  816. bytesleft -= mapbytes;
  817. dev_dbg(&pl022->adev->dev,
  818. "set RX/TX to dummy page %d bytes, %d left\n",
  819. mapbytes, bytesleft);
  820. }
  821. }
  822. BUG_ON(bytesleft);
  823. }
  824. /**
  825. * configure_dma - configures the channels for the next transfer
  826. * @pl022: SSP driver's private data structure
  827. */
  828. static int configure_dma(struct pl022 *pl022)
  829. {
  830. struct dma_slave_config rx_conf = {
  831. .src_addr = SSP_DR(pl022->phybase),
  832. .direction = DMA_DEV_TO_MEM,
  833. .device_fc = false,
  834. };
  835. struct dma_slave_config tx_conf = {
  836. .dst_addr = SSP_DR(pl022->phybase),
  837. .direction = DMA_MEM_TO_DEV,
  838. .device_fc = false,
  839. };
  840. unsigned int pages;
  841. int ret;
  842. int rx_sglen, tx_sglen;
  843. struct dma_chan *rxchan = pl022->dma_rx_channel;
  844. struct dma_chan *txchan = pl022->dma_tx_channel;
  845. struct dma_async_tx_descriptor *rxdesc;
  846. struct dma_async_tx_descriptor *txdesc;
  847. /* Check that the channels are available */
  848. if (!rxchan || !txchan)
  849. return -ENODEV;
  850. /*
  851. * If supplied, the DMA burstsize should equal the FIFO trigger level.
  852. * Notice that the DMA engine uses one-to-one mapping. Since we can
  853. * not trigger on 2 elements this needs explicit mapping rather than
  854. * calculation.
  855. */
  856. switch (pl022->rx_lev_trig) {
  857. case SSP_RX_1_OR_MORE_ELEM:
  858. rx_conf.src_maxburst = 1;
  859. break;
  860. case SSP_RX_4_OR_MORE_ELEM:
  861. rx_conf.src_maxburst = 4;
  862. break;
  863. case SSP_RX_8_OR_MORE_ELEM:
  864. rx_conf.src_maxburst = 8;
  865. break;
  866. case SSP_RX_16_OR_MORE_ELEM:
  867. rx_conf.src_maxburst = 16;
  868. break;
  869. case SSP_RX_32_OR_MORE_ELEM:
  870. rx_conf.src_maxburst = 32;
  871. break;
  872. default:
  873. rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
  874. break;
  875. }
  876. switch (pl022->tx_lev_trig) {
  877. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  878. tx_conf.dst_maxburst = 1;
  879. break;
  880. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  881. tx_conf.dst_maxburst = 4;
  882. break;
  883. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  884. tx_conf.dst_maxburst = 8;
  885. break;
  886. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  887. tx_conf.dst_maxburst = 16;
  888. break;
  889. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  890. tx_conf.dst_maxburst = 32;
  891. break;
  892. default:
  893. tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
  894. break;
  895. }
  896. switch (pl022->read) {
  897. case READING_NULL:
  898. /* Use the same as for writing */
  899. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  900. break;
  901. case READING_U8:
  902. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  903. break;
  904. case READING_U16:
  905. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  906. break;
  907. case READING_U32:
  908. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  909. break;
  910. }
  911. switch (pl022->write) {
  912. case WRITING_NULL:
  913. /* Use the same as for reading */
  914. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  915. break;
  916. case WRITING_U8:
  917. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  918. break;
  919. case WRITING_U16:
  920. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  921. break;
  922. case WRITING_U32:
  923. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  924. break;
  925. }
  926. /* SPI pecularity: we need to read and write the same width */
  927. if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  928. rx_conf.src_addr_width = tx_conf.dst_addr_width;
  929. if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  930. tx_conf.dst_addr_width = rx_conf.src_addr_width;
  931. BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
  932. dmaengine_slave_config(rxchan, &rx_conf);
  933. dmaengine_slave_config(txchan, &tx_conf);
  934. /* Create sglists for the transfers */
  935. pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
  936. dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
  937. ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
  938. if (ret)
  939. goto err_alloc_rx_sg;
  940. ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
  941. if (ret)
  942. goto err_alloc_tx_sg;
  943. /* Fill in the scatterlists for the RX+TX buffers */
  944. setup_dma_scatter(pl022, pl022->rx,
  945. pl022->cur_transfer->len, &pl022->sgt_rx);
  946. setup_dma_scatter(pl022, pl022->tx,
  947. pl022->cur_transfer->len, &pl022->sgt_tx);
  948. /* Map DMA buffers */
  949. rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  950. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  951. if (!rx_sglen)
  952. goto err_rx_sgmap;
  953. tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  954. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  955. if (!tx_sglen)
  956. goto err_tx_sgmap;
  957. /* Send both scatterlists */
  958. rxdesc = dmaengine_prep_slave_sg(rxchan,
  959. pl022->sgt_rx.sgl,
  960. rx_sglen,
  961. DMA_DEV_TO_MEM,
  962. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  963. if (!rxdesc)
  964. goto err_rxdesc;
  965. txdesc = dmaengine_prep_slave_sg(txchan,
  966. pl022->sgt_tx.sgl,
  967. tx_sglen,
  968. DMA_MEM_TO_DEV,
  969. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  970. if (!txdesc)
  971. goto err_txdesc;
  972. /* Put the callback on the RX transfer only, that should finish last */
  973. rxdesc->callback = dma_callback;
  974. rxdesc->callback_param = pl022;
  975. /* Submit and fire RX and TX with TX last so we're ready to read! */
  976. dmaengine_submit(rxdesc);
  977. dmaengine_submit(txdesc);
  978. dma_async_issue_pending(rxchan);
  979. dma_async_issue_pending(txchan);
  980. pl022->dma_running = true;
  981. return 0;
  982. err_txdesc:
  983. dmaengine_terminate_all(txchan);
  984. err_rxdesc:
  985. dmaengine_terminate_all(rxchan);
  986. dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  987. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  988. err_tx_sgmap:
  989. dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  990. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  991. err_rx_sgmap:
  992. sg_free_table(&pl022->sgt_tx);
  993. err_alloc_tx_sg:
  994. sg_free_table(&pl022->sgt_rx);
  995. err_alloc_rx_sg:
  996. return -ENOMEM;
  997. }
  998. static int pl022_dma_probe(struct pl022 *pl022)
  999. {
  1000. dma_cap_mask_t mask;
  1001. /* Try to acquire a generic DMA engine slave channel */
  1002. dma_cap_zero(mask);
  1003. dma_cap_set(DMA_SLAVE, mask);
  1004. /*
  1005. * We need both RX and TX channels to do DMA, else do none
  1006. * of them.
  1007. */
  1008. pl022->dma_rx_channel = dma_request_channel(mask,
  1009. pl022->master_info->dma_filter,
  1010. pl022->master_info->dma_rx_param);
  1011. if (!pl022->dma_rx_channel) {
  1012. dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
  1013. goto err_no_rxchan;
  1014. }
  1015. pl022->dma_tx_channel = dma_request_channel(mask,
  1016. pl022->master_info->dma_filter,
  1017. pl022->master_info->dma_tx_param);
  1018. if (!pl022->dma_tx_channel) {
  1019. dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
  1020. goto err_no_txchan;
  1021. }
  1022. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1023. if (!pl022->dummypage)
  1024. goto err_no_dummypage;
  1025. dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
  1026. dma_chan_name(pl022->dma_rx_channel),
  1027. dma_chan_name(pl022->dma_tx_channel));
  1028. return 0;
  1029. err_no_dummypage:
  1030. dma_release_channel(pl022->dma_tx_channel);
  1031. err_no_txchan:
  1032. dma_release_channel(pl022->dma_rx_channel);
  1033. pl022->dma_rx_channel = NULL;
  1034. err_no_rxchan:
  1035. dev_err(&pl022->adev->dev,
  1036. "Failed to work in dma mode, work without dma!\n");
  1037. return -ENODEV;
  1038. }
  1039. static int pl022_dma_autoprobe(struct pl022 *pl022)
  1040. {
  1041. struct device *dev = &pl022->adev->dev;
  1042. struct dma_chan *chan;
  1043. int err;
  1044. /* automatically configure DMA channels from platform, normally using DT */
  1045. chan = dma_request_chan(dev, "rx");
  1046. if (IS_ERR(chan)) {
  1047. err = PTR_ERR(chan);
  1048. goto err_no_rxchan;
  1049. }
  1050. pl022->dma_rx_channel = chan;
  1051. chan = dma_request_chan(dev, "tx");
  1052. if (IS_ERR(chan)) {
  1053. err = PTR_ERR(chan);
  1054. goto err_no_txchan;
  1055. }
  1056. pl022->dma_tx_channel = chan;
  1057. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1058. if (!pl022->dummypage) {
  1059. err = -ENOMEM;
  1060. goto err_no_dummypage;
  1061. }
  1062. return 0;
  1063. err_no_dummypage:
  1064. dma_release_channel(pl022->dma_tx_channel);
  1065. pl022->dma_tx_channel = NULL;
  1066. err_no_txchan:
  1067. dma_release_channel(pl022->dma_rx_channel);
  1068. pl022->dma_rx_channel = NULL;
  1069. err_no_rxchan:
  1070. return err;
  1071. }
  1072. static void terminate_dma(struct pl022 *pl022)
  1073. {
  1074. struct dma_chan *rxchan = pl022->dma_rx_channel;
  1075. struct dma_chan *txchan = pl022->dma_tx_channel;
  1076. dmaengine_terminate_all(rxchan);
  1077. dmaengine_terminate_all(txchan);
  1078. unmap_free_dma_scatter(pl022);
  1079. pl022->dma_running = false;
  1080. }
  1081. static void pl022_dma_remove(struct pl022 *pl022)
  1082. {
  1083. if (pl022->dma_running)
  1084. terminate_dma(pl022);
  1085. if (pl022->dma_tx_channel)
  1086. dma_release_channel(pl022->dma_tx_channel);
  1087. if (pl022->dma_rx_channel)
  1088. dma_release_channel(pl022->dma_rx_channel);
  1089. kfree(pl022->dummypage);
  1090. }
  1091. #else
  1092. static inline int configure_dma(struct pl022 *pl022)
  1093. {
  1094. return -ENODEV;
  1095. }
  1096. static inline int pl022_dma_autoprobe(struct pl022 *pl022)
  1097. {
  1098. return 0;
  1099. }
  1100. static inline int pl022_dma_probe(struct pl022 *pl022)
  1101. {
  1102. return 0;
  1103. }
  1104. static inline void pl022_dma_remove(struct pl022 *pl022)
  1105. {
  1106. }
  1107. #endif
  1108. /**
  1109. * pl022_interrupt_handler - Interrupt handler for SSP controller
  1110. * @irq: IRQ number
  1111. * @dev_id: Local device data
  1112. *
  1113. * This function handles interrupts generated for an interrupt based transfer.
  1114. * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
  1115. * current message's state as STATE_ERROR and schedule the tasklet
  1116. * pump_transfers which will do the postprocessing of the current message by
  1117. * calling giveback(). Otherwise it reads data from RX FIFO till there is no
  1118. * more data, and writes data in TX FIFO till it is not full. If we complete
  1119. * the transfer we move to the next transfer and schedule the tasklet.
  1120. */
  1121. static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
  1122. {
  1123. struct pl022 *pl022 = dev_id;
  1124. struct spi_message *msg = pl022->cur_msg;
  1125. u16 irq_status = 0;
  1126. if (unlikely(!msg)) {
  1127. dev_err(&pl022->adev->dev,
  1128. "bad message state in interrupt handler");
  1129. /* Never fail */
  1130. return IRQ_HANDLED;
  1131. }
  1132. /* Read the Interrupt Status Register */
  1133. irq_status = readw(SSP_MIS(pl022->virtbase));
  1134. if (unlikely(!irq_status))
  1135. return IRQ_NONE;
  1136. /*
  1137. * This handles the FIFO interrupts, the timeout
  1138. * interrupts are flatly ignored, they cannot be
  1139. * trusted.
  1140. */
  1141. if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
  1142. /*
  1143. * Overrun interrupt - bail out since our Data has been
  1144. * corrupted
  1145. */
  1146. dev_err(&pl022->adev->dev, "FIFO overrun\n");
  1147. if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
  1148. dev_err(&pl022->adev->dev,
  1149. "RXFIFO is full\n");
  1150. /*
  1151. * Disable and clear interrupts, disable SSP,
  1152. * mark message with bad status so it can be
  1153. * retried.
  1154. */
  1155. writew(DISABLE_ALL_INTERRUPTS,
  1156. SSP_IMSC(pl022->virtbase));
  1157. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1158. writew((readw(SSP_CR1(pl022->virtbase)) &
  1159. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1160. msg->state = STATE_ERROR;
  1161. /* Schedule message queue handler */
  1162. tasklet_schedule(&pl022->pump_transfers);
  1163. return IRQ_HANDLED;
  1164. }
  1165. readwriter(pl022);
  1166. if (pl022->tx == pl022->tx_end) {
  1167. /* Disable Transmit interrupt, enable receive interrupt */
  1168. writew((readw(SSP_IMSC(pl022->virtbase)) &
  1169. ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
  1170. SSP_IMSC(pl022->virtbase));
  1171. }
  1172. /*
  1173. * Since all transactions must write as much as shall be read,
  1174. * we can conclude the entire transaction once RX is complete.
  1175. * At this point, all TX will always be finished.
  1176. */
  1177. if (pl022->rx >= pl022->rx_end) {
  1178. writew(DISABLE_ALL_INTERRUPTS,
  1179. SSP_IMSC(pl022->virtbase));
  1180. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1181. if (unlikely(pl022->rx > pl022->rx_end)) {
  1182. dev_warn(&pl022->adev->dev, "read %u surplus "
  1183. "bytes (did you request an odd "
  1184. "number of bytes on a 16bit bus?)\n",
  1185. (u32) (pl022->rx - pl022->rx_end));
  1186. }
  1187. /* Update total bytes transferred */
  1188. msg->actual_length += pl022->cur_transfer->len;
  1189. /* Move to next transfer */
  1190. msg->state = next_transfer(pl022);
  1191. if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
  1192. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1193. tasklet_schedule(&pl022->pump_transfers);
  1194. return IRQ_HANDLED;
  1195. }
  1196. return IRQ_HANDLED;
  1197. }
  1198. /*
  1199. * This sets up the pointers to memory for the next message to
  1200. * send out on the SPI bus.
  1201. */
  1202. static int set_up_next_transfer(struct pl022 *pl022,
  1203. struct spi_transfer *transfer)
  1204. {
  1205. int residue;
  1206. /* Sanity check the message for this bus width */
  1207. residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
  1208. if (unlikely(residue != 0)) {
  1209. dev_err(&pl022->adev->dev,
  1210. "message of %u bytes to transmit but the current "
  1211. "chip bus has a data width of %u bytes!\n",
  1212. pl022->cur_transfer->len,
  1213. pl022->cur_chip->n_bytes);
  1214. dev_err(&pl022->adev->dev, "skipping this message\n");
  1215. return -EIO;
  1216. }
  1217. pl022->tx = (void *)transfer->tx_buf;
  1218. pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
  1219. pl022->rx = (void *)transfer->rx_buf;
  1220. pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
  1221. pl022->write =
  1222. pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
  1223. pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
  1224. return 0;
  1225. }
  1226. /**
  1227. * pump_transfers - Tasklet function which schedules next transfer
  1228. * when running in interrupt or DMA transfer mode.
  1229. * @data: SSP driver private data structure
  1230. *
  1231. */
  1232. static void pump_transfers(unsigned long data)
  1233. {
  1234. struct pl022 *pl022 = (struct pl022 *) data;
  1235. struct spi_message *message = NULL;
  1236. struct spi_transfer *transfer = NULL;
  1237. struct spi_transfer *previous = NULL;
  1238. /* Get current state information */
  1239. message = pl022->cur_msg;
  1240. transfer = pl022->cur_transfer;
  1241. /* Handle for abort */
  1242. if (message->state == STATE_ERROR) {
  1243. message->status = -EIO;
  1244. giveback(pl022);
  1245. return;
  1246. }
  1247. /* Handle end of message */
  1248. if (message->state == STATE_DONE) {
  1249. message->status = 0;
  1250. giveback(pl022);
  1251. return;
  1252. }
  1253. /* Delay if requested at end of transfer before CS change */
  1254. if (message->state == STATE_RUNNING) {
  1255. previous = list_entry(transfer->transfer_list.prev,
  1256. struct spi_transfer,
  1257. transfer_list);
  1258. /*
  1259. * FIXME: This runs in interrupt context.
  1260. * Is this really smart?
  1261. */
  1262. spi_transfer_delay_exec(previous);
  1263. /* Reselect chip select only if cs_change was requested */
  1264. if (previous->cs_change)
  1265. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1266. } else {
  1267. /* STATE_START */
  1268. message->state = STATE_RUNNING;
  1269. }
  1270. if (set_up_next_transfer(pl022, transfer)) {
  1271. message->state = STATE_ERROR;
  1272. message->status = -EIO;
  1273. giveback(pl022);
  1274. return;
  1275. }
  1276. /* Flush the FIFOs and let's go! */
  1277. flush(pl022);
  1278. if (pl022->cur_chip->enable_dma) {
  1279. if (configure_dma(pl022)) {
  1280. dev_dbg(&pl022->adev->dev,
  1281. "configuration of DMA failed, fall back to interrupt mode\n");
  1282. goto err_config_dma;
  1283. }
  1284. return;
  1285. }
  1286. err_config_dma:
  1287. /* enable all interrupts except RX */
  1288. writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
  1289. }
  1290. static void do_interrupt_dma_transfer(struct pl022 *pl022)
  1291. {
  1292. /*
  1293. * Default is to enable all interrupts except RX -
  1294. * this will be enabled once TX is complete
  1295. */
  1296. u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
  1297. /* Enable target chip, if not already active */
  1298. if (!pl022->next_msg_cs_active)
  1299. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1300. if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
  1301. /* Error path */
  1302. pl022->cur_msg->state = STATE_ERROR;
  1303. pl022->cur_msg->status = -EIO;
  1304. giveback(pl022);
  1305. return;
  1306. }
  1307. /* If we're using DMA, set up DMA here */
  1308. if (pl022->cur_chip->enable_dma) {
  1309. /* Configure DMA transfer */
  1310. if (configure_dma(pl022)) {
  1311. dev_dbg(&pl022->adev->dev,
  1312. "configuration of DMA failed, fall back to interrupt mode\n");
  1313. goto err_config_dma;
  1314. }
  1315. /* Disable interrupts in DMA mode, IRQ from DMA controller */
  1316. irqflags = DISABLE_ALL_INTERRUPTS;
  1317. }
  1318. err_config_dma:
  1319. /* Enable SSP, turn on interrupts */
  1320. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1321. SSP_CR1(pl022->virtbase));
  1322. writew(irqflags, SSP_IMSC(pl022->virtbase));
  1323. }
  1324. static void print_current_status(struct pl022 *pl022)
  1325. {
  1326. u32 read_cr0;
  1327. u16 read_cr1, read_dmacr, read_sr;
  1328. if (pl022->vendor->extended_cr)
  1329. read_cr0 = readl(SSP_CR0(pl022->virtbase));
  1330. else
  1331. read_cr0 = readw(SSP_CR0(pl022->virtbase));
  1332. read_cr1 = readw(SSP_CR1(pl022->virtbase));
  1333. read_dmacr = readw(SSP_DMACR(pl022->virtbase));
  1334. read_sr = readw(SSP_SR(pl022->virtbase));
  1335. dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
  1336. dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
  1337. dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
  1338. dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
  1339. dev_warn(&pl022->adev->dev,
  1340. "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
  1341. pl022->exp_fifo_level,
  1342. pl022->vendor->fifodepth);
  1343. }
  1344. static void do_polling_transfer(struct pl022 *pl022)
  1345. {
  1346. struct spi_message *message = NULL;
  1347. struct spi_transfer *transfer = NULL;
  1348. struct spi_transfer *previous = NULL;
  1349. unsigned long time, timeout;
  1350. message = pl022->cur_msg;
  1351. while (message->state != STATE_DONE) {
  1352. /* Handle for abort */
  1353. if (message->state == STATE_ERROR)
  1354. break;
  1355. transfer = pl022->cur_transfer;
  1356. /* Delay if requested at end of transfer */
  1357. if (message->state == STATE_RUNNING) {
  1358. previous =
  1359. list_entry(transfer->transfer_list.prev,
  1360. struct spi_transfer, transfer_list);
  1361. spi_transfer_delay_exec(previous);
  1362. if (previous->cs_change)
  1363. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1364. } else {
  1365. /* STATE_START */
  1366. message->state = STATE_RUNNING;
  1367. if (!pl022->next_msg_cs_active)
  1368. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1369. }
  1370. /* Configuration Changing Per Transfer */
  1371. if (set_up_next_transfer(pl022, transfer)) {
  1372. /* Error path */
  1373. message->state = STATE_ERROR;
  1374. break;
  1375. }
  1376. /* Flush FIFOs and enable SSP */
  1377. flush(pl022);
  1378. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1379. SSP_CR1(pl022->virtbase));
  1380. dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
  1381. timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
  1382. while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
  1383. time = jiffies;
  1384. readwriter(pl022);
  1385. if (time_after(time, timeout)) {
  1386. dev_warn(&pl022->adev->dev,
  1387. "%s: timeout!\n", __func__);
  1388. message->state = STATE_TIMEOUT;
  1389. print_current_status(pl022);
  1390. goto out;
  1391. }
  1392. cpu_relax();
  1393. }
  1394. /* Update total byte transferred */
  1395. message->actual_length += pl022->cur_transfer->len;
  1396. /* Move to next transfer */
  1397. message->state = next_transfer(pl022);
  1398. if (message->state != STATE_DONE
  1399. && pl022->cur_transfer->cs_change)
  1400. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1401. }
  1402. out:
  1403. /* Handle end of message */
  1404. if (message->state == STATE_DONE)
  1405. message->status = 0;
  1406. else if (message->state == STATE_TIMEOUT)
  1407. message->status = -EAGAIN;
  1408. else
  1409. message->status = -EIO;
  1410. giveback(pl022);
  1411. return;
  1412. }
  1413. static int pl022_transfer_one_message(struct spi_master *master,
  1414. struct spi_message *msg)
  1415. {
  1416. struct pl022 *pl022 = spi_master_get_devdata(master);
  1417. /* Initial message state */
  1418. pl022->cur_msg = msg;
  1419. msg->state = STATE_START;
  1420. pl022->cur_transfer = list_entry(msg->transfers.next,
  1421. struct spi_transfer, transfer_list);
  1422. /* Setup the SPI using the per chip configuration */
  1423. pl022->cur_chip = spi_get_ctldata(msg->spi);
  1424. pl022->cur_cs = msg->spi->chip_select;
  1425. /* This is always available but may be set to -ENOENT */
  1426. pl022->cur_gpiod = msg->spi->cs_gpiod;
  1427. restore_state(pl022);
  1428. flush(pl022);
  1429. if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
  1430. do_polling_transfer(pl022);
  1431. else
  1432. do_interrupt_dma_transfer(pl022);
  1433. return 0;
  1434. }
  1435. static int pl022_unprepare_transfer_hardware(struct spi_master *master)
  1436. {
  1437. struct pl022 *pl022 = spi_master_get_devdata(master);
  1438. /* nothing more to do - disable spi/ssp and power off */
  1439. writew((readw(SSP_CR1(pl022->virtbase)) &
  1440. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1441. return 0;
  1442. }
  1443. static int verify_controller_parameters(struct pl022 *pl022,
  1444. struct pl022_config_chip const *chip_info)
  1445. {
  1446. if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
  1447. || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
  1448. dev_err(&pl022->adev->dev,
  1449. "interface is configured incorrectly\n");
  1450. return -EINVAL;
  1451. }
  1452. if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
  1453. (!pl022->vendor->unidir)) {
  1454. dev_err(&pl022->adev->dev,
  1455. "unidirectional mode not supported in this "
  1456. "hardware version\n");
  1457. return -EINVAL;
  1458. }
  1459. if ((chip_info->hierarchy != SSP_MASTER)
  1460. && (chip_info->hierarchy != SSP_SLAVE)) {
  1461. dev_err(&pl022->adev->dev,
  1462. "hierarchy is configured incorrectly\n");
  1463. return -EINVAL;
  1464. }
  1465. if ((chip_info->com_mode != INTERRUPT_TRANSFER)
  1466. && (chip_info->com_mode != DMA_TRANSFER)
  1467. && (chip_info->com_mode != POLLING_TRANSFER)) {
  1468. dev_err(&pl022->adev->dev,
  1469. "Communication mode is configured incorrectly\n");
  1470. return -EINVAL;
  1471. }
  1472. switch (chip_info->rx_lev_trig) {
  1473. case SSP_RX_1_OR_MORE_ELEM:
  1474. case SSP_RX_4_OR_MORE_ELEM:
  1475. case SSP_RX_8_OR_MORE_ELEM:
  1476. /* These are always OK, all variants can handle this */
  1477. break;
  1478. case SSP_RX_16_OR_MORE_ELEM:
  1479. if (pl022->vendor->fifodepth < 16) {
  1480. dev_err(&pl022->adev->dev,
  1481. "RX FIFO Trigger Level is configured incorrectly\n");
  1482. return -EINVAL;
  1483. }
  1484. break;
  1485. case SSP_RX_32_OR_MORE_ELEM:
  1486. if (pl022->vendor->fifodepth < 32) {
  1487. dev_err(&pl022->adev->dev,
  1488. "RX FIFO Trigger Level is configured incorrectly\n");
  1489. return -EINVAL;
  1490. }
  1491. break;
  1492. default:
  1493. dev_err(&pl022->adev->dev,
  1494. "RX FIFO Trigger Level is configured incorrectly\n");
  1495. return -EINVAL;
  1496. }
  1497. switch (chip_info->tx_lev_trig) {
  1498. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  1499. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  1500. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  1501. /* These are always OK, all variants can handle this */
  1502. break;
  1503. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  1504. if (pl022->vendor->fifodepth < 16) {
  1505. dev_err(&pl022->adev->dev,
  1506. "TX FIFO Trigger Level is configured incorrectly\n");
  1507. return -EINVAL;
  1508. }
  1509. break;
  1510. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  1511. if (pl022->vendor->fifodepth < 32) {
  1512. dev_err(&pl022->adev->dev,
  1513. "TX FIFO Trigger Level is configured incorrectly\n");
  1514. return -EINVAL;
  1515. }
  1516. break;
  1517. default:
  1518. dev_err(&pl022->adev->dev,
  1519. "TX FIFO Trigger Level is configured incorrectly\n");
  1520. return -EINVAL;
  1521. }
  1522. if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
  1523. if ((chip_info->ctrl_len < SSP_BITS_4)
  1524. || (chip_info->ctrl_len > SSP_BITS_32)) {
  1525. dev_err(&pl022->adev->dev,
  1526. "CTRL LEN is configured incorrectly\n");
  1527. return -EINVAL;
  1528. }
  1529. if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
  1530. && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
  1531. dev_err(&pl022->adev->dev,
  1532. "Wait State is configured incorrectly\n");
  1533. return -EINVAL;
  1534. }
  1535. /* Half duplex is only available in the ST Micro version */
  1536. if (pl022->vendor->extended_cr) {
  1537. if ((chip_info->duplex !=
  1538. SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
  1539. && (chip_info->duplex !=
  1540. SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
  1541. dev_err(&pl022->adev->dev,
  1542. "Microwire duplex mode is configured incorrectly\n");
  1543. return -EINVAL;
  1544. }
  1545. } else {
  1546. if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) {
  1547. dev_err(&pl022->adev->dev,
  1548. "Microwire half duplex mode requested,"
  1549. " but this is only available in the"
  1550. " ST version of PL022\n");
  1551. return -EINVAL;
  1552. }
  1553. }
  1554. }
  1555. return 0;
  1556. }
  1557. static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
  1558. {
  1559. return rate / (cpsdvsr * (1 + scr));
  1560. }
  1561. static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
  1562. ssp_clock_params * clk_freq)
  1563. {
  1564. /* Lets calculate the frequency parameters */
  1565. u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
  1566. u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
  1567. best_scr = 0, tmp, found = 0;
  1568. rate = clk_get_rate(pl022->clk);
  1569. /* cpsdvscr = 2 & scr 0 */
  1570. max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
  1571. /* cpsdvsr = 254 & scr = 255 */
  1572. min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
  1573. if (freq > max_tclk)
  1574. dev_warn(&pl022->adev->dev,
  1575. "Max speed that can be programmed is %d Hz, you requested %d\n",
  1576. max_tclk, freq);
  1577. if (freq < min_tclk) {
  1578. dev_err(&pl022->adev->dev,
  1579. "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
  1580. freq, min_tclk);
  1581. return -EINVAL;
  1582. }
  1583. /*
  1584. * best_freq will give closest possible available rate (<= requested
  1585. * freq) for all values of scr & cpsdvsr.
  1586. */
  1587. while ((cpsdvsr <= CPSDVR_MAX) && !found) {
  1588. while (scr <= SCR_MAX) {
  1589. tmp = spi_rate(rate, cpsdvsr, scr);
  1590. if (tmp > freq) {
  1591. /* we need lower freq */
  1592. scr++;
  1593. continue;
  1594. }
  1595. /*
  1596. * If found exact value, mark found and break.
  1597. * If found more closer value, update and break.
  1598. */
  1599. if (tmp > best_freq) {
  1600. best_freq = tmp;
  1601. best_cpsdvsr = cpsdvsr;
  1602. best_scr = scr;
  1603. if (tmp == freq)
  1604. found = 1;
  1605. }
  1606. /*
  1607. * increased scr will give lower rates, which are not
  1608. * required
  1609. */
  1610. break;
  1611. }
  1612. cpsdvsr += 2;
  1613. scr = SCR_MIN;
  1614. }
  1615. WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
  1616. freq);
  1617. clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
  1618. clk_freq->scr = (u8) (best_scr & 0xFF);
  1619. dev_dbg(&pl022->adev->dev,
  1620. "SSP Target Frequency is: %u, Effective Frequency is %u\n",
  1621. freq, best_freq);
  1622. dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
  1623. clk_freq->cpsdvsr, clk_freq->scr);
  1624. return 0;
  1625. }
  1626. /*
  1627. * A piece of default chip info unless the platform
  1628. * supplies it.
  1629. */
  1630. static const struct pl022_config_chip pl022_default_chip_info = {
  1631. .com_mode = INTERRUPT_TRANSFER,
  1632. .iface = SSP_INTERFACE_MOTOROLA_SPI,
  1633. .hierarchy = SSP_MASTER,
  1634. .slave_tx_disable = DO_NOT_DRIVE_TX,
  1635. .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
  1636. .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
  1637. .ctrl_len = SSP_BITS_8,
  1638. .wait_state = SSP_MWIRE_WAIT_ZERO,
  1639. .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
  1640. };
  1641. /**
  1642. * pl022_setup - setup function registered to SPI master framework
  1643. * @spi: spi device which is requesting setup
  1644. *
  1645. * This function is registered to the SPI framework for this SPI master
  1646. * controller. If it is the first time when setup is called by this device,
  1647. * this function will initialize the runtime state for this chip and save
  1648. * the same in the device structure. Else it will update the runtime info
  1649. * with the updated chip info. Nothing is really being written to the
  1650. * controller hardware here, that is not done until the actual transfer
  1651. * commence.
  1652. */
  1653. static int pl022_setup(struct spi_device *spi)
  1654. {
  1655. struct pl022_config_chip const *chip_info;
  1656. struct pl022_config_chip chip_info_dt;
  1657. struct chip_data *chip;
  1658. struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
  1659. int status = 0;
  1660. struct pl022 *pl022 = spi_master_get_devdata(spi->master);
  1661. unsigned int bits = spi->bits_per_word;
  1662. u32 tmp;
  1663. struct device_node *np = spi->dev.of_node;
  1664. if (!spi->max_speed_hz)
  1665. return -EINVAL;
  1666. /* Get controller_state if one is supplied */
  1667. chip = spi_get_ctldata(spi);
  1668. if (chip == NULL) {
  1669. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  1670. if (!chip)
  1671. return -ENOMEM;
  1672. dev_dbg(&spi->dev,
  1673. "allocated memory for controller's runtime state\n");
  1674. }
  1675. /* Get controller data if one is supplied */
  1676. chip_info = spi->controller_data;
  1677. if (chip_info == NULL) {
  1678. if (np) {
  1679. chip_info_dt = pl022_default_chip_info;
  1680. chip_info_dt.hierarchy = SSP_MASTER;
  1681. of_property_read_u32(np, "pl022,interface",
  1682. &chip_info_dt.iface);
  1683. of_property_read_u32(np, "pl022,com-mode",
  1684. &chip_info_dt.com_mode);
  1685. of_property_read_u32(np, "pl022,rx-level-trig",
  1686. &chip_info_dt.rx_lev_trig);
  1687. of_property_read_u32(np, "pl022,tx-level-trig",
  1688. &chip_info_dt.tx_lev_trig);
  1689. of_property_read_u32(np, "pl022,ctrl-len",
  1690. &chip_info_dt.ctrl_len);
  1691. of_property_read_u32(np, "pl022,wait-state",
  1692. &chip_info_dt.wait_state);
  1693. of_property_read_u32(np, "pl022,duplex",
  1694. &chip_info_dt.duplex);
  1695. chip_info = &chip_info_dt;
  1696. } else {
  1697. chip_info = &pl022_default_chip_info;
  1698. /* spi_board_info.controller_data not is supplied */
  1699. dev_dbg(&spi->dev,
  1700. "using default controller_data settings\n");
  1701. }
  1702. } else
  1703. dev_dbg(&spi->dev,
  1704. "using user supplied controller_data settings\n");
  1705. /*
  1706. * We can override with custom divisors, else we use the board
  1707. * frequency setting
  1708. */
  1709. if ((0 == chip_info->clk_freq.cpsdvsr)
  1710. && (0 == chip_info->clk_freq.scr)) {
  1711. status = calculate_effective_freq(pl022,
  1712. spi->max_speed_hz,
  1713. &clk_freq);
  1714. if (status < 0)
  1715. goto err_config_params;
  1716. } else {
  1717. memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
  1718. if ((clk_freq.cpsdvsr % 2) != 0)
  1719. clk_freq.cpsdvsr =
  1720. clk_freq.cpsdvsr - 1;
  1721. }
  1722. if ((clk_freq.cpsdvsr < CPSDVR_MIN)
  1723. || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
  1724. status = -EINVAL;
  1725. dev_err(&spi->dev,
  1726. "cpsdvsr is configured incorrectly\n");
  1727. goto err_config_params;
  1728. }
  1729. status = verify_controller_parameters(pl022, chip_info);
  1730. if (status) {
  1731. dev_err(&spi->dev, "controller data is incorrect");
  1732. goto err_config_params;
  1733. }
  1734. pl022->rx_lev_trig = chip_info->rx_lev_trig;
  1735. pl022->tx_lev_trig = chip_info->tx_lev_trig;
  1736. /* Now set controller state based on controller data */
  1737. chip->xfer_type = chip_info->com_mode;
  1738. /* Check bits per word with vendor specific range */
  1739. if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
  1740. status = -ENOTSUPP;
  1741. dev_err(&spi->dev, "illegal data size for this controller!\n");
  1742. dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
  1743. pl022->vendor->max_bpw);
  1744. goto err_config_params;
  1745. } else if (bits <= 8) {
  1746. dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
  1747. chip->n_bytes = 1;
  1748. chip->read = READING_U8;
  1749. chip->write = WRITING_U8;
  1750. } else if (bits <= 16) {
  1751. dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
  1752. chip->n_bytes = 2;
  1753. chip->read = READING_U16;
  1754. chip->write = WRITING_U16;
  1755. } else {
  1756. dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
  1757. chip->n_bytes = 4;
  1758. chip->read = READING_U32;
  1759. chip->write = WRITING_U32;
  1760. }
  1761. /* Now Initialize all register settings required for this chip */
  1762. chip->cr0 = 0;
  1763. chip->cr1 = 0;
  1764. chip->dmacr = 0;
  1765. chip->cpsr = 0;
  1766. if ((chip_info->com_mode == DMA_TRANSFER)
  1767. && ((pl022->master_info)->enable_dma)) {
  1768. chip->enable_dma = true;
  1769. dev_dbg(&spi->dev, "DMA mode set in controller state\n");
  1770. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1771. SSP_DMACR_MASK_RXDMAE, 0);
  1772. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1773. SSP_DMACR_MASK_TXDMAE, 1);
  1774. } else {
  1775. chip->enable_dma = false;
  1776. dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
  1777. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1778. SSP_DMACR_MASK_RXDMAE, 0);
  1779. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1780. SSP_DMACR_MASK_TXDMAE, 1);
  1781. }
  1782. chip->cpsr = clk_freq.cpsdvsr;
  1783. /* Special setup for the ST micro extended control registers */
  1784. if (pl022->vendor->extended_cr) {
  1785. u32 etx;
  1786. if (pl022->vendor->pl023) {
  1787. /* These bits are only in the PL023 */
  1788. SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
  1789. SSP_CR1_MASK_FBCLKDEL_ST, 13);
  1790. } else {
  1791. /* These bits are in the PL022 but not PL023 */
  1792. SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
  1793. SSP_CR0_MASK_HALFDUP_ST, 5);
  1794. SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
  1795. SSP_CR0_MASK_CSS_ST, 16);
  1796. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1797. SSP_CR0_MASK_FRF_ST, 21);
  1798. SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
  1799. SSP_CR1_MASK_MWAIT_ST, 6);
  1800. }
  1801. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1802. SSP_CR0_MASK_DSS_ST, 0);
  1803. if (spi->mode & SPI_LSB_FIRST) {
  1804. tmp = SSP_RX_LSB;
  1805. etx = SSP_TX_LSB;
  1806. } else {
  1807. tmp = SSP_RX_MSB;
  1808. etx = SSP_TX_MSB;
  1809. }
  1810. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
  1811. SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
  1812. SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
  1813. SSP_CR1_MASK_RXIFLSEL_ST, 7);
  1814. SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
  1815. SSP_CR1_MASK_TXIFLSEL_ST, 10);
  1816. } else {
  1817. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1818. SSP_CR0_MASK_DSS, 0);
  1819. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1820. SSP_CR0_MASK_FRF, 4);
  1821. }
  1822. /* Stuff that is common for all versions */
  1823. if (spi->mode & SPI_CPOL)
  1824. tmp = SSP_CLK_POL_IDLE_HIGH;
  1825. else
  1826. tmp = SSP_CLK_POL_IDLE_LOW;
  1827. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
  1828. if (spi->mode & SPI_CPHA)
  1829. tmp = SSP_CLK_SECOND_EDGE;
  1830. else
  1831. tmp = SSP_CLK_FIRST_EDGE;
  1832. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
  1833. SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
  1834. /* Loopback is available on all versions except PL023 */
  1835. if (pl022->vendor->loopback) {
  1836. if (spi->mode & SPI_LOOP)
  1837. tmp = LOOPBACK_ENABLED;
  1838. else
  1839. tmp = LOOPBACK_DISABLED;
  1840. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
  1841. }
  1842. SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
  1843. SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
  1844. SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
  1845. 3);
  1846. /* Save controller_state */
  1847. spi_set_ctldata(spi, chip);
  1848. return status;
  1849. err_config_params:
  1850. spi_set_ctldata(spi, NULL);
  1851. kfree(chip);
  1852. return status;
  1853. }
  1854. /**
  1855. * pl022_cleanup - cleanup function registered to SPI master framework
  1856. * @spi: spi device which is requesting cleanup
  1857. *
  1858. * This function is registered to the SPI framework for this SPI master
  1859. * controller. It will free the runtime state of chip.
  1860. */
  1861. static void pl022_cleanup(struct spi_device *spi)
  1862. {
  1863. struct chip_data *chip = spi_get_ctldata(spi);
  1864. spi_set_ctldata(spi, NULL);
  1865. kfree(chip);
  1866. }
  1867. static struct pl022_ssp_controller *
  1868. pl022_platform_data_dt_get(struct device *dev)
  1869. {
  1870. struct device_node *np = dev->of_node;
  1871. struct pl022_ssp_controller *pd;
  1872. if (!np) {
  1873. dev_err(dev, "no dt node defined\n");
  1874. return NULL;
  1875. }
  1876. pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
  1877. if (!pd)
  1878. return NULL;
  1879. pd->bus_id = -1;
  1880. pd->enable_dma = 1;
  1881. of_property_read_u32(np, "pl022,autosuspend-delay",
  1882. &pd->autosuspend_delay);
  1883. pd->rt = of_property_read_bool(np, "pl022,rt");
  1884. return pd;
  1885. }
  1886. static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
  1887. {
  1888. struct device *dev = &adev->dev;
  1889. struct pl022_ssp_controller *platform_info =
  1890. dev_get_platdata(&adev->dev);
  1891. struct spi_master *master;
  1892. struct pl022 *pl022 = NULL; /*Data for this driver */
  1893. int status = 0;
  1894. dev_info(&adev->dev,
  1895. "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
  1896. if (!platform_info && IS_ENABLED(CONFIG_OF))
  1897. platform_info = pl022_platform_data_dt_get(dev);
  1898. if (!platform_info) {
  1899. dev_err(dev, "probe: no platform data defined\n");
  1900. return -ENODEV;
  1901. }
  1902. /* Allocate master with space for data */
  1903. master = spi_alloc_master(dev, sizeof(struct pl022));
  1904. if (master == NULL) {
  1905. dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
  1906. return -ENOMEM;
  1907. }
  1908. pl022 = spi_master_get_devdata(master);
  1909. pl022->master = master;
  1910. pl022->master_info = platform_info;
  1911. pl022->adev = adev;
  1912. pl022->vendor = id->data;
  1913. /*
  1914. * Bus Number Which has been Assigned to this SSP controller
  1915. * on this board
  1916. */
  1917. master->bus_num = platform_info->bus_id;
  1918. master->cleanup = pl022_cleanup;
  1919. master->setup = pl022_setup;
  1920. master->auto_runtime_pm = true;
  1921. master->transfer_one_message = pl022_transfer_one_message;
  1922. master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
  1923. master->rt = platform_info->rt;
  1924. master->dev.of_node = dev->of_node;
  1925. master->use_gpio_descriptors = true;
  1926. /*
  1927. * Supports mode 0-3, loopback, and active low CS. Transfers are
  1928. * always MS bit first on the original pl022.
  1929. */
  1930. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
  1931. if (pl022->vendor->extended_cr)
  1932. master->mode_bits |= SPI_LSB_FIRST;
  1933. dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
  1934. status = amba_request_regions(adev, NULL);
  1935. if (status)
  1936. goto err_no_ioregion;
  1937. pl022->phybase = adev->res.start;
  1938. pl022->virtbase = devm_ioremap(dev, adev->res.start,
  1939. resource_size(&adev->res));
  1940. if (pl022->virtbase == NULL) {
  1941. status = -ENOMEM;
  1942. goto err_no_ioremap;
  1943. }
  1944. dev_info(&adev->dev, "mapped registers from %pa to %p\n",
  1945. &adev->res.start, pl022->virtbase);
  1946. pl022->clk = devm_clk_get(&adev->dev, NULL);
  1947. if (IS_ERR(pl022->clk)) {
  1948. status = PTR_ERR(pl022->clk);
  1949. dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
  1950. goto err_no_clk;
  1951. }
  1952. status = clk_prepare_enable(pl022->clk);
  1953. if (status) {
  1954. dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
  1955. goto err_no_clk_en;
  1956. }
  1957. /* Initialize transfer pump */
  1958. tasklet_init(&pl022->pump_transfers, pump_transfers,
  1959. (unsigned long)pl022);
  1960. /* Disable SSP */
  1961. writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
  1962. SSP_CR1(pl022->virtbase));
  1963. load_ssp_default_config(pl022);
  1964. status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
  1965. 0, "pl022", pl022);
  1966. if (status < 0) {
  1967. dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
  1968. goto err_no_irq;
  1969. }
  1970. /* Get DMA channels, try autoconfiguration first */
  1971. status = pl022_dma_autoprobe(pl022);
  1972. if (status == -EPROBE_DEFER) {
  1973. dev_dbg(dev, "deferring probe to get DMA channel\n");
  1974. goto err_no_irq;
  1975. }
  1976. /* If that failed, use channels from platform_info */
  1977. if (status == 0)
  1978. platform_info->enable_dma = 1;
  1979. else if (platform_info->enable_dma) {
  1980. status = pl022_dma_probe(pl022);
  1981. if (status != 0)
  1982. platform_info->enable_dma = 0;
  1983. }
  1984. /* Register with the SPI framework */
  1985. amba_set_drvdata(adev, pl022);
  1986. status = devm_spi_register_master(&adev->dev, master);
  1987. if (status != 0) {
  1988. dev_err(&adev->dev,
  1989. "probe - problem registering spi master\n");
  1990. goto err_spi_register;
  1991. }
  1992. dev_dbg(dev, "probe succeeded\n");
  1993. /* let runtime pm put suspend */
  1994. if (platform_info->autosuspend_delay > 0) {
  1995. dev_info(&adev->dev,
  1996. "will use autosuspend for runtime pm, delay %dms\n",
  1997. platform_info->autosuspend_delay);
  1998. pm_runtime_set_autosuspend_delay(dev,
  1999. platform_info->autosuspend_delay);
  2000. pm_runtime_use_autosuspend(dev);
  2001. }
  2002. pm_runtime_put(dev);
  2003. return 0;
  2004. err_spi_register:
  2005. if (platform_info->enable_dma)
  2006. pl022_dma_remove(pl022);
  2007. err_no_irq:
  2008. clk_disable_unprepare(pl022->clk);
  2009. err_no_clk_en:
  2010. err_no_clk:
  2011. err_no_ioremap:
  2012. amba_release_regions(adev);
  2013. err_no_ioregion:
  2014. spi_master_put(master);
  2015. return status;
  2016. }
  2017. static void
  2018. pl022_remove(struct amba_device *adev)
  2019. {
  2020. struct pl022 *pl022 = amba_get_drvdata(adev);
  2021. if (!pl022)
  2022. return;
  2023. /*
  2024. * undo pm_runtime_put() in probe. I assume that we're not
  2025. * accessing the primecell here.
  2026. */
  2027. pm_runtime_get_noresume(&adev->dev);
  2028. load_ssp_default_config(pl022);
  2029. if (pl022->master_info->enable_dma)
  2030. pl022_dma_remove(pl022);
  2031. clk_disable_unprepare(pl022->clk);
  2032. amba_release_regions(adev);
  2033. tasklet_disable(&pl022->pump_transfers);
  2034. }
  2035. #ifdef CONFIG_PM_SLEEP
  2036. static int pl022_suspend(struct device *dev)
  2037. {
  2038. struct pl022 *pl022 = dev_get_drvdata(dev);
  2039. int ret;
  2040. ret = spi_master_suspend(pl022->master);
  2041. if (ret)
  2042. return ret;
  2043. ret = pm_runtime_force_suspend(dev);
  2044. if (ret) {
  2045. spi_master_resume(pl022->master);
  2046. return ret;
  2047. }
  2048. pinctrl_pm_select_sleep_state(dev);
  2049. dev_dbg(dev, "suspended\n");
  2050. return 0;
  2051. }
  2052. static int pl022_resume(struct device *dev)
  2053. {
  2054. struct pl022 *pl022 = dev_get_drvdata(dev);
  2055. int ret;
  2056. ret = pm_runtime_force_resume(dev);
  2057. if (ret)
  2058. dev_err(dev, "problem resuming\n");
  2059. /* Start the queue running */
  2060. ret = spi_master_resume(pl022->master);
  2061. if (!ret)
  2062. dev_dbg(dev, "resumed\n");
  2063. return ret;
  2064. }
  2065. #endif
  2066. #ifdef CONFIG_PM
  2067. static int pl022_runtime_suspend(struct device *dev)
  2068. {
  2069. struct pl022 *pl022 = dev_get_drvdata(dev);
  2070. clk_disable_unprepare(pl022->clk);
  2071. pinctrl_pm_select_idle_state(dev);
  2072. return 0;
  2073. }
  2074. static int pl022_runtime_resume(struct device *dev)
  2075. {
  2076. struct pl022 *pl022 = dev_get_drvdata(dev);
  2077. pinctrl_pm_select_default_state(dev);
  2078. clk_prepare_enable(pl022->clk);
  2079. return 0;
  2080. }
  2081. #endif
  2082. static const struct dev_pm_ops pl022_dev_pm_ops = {
  2083. SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
  2084. SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
  2085. };
  2086. static struct vendor_data vendor_arm = {
  2087. .fifodepth = 8,
  2088. .max_bpw = 16,
  2089. .unidir = false,
  2090. .extended_cr = false,
  2091. .pl023 = false,
  2092. .loopback = true,
  2093. .internal_cs_ctrl = false,
  2094. };
  2095. static struct vendor_data vendor_st = {
  2096. .fifodepth = 32,
  2097. .max_bpw = 32,
  2098. .unidir = false,
  2099. .extended_cr = true,
  2100. .pl023 = false,
  2101. .loopback = true,
  2102. .internal_cs_ctrl = false,
  2103. };
  2104. static struct vendor_data vendor_st_pl023 = {
  2105. .fifodepth = 32,
  2106. .max_bpw = 32,
  2107. .unidir = false,
  2108. .extended_cr = true,
  2109. .pl023 = true,
  2110. .loopback = false,
  2111. .internal_cs_ctrl = false,
  2112. };
  2113. static struct vendor_data vendor_lsi = {
  2114. .fifodepth = 8,
  2115. .max_bpw = 16,
  2116. .unidir = false,
  2117. .extended_cr = false,
  2118. .pl023 = false,
  2119. .loopback = true,
  2120. .internal_cs_ctrl = true,
  2121. };
  2122. static const struct amba_id pl022_ids[] = {
  2123. {
  2124. /*
  2125. * ARM PL022 variant, this has a 16bit wide
  2126. * and 8 locations deep TX/RX FIFO
  2127. */
  2128. .id = 0x00041022,
  2129. .mask = 0x000fffff,
  2130. .data = &vendor_arm,
  2131. },
  2132. {
  2133. /*
  2134. * ST Micro derivative, this has 32bit wide
  2135. * and 32 locations deep TX/RX FIFO
  2136. */
  2137. .id = 0x01080022,
  2138. .mask = 0xffffffff,
  2139. .data = &vendor_st,
  2140. },
  2141. {
  2142. /*
  2143. * ST-Ericsson derivative "PL023" (this is not
  2144. * an official ARM number), this is a PL022 SSP block
  2145. * stripped to SPI mode only, it has 32bit wide
  2146. * and 32 locations deep TX/RX FIFO but no extended
  2147. * CR0/CR1 register
  2148. */
  2149. .id = 0x00080023,
  2150. .mask = 0xffffffff,
  2151. .data = &vendor_st_pl023,
  2152. },
  2153. {
  2154. /*
  2155. * PL022 variant that has a chip select control register whih
  2156. * allows control of 5 output signals nCS[0:4].
  2157. */
  2158. .id = 0x000b6022,
  2159. .mask = 0x000fffff,
  2160. .data = &vendor_lsi,
  2161. },
  2162. { 0, 0 },
  2163. };
  2164. MODULE_DEVICE_TABLE(amba, pl022_ids);
  2165. static struct amba_driver pl022_driver = {
  2166. .drv = {
  2167. .name = "ssp-pl022",
  2168. .pm = &pl022_dev_pm_ops,
  2169. },
  2170. .id_table = pl022_ids,
  2171. .probe = pl022_probe,
  2172. .remove = pl022_remove,
  2173. };
  2174. static int __init pl022_init(void)
  2175. {
  2176. return amba_driver_register(&pl022_driver);
  2177. }
  2178. subsys_initcall(pl022_init);
  2179. static void __exit pl022_exit(void)
  2180. {
  2181. amba_driver_unregister(&pl022_driver);
  2182. }
  2183. module_exit(pl022_exit);
  2184. MODULE_AUTHOR("Linus Walleij <[email protected]>");
  2185. MODULE_DESCRIPTION("PL022 SSP Controller Driver");
  2186. MODULE_LICENSE("GPL");